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cgu.csv

This commit is contained in:
Michael Ossmann 2012-09-27 11:33:53 -06:00 committed by Piotr Esden-Tempski
parent 07ee98420c
commit 0f7e6cf54d
2 changed files with 142 additions and 1 deletions
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2
scripts/data/lpc43xx/README
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These files contain information derived from the LPC43xx data sheet (UM10503).
These files contain information derived from the LPC43xx user manual (UM10503).
They are intended to be used by scripts for the generation of header files and
functions.

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scripts/data/lpc43xx/cgu.csv Normal file
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CGU_FREQ_MON,0,9,RCNT,9-bit reference clock-counter value,0,rw
CGU_FREQ_MON,9,14,FCNT,14-bit selected clock-counter value,0,r
CGU_FREQ_MON,23,1,MEAS,Measure frequency,0,rw
CGU_FREQ_MON,24,5,CLK_SEL,Clock-source selection for the clock to be measured,0,rw
CGU_XTAL_OSC_CTRL,0,1,ENABLE,Oscillator-pad enable,1,rw
CGU_XTAL_OSC_CTRL,1,1,BYPASS,Configure crystal operation or external-clock input pin XTAL1,0,rw
CGU_XTAL_OSC_CTRL,2,1,HF,Select frequency range,1,rw
CGU_PLL0USB_STAT,0,1,LOCK,PLL0 lock indicator,0,r
CGU_PLL0USB_STAT,1,1,FR,PLL0 free running indicator,0,r
CGU_PLL0USB_CTRL,0,1,PD,PLL0 power down,1,rw
CGU_PLL0USB_CTRL,1,1,BYPASS,Input clock bypass control,1,rw
CGU_PLL0USB_CTRL,2,1,DIRECTI,PLL0 direct input,0,rw
CGU_PLL0USB_CTRL,4,1,CLKEN,PLL0 clock enable,0,rw
CGU_PLL0USB_CTRL,6,1,FRM,Free running mode,0,rw
CGU_PLL0USB_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_PLL0USB_CTRL,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_PLL0USB_MDIV,0,17,MDEC,Decoded M-divider coefficient value,0x5B6A,rw
CGU_PLL0USB_MDIV,17,5,SELP,Bandwidth select P value,0x1C,rw
CGU_PLL0USB_MDIV,22,6,SELI,Bandwidth select I value,0x17,rw
CGU_PLL0USB_MDIV,28,4,SELR,Bandwidth select R value,0x0,rw
CGU_PLL0USB_NP_DIV,0,7,PDEC,Decoded P-divider coefficient value,0x02,rw
CGU_PLL0USB_NP_DIV,12,10,NDEC,Decoded N-divider coefficient value,0xB1,rw
CGU_PLL0AUDIO_STAT,0,1,LOCK,PLL0 lock indicator,0,r
CGU_PLL0AUDIO_STAT,1,1,FR,PLL0 free running indicator,0,r
CGU_PLL0AUDIO_CTRL,0,1,PD,PLL0 power down,1,rw
CGU_PLL0AUDIO_CTRL,1,1,BYPASS,Input clock bypass control,1,rw
CGU_PLL0AUDIO_CTRL,2,1,DIRECTI,PLL0 direct input,0,rw
CGU_PLL0AUDIO_CTRL,3,1,DIRECTO,PLL0 direct output,0,rw
CGU_PLL0AUDIO_CTRL,4,1,CLKEN,PLL0 clock enable,0,rw
CGU_PLL0AUDIO_CTRL,6,1,FRM,Free running mode,0,rw
CGU_PLL0AUDIO_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_PLL0AUDIO_CTRL,12,1,PLLFRACT_REQ,Fractional PLL word write request,0,rw
CGU_PLL0AUDIO_CTRL,13,1,SEL_EXT,Select fractional divider,0,rw
CGU_PLL0AUDIO_CTRL,14,1,MOD_PD,Sigma-Delta modulator power-down,1,rw
CGU_PLL0AUDIO_CTRL,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_PLL0AUDIO_MDIV,0,17,MDEC,Decoded M-divider coefficient value,0x5B6A,rw
CGU_PLL0AUDIO_NP_DIV,0,7,PDEC,Decoded P-divider coefficient value,0x02,rw
CGU_PLL0AUDIO_NP_DIV,12,10,NDEC,Decoded N-divider coefficient value,0xB1,rw
CGU_PLLAUDIO_FRAC,0,22,PLLFRACT_CTRL,PLL fractional divider control word,0x00,rw
CGU_PLL1_STAT,0,1,LOCK,PLL1 lock indicator,0,r
CGU_PLL1_CTRL,0,1,PD,PLL1 power down,1,rw
CGU_PLL1_CTRL,1,1,BYPASS,Input clock bypass control,1,rw
CGU_PLL1_CTRL,6,1,FBSEL,PLL feedback select,0,rw
CGU_PLL1_CTRL,7,1,DIRECT,PLL direct CCO output,0,rw
CGU_PLL1_CTRL,8,2,PSEL,Post-divider division ratio P,0x1,rw
CGU_PLL1_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_PLL1_CTRL,12,2,NSEL,Pre-divider division ratio N,0x2,rw
CGU_PLL1_CTRL,16,8,MSEL,Feedback-divider division ratio (M),0x18,rw
CGU_PLL1_CTRL,24,5,CLK_SEL,Clock-source selection,0x01,rw
CGU_IDIVA_CTRL,0,1,PD,Integer divider power down,0,rw
CGU_IDIVA_CTRL,2,2,IDIV,Integer divider A divider value (1/(IDIV + 1)),0x0,rw
CGU_IDIVA_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_IDIVA_CTRL,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_IDIVB_CTRL,0,1,PD,Integer divider power down,0,rw
CGU_IDIVB_CTRL,2,4,IDIV,Integer divider B divider value (1/(IDIV + 1)),0x0,rw
CGU_IDIVB_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_IDIVB_CTRL,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_IDIVC_CTRL,0,1,PD,Integer divider power down,0,rw
CGU_IDIVC_CTRL,2,4,IDIV,Integer divider C divider value (1/(IDIV + 1)),0x0,rw
CGU_IDIVC_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_IDIVC_CTRL,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_IDIVD_CTRL,0,1,PD,Integer divider power down,0,rw
CGU_IDIVD_CTRL,2,4,IDIV,Integer divider D divider value (1/(IDIV + 1)),0x0,rw
CGU_IDIVD_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_IDIVD_CTRL,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_IDIVE_CTRL,0,1,PD,Integer divider power down,0,rw
CGU_IDIVE_CTRL,2,8,IDIV,Integer divider E divider value (1/(IDIV + 1)),0x00,rw
CGU_IDIVE_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_IDIVE_CTRL,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_SAFE_CLK,0,1,PD,Output stage power down,0,r
CGU_BASE_SAFE_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,r
CGU_BASE_SAFE_CLK,24,5,CLK_SEL,Clock source selection,0x01,r
CGU_BASE_USB0_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_USB0_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_USB0_CLK,24,5,CLK_SEL,Clock source selection,0x07,rw
CGU_BASE_PERIPH_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_PERIPH_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_PERIPH_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_USB1_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_USB1_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_USB1_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_M4_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_M4_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_M4_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_SPIFI_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_SPIFI_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_SPIFI_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_SPI_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_SPI_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_SPI_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_PHY_RX_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_PHY_RX_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_PHY_RX_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_PHY_TX_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_PHY_TX_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_PHY_TX_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_APB1_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_APB1_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_APB1_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_APB3_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_APB3_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_APB3_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_LCD_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_LCD_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_LCD_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_VADC_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_VADC_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_VADC_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_SDIO_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_SDIO_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_SDIO_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_SSP0_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_SSP0_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_SSP0_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_SSP1_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_SSP1_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_SSP1_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_UART0_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_UART0_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_UART0_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_UART1_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_UART1_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_UART1_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_UART2_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_UART2_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_UART2_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_UART3_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_UART3_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_UART3_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_OUT_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_OUT_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_OUT_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_APLL_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_APLL_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_APLL_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_CGU_OUT0_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_CGU_OUT0_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_CGU_OUT0_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_CGU_OUT1_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_CGU_OUT1_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_CGU_OUT1_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
1 CGU_FREQ_MON 0 9 RCNT 9-bit reference clock-counter value 0 rw
2 CGU_FREQ_MON 9 14 FCNT 14-bit selected clock-counter value 0 r
3 CGU_FREQ_MON 23 1 MEAS Measure frequency 0 rw
4 CGU_FREQ_MON 24 5 CLK_SEL Clock-source selection for the clock to be measured 0 rw
5 CGU_XTAL_OSC_CTRL 0 1 ENABLE Oscillator-pad enable 1 rw
6 CGU_XTAL_OSC_CTRL 1 1 BYPASS Configure crystal operation or external-clock input pin XTAL1 0 rw
7 CGU_XTAL_OSC_CTRL 2 1 HF Select frequency range 1 rw
8 CGU_PLL0USB_STAT 0 1 LOCK PLL0 lock indicator 0 r
9 CGU_PLL0USB_STAT 1 1 FR PLL0 free running indicator 0 r
10 CGU_PLL0USB_CTRL 0 1 PD PLL0 power down 1 rw
11 CGU_PLL0USB_CTRL 1 1 BYPASS Input clock bypass control 1 rw
12 CGU_PLL0USB_CTRL 2 1 DIRECTI PLL0 direct input 0 rw
13 CGU_PLL0USB_CTRL 4 1 CLKEN PLL0 clock enable 0 rw
14 CGU_PLL0USB_CTRL 6 1 FRM Free running mode 0 rw
15 CGU_PLL0USB_CTRL 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
16 CGU_PLL0USB_CTRL 24 5 CLK_SEL Clock source selection 0x01 rw
17 CGU_PLL0USB_MDIV 0 17 MDEC Decoded M-divider coefficient value 0x5B6A rw
18 CGU_PLL0USB_MDIV 17 5 SELP Bandwidth select P value 0x1C rw
19 CGU_PLL0USB_MDIV 22 6 SELI Bandwidth select I value 0x17 rw
20 CGU_PLL0USB_MDIV 28 4 SELR Bandwidth select R value 0x0 rw
21 CGU_PLL0USB_NP_DIV 0 7 PDEC Decoded P-divider coefficient value 0x02 rw
22 CGU_PLL0USB_NP_DIV 12 10 NDEC Decoded N-divider coefficient value 0xB1 rw
23 CGU_PLL0AUDIO_STAT 0 1 LOCK PLL0 lock indicator 0 r
24 CGU_PLL0AUDIO_STAT 1 1 FR PLL0 free running indicator 0 r
25 CGU_PLL0AUDIO_CTRL 0 1 PD PLL0 power down 1 rw
26 CGU_PLL0AUDIO_CTRL 1 1 BYPASS Input clock bypass control 1 rw
27 CGU_PLL0AUDIO_CTRL 2 1 DIRECTI PLL0 direct input 0 rw
28 CGU_PLL0AUDIO_CTRL 3 1 DIRECTO PLL0 direct output 0 rw
29 CGU_PLL0AUDIO_CTRL 4 1 CLKEN PLL0 clock enable 0 rw
30 CGU_PLL0AUDIO_CTRL 6 1 FRM Free running mode 0 rw
31 CGU_PLL0AUDIO_CTRL 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
32 CGU_PLL0AUDIO_CTRL 12 1 PLLFRACT_REQ Fractional PLL word write request 0 rw
33 CGU_PLL0AUDIO_CTRL 13 1 SEL_EXT Select fractional divider 0 rw
34 CGU_PLL0AUDIO_CTRL 14 1 MOD_PD Sigma-Delta modulator power-down 1 rw
35 CGU_PLL0AUDIO_CTRL 24 5 CLK_SEL Clock source selection 0x01 rw
36 CGU_PLL0AUDIO_MDIV 0 17 MDEC Decoded M-divider coefficient value 0x5B6A rw
37 CGU_PLL0AUDIO_NP_DIV 0 7 PDEC Decoded P-divider coefficient value 0x02 rw
38 CGU_PLL0AUDIO_NP_DIV 12 10 NDEC Decoded N-divider coefficient value 0xB1 rw
39 CGU_PLLAUDIO_FRAC 0 22 PLLFRACT_CTRL PLL fractional divider control word 0x00 rw
40 CGU_PLL1_STAT 0 1 LOCK PLL1 lock indicator 0 r
41 CGU_PLL1_CTRL 0 1 PD PLL1 power down 1 rw
42 CGU_PLL1_CTRL 1 1 BYPASS Input clock bypass control 1 rw
43 CGU_PLL1_CTRL 6 1 FBSEL PLL feedback select 0 rw
44 CGU_PLL1_CTRL 7 1 DIRECT PLL direct CCO output 0 rw
45 CGU_PLL1_CTRL 8 2 PSEL Post-divider division ratio P 0x1 rw
46 CGU_PLL1_CTRL 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
47 CGU_PLL1_CTRL 12 2 NSEL Pre-divider division ratio N 0x2 rw
48 CGU_PLL1_CTRL 16 8 MSEL Feedback-divider division ratio (M) 0x18 rw
49 CGU_PLL1_CTRL 24 5 CLK_SEL Clock-source selection 0x01 rw
50 CGU_IDIVA_CTRL 0 1 PD Integer divider power down 0 rw
51 CGU_IDIVA_CTRL 2 2 IDIV Integer divider A divider value (1/(IDIV + 1)) 0x0 rw
52 CGU_IDIVA_CTRL 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
53 CGU_IDIVA_CTRL 24 5 CLK_SEL Clock source selection 0x01 rw
54 CGU_IDIVB_CTRL 0 1 PD Integer divider power down 0 rw
55 CGU_IDIVB_CTRL 2 4 IDIV Integer divider B divider value (1/(IDIV + 1)) 0x0 rw
56 CGU_IDIVB_CTRL 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
57 CGU_IDIVB_CTRL 24 5 CLK_SEL Clock source selection 0x01 rw
58 CGU_IDIVC_CTRL 0 1 PD Integer divider power down 0 rw
59 CGU_IDIVC_CTRL 2 4 IDIV Integer divider C divider value (1/(IDIV + 1)) 0x0 rw
60 CGU_IDIVC_CTRL 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
61 CGU_IDIVC_CTRL 24 5 CLK_SEL Clock source selection 0x01 rw
62 CGU_IDIVD_CTRL 0 1 PD Integer divider power down 0 rw
63 CGU_IDIVD_CTRL 2 4 IDIV Integer divider D divider value (1/(IDIV + 1)) 0x0 rw
64 CGU_IDIVD_CTRL 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
65 CGU_IDIVD_CTRL 24 5 CLK_SEL Clock source selection 0x01 rw
66 CGU_IDIVE_CTRL 0 1 PD Integer divider power down 0 rw
67 CGU_IDIVE_CTRL 2 8 IDIV Integer divider E divider value (1/(IDIV + 1)) 0x00 rw
68 CGU_IDIVE_CTRL 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
69 CGU_IDIVE_CTRL 24 5 CLK_SEL Clock source selection 0x01 rw
70 CGU_BASE_SAFE_CLK 0 1 PD Output stage power down 0 r
71 CGU_BASE_SAFE_CLK 11 1 AUTOBLOCK Block clock automatically during frequency change 0 r
72 CGU_BASE_SAFE_CLK 24 5 CLK_SEL Clock source selection 0x01 r
73 CGU_BASE_USB0_CLK 0 1 PD Output stage power down 0 rw
74 CGU_BASE_USB0_CLK 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
75 CGU_BASE_USB0_CLK 24 5 CLK_SEL Clock source selection 0x07 rw
76 CGU_BASE_PERIPH_CLK 0 1 PD Output stage power down 0 rw
77 CGU_BASE_PERIPH_CLK 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
78 CGU_BASE_PERIPH_CLK 24 5 CLK_SEL Clock source selection 0x01 rw
79 CGU_BASE_USB1_CLK 0 1 PD Output stage power down 0 rw
80 CGU_BASE_USB1_CLK 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
81 CGU_BASE_USB1_CLK 24 5 CLK_SEL Clock source selection 0x01 rw
82 CGU_BASE_M4_CLK 0 1 PD Output stage power down 0 rw
83 CGU_BASE_M4_CLK 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
84 CGU_BASE_M4_CLK 24 5 CLK_SEL Clock source selection 0x01 rw
85 CGU_BASE_SPIFI_CLK 0 1 PD Output stage power down 0 rw
86 CGU_BASE_SPIFI_CLK 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
87 CGU_BASE_SPIFI_CLK 24 5 CLK_SEL Clock source selection 0x01 rw
88 CGU_BASE_SPI_CLK 0 1 PD Output stage power down 0 rw
89 CGU_BASE_SPI_CLK 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
90 CGU_BASE_SPI_CLK 24 5 CLK_SEL Clock source selection 0x01 rw
91 CGU_BASE_PHY_RX_CLK 0 1 PD Output stage power down 0 rw
92 CGU_BASE_PHY_RX_CLK 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
93 CGU_BASE_PHY_RX_CLK 24 5 CLK_SEL Clock source selection 0x01 rw
94 CGU_BASE_PHY_TX_CLK 0 1 PD Output stage power down 0 rw
95 CGU_BASE_PHY_TX_CLK 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
96 CGU_BASE_PHY_TX_CLK 24 5 CLK_SEL Clock source selection 0x01 rw
97 CGU_BASE_APB1_CLK 0 1 PD Output stage power down 0 rw
98 CGU_BASE_APB1_CLK 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
99 CGU_BASE_APB1_CLK 24 5 CLK_SEL Clock source selection 0x01 rw
100 CGU_BASE_APB3_CLK 0 1 PD Output stage power down 0 rw
101 CGU_BASE_APB3_CLK 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
102 CGU_BASE_APB3_CLK 24 5 CLK_SEL Clock source selection 0x01 rw
103 CGU_BASE_LCD_CLK 0 1 PD Output stage power down 0 rw
104 CGU_BASE_LCD_CLK 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
105 CGU_BASE_LCD_CLK 24 5 CLK_SEL Clock source selection 0x01 rw
106 CGU_BASE_VADC_CLK 0 1 PD Output stage power down 0 rw
107 CGU_BASE_VADC_CLK 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
108 CGU_BASE_VADC_CLK 24 5 CLK_SEL Clock source selection 0x01 rw
109 CGU_BASE_SDIO_CLK 0 1 PD Output stage power down 0 rw
110 CGU_BASE_SDIO_CLK 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
111 CGU_BASE_SDIO_CLK 24 5 CLK_SEL Clock source selection 0x01 rw
112 CGU_BASE_SSP0_CLK 0 1 PD Output stage power down 0 rw
113 CGU_BASE_SSP0_CLK 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
114 CGU_BASE_SSP0_CLK 24 5 CLK_SEL Clock source selection 0x01 rw
115 CGU_BASE_SSP1_CLK 0 1 PD Output stage power down 0 rw
116 CGU_BASE_SSP1_CLK 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
117 CGU_BASE_SSP1_CLK 24 5 CLK_SEL Clock source selection 0x01 rw
118 CGU_BASE_UART0_CLK 0 1 PD Output stage power down 0 rw
119 CGU_BASE_UART0_CLK 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
120 CGU_BASE_UART0_CLK 24 5 CLK_SEL Clock source selection 0x01 rw
121 CGU_BASE_UART1_CLK 0 1 PD Output stage power down 0 rw
122 CGU_BASE_UART1_CLK 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
123 CGU_BASE_UART1_CLK 24 5 CLK_SEL Clock source selection 0x01 rw
124 CGU_BASE_UART2_CLK 0 1 PD Output stage power down 0 rw
125 CGU_BASE_UART2_CLK 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
126 CGU_BASE_UART2_CLK 24 5 CLK_SEL Clock source selection 0x01 rw
127 CGU_BASE_UART3_CLK 0 1 PD Output stage power down 0 rw
128 CGU_BASE_UART3_CLK 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
129 CGU_BASE_UART3_CLK 24 5 CLK_SEL Clock source selection 0x01 rw
130 CGU_BASE_OUT_CLK 0 1 PD Output stage power down 0 rw
131 CGU_BASE_OUT_CLK 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
132 CGU_BASE_OUT_CLK 24 5 CLK_SEL Clock source selection 0x01 rw
133 CGU_BASE_APLL_CLK 0 1 PD Output stage power down 0 rw
134 CGU_BASE_APLL_CLK 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
135 CGU_BASE_APLL_CLK 24 5 CLK_SEL Clock source selection 0x01 rw
136 CGU_BASE_CGU_OUT0_CLK 0 1 PD Output stage power down 0 rw
137 CGU_BASE_CGU_OUT0_CLK 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
138 CGU_BASE_CGU_OUT0_CLK 24 5 CLK_SEL Clock source selection 0x01 rw
139 CGU_BASE_CGU_OUT1_CLK 0 1 PD Output stage power down 0 rw
140 CGU_BASE_CGU_OUT1_CLK 11 1 AUTOBLOCK Block clock automatically during frequency change 0 rw
141 CGU_BASE_CGU_OUT1_CLK 24 5 CLK_SEL Clock source selection 0x01 rw