STM32H7: Add QSPI Defines
Move the STM32F4 QuadSPI peripheral defines to the common folder as the F4 and H7 variants of the IP share almost all the same bits. For those bits that are separate put them into their own headers.
This commit is contained in:
Matt Walker
Karl Palsson
parent
7df670b6aa
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/*
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* This file is part of the libopencm3 project.
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*
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA quadspi.h
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The order of header inclusion is important. quadspi.h includes the device
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specific memorymap.h header before including this header file.*/
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/** @cond */
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#ifdef LIBOPENCM3_QUADSPI_H
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/** @endcond */
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#ifndef LIBOPENCM3_QUADSPI_COMMON_V1_H
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#define LIBOPENCM3_QUADSPI_COMMON_V1_H
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/* QUADSPI Control register */
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#define QUADSPI_CR MMIO32(QUADSPI_BASE + 0x0U)
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#define QUADSPI_CR_PRESCALE_MASK 0xff
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#define QUADSPI_CR_PRESCALE_SHIFT 24
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#define QUADSPI_CR_PMM (1 << 23)
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#define QUADSPI_CR_APMS (1 << 22)
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/* bit 21 is reserved */
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#define QUADSPI_CR_TOIE (1 << 20)
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#define QUADSPI_CR_SMIE (1 << 19)
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#define QUADSPI_CR_FTIE (1 << 18)
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#define QUADSPI_CR_TCIE (1 << 17)
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#define QUADSPI_CR_TEIE (1 << 16)
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/* bits 15:13 reserved */
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#define QUADSPI_CR_FTHRES_MASK 0x1f
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#define QUADSPI_CR_FTHRES_SHIFT 8
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#define QUADSPI_CR_FSEL (1 << 7)
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#define QUADSPI_CR_DFM (1 << 6)
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/* bit 5 reserved */
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#define QUADSPI_CR_SSHIFT (1 << 4)
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#define QUADSPI_CR_TCEN (1 << 3)
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/* bit 2 reserved on h7, DMAEN on f4 */
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#define QUADSPI_CR_ABORT (1 << 1)
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#define QUADSPI_CR_EN (1 << 0)
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/* QUADSPI Device Configuration */
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#define QUADSPI_DCR MMIO32(QUADSPI_BASE + 0x4U)
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/* bits 31:21 reserved */
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#define QUADSPI_DCR_FSIZE_MASK 0x1f
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#define QUADSPI_DCR_FSIZE_SHIFT 16
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/* bits 15:11 reserved */
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#define QUADSPI_DCR_CSHT_MASK 0x7
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#define QUADSPI_DCR_CSHT_SHIFT 8
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/* bits 7:1 reserved */
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#define QUADSPI_DCR_CKMODE (1 << 0)
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/* QUADSPI Status Register */
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#define QUADSPI_SR MMIO32(QUADSPI_BASE + 0x8U)
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/* bits 31:14 reserved */
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#define QUADSPI_SR_FLEVEL_MASK 0x3f
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#define QUADSPI_SR_FLEVEL_SHIFT 8
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/* bits 7:6 reserved */
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#define QUADSPI_SR_BUSY (1 << 5)
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#define QUADSPI_SR_TOF (1 << 4)
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#define QUADSPI_SR_SMF (1 << 3)
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#define QUADSPI_SR_FTF (1 << 2)
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#define QUADSPI_SR_TCF (1 << 1)
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#define QUADSPI_SR_TEF (1 << 0)
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/* QUADSPI Flag Clear Register */
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#define QUADSPI_FCR MMIO32(QUADSPI_BASE + 0xCU)
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/* bits 31:5 reserved */
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#define QUADSPI_FCR_CTOF (1 << 4)
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#define QUADSPI_FCR_CSMF (1 << 3)
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/* bit 2 reserved */
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#define QUADSPI_FCR_CTCF (1 << 1)
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#define QUADSPI_FCR_CTEF (1 << 0)
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/* QUADSPI Data Length Register */
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#define QUADSPI_DLR MMIO32(QUADSPI_BASE + 0x10U)
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/* QUADSPI Communication Configuration Register */
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#define QUADSPI_CCR MMIO32(QUADSPI_BASE + 0x14U)
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#define QUADSPI_CCR_DDRM (1 << 31)
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#define QUADSPI_CCR_DHHC (1 << 30)
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/* bit 29 reserved on F4, FRCM on H7 */
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#define QUADSPI_CCR_SIOO (1 << 28)
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#define QUADSPI_CCR_FMODE_MASK 0x3
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#define QUADSPI_CCR_FMODE_SHIFT 26
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#define QUADSPI_CCR_DMODE_MASK 0x3
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#define QUADSPI_CCR_DMODE_SHIFT 24
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/* bit 23 reserved */
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#define QUADSPI_CCR_DCYC_MASK 0x1f
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#define QUADSPI_CCR_DCYC_SHIFT 18
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#define QUADSPI_CCR_ABSIZE_MASK 0x3
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#define QUADSPI_CCR_ABSIZE_SHIFT 16
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#define QUADSPI_CCR_ABMODE_MASK 0x3
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#define QUADSPI_CCR_ABMODE_SHIFT 14
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#define QUADSPI_CCR_ADSIZE_MASK 0x3
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#define QUADSPI_CCR_ADSIZE_SHIFT 12
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#define QUADSPI_CCR_ADMODE_MASK 0x3
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#define QUADSPI_CCR_ADMODE_SHIFT 10
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#define QUADSPI_CCR_IMODE_MASK 0x3
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#define QUADSPI_CCR_IMODE_SHIFT 8
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#define QUADSPI_CCR_INST_MASK 0xff
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#define QUADSPI_CCR_INST_SHIFT 0
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/* MODE values */
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#define QUADSPI_CCR_MODE_NONE 0
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#define QUADSPI_CCR_MODE_1LINE 1
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#define QUADSPI_CCR_MODE_2LINE 2
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#define QUADSPI_CCR_MODE_4LINE 3
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/* FMODE values */
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#define QUADSPI_CCR_FMODE_IWRITE 0
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#define QUADSPI_CCR_FMODE_IREAD 1
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#define QUADSPI_CCR_FMODE_APOLL 2
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#define QUADSPI_CCR_FMODE_MEMMAP 3
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/* QUADSPI address register */
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#define QUADSPI_AR MMIO32(QUADSPI_BASE + 0x18U)
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/* QUADSPI alternate bytes register */
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#define QUADSPI_ABR MMIO32(QUADSPI_BASE + 0x1CU)
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/* QUADSPI data register */
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#define QUADSPI_DR MMIO32(QUADSPI_BASE + 0x20U)
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/* BYTE addressable version for fetching bytes from the interface */
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#define QUADSPI_BYTE_DR MMIO8(QUADSPI_BASE + 0x20U)
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/* QUADSPI polling status */
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#define QUADSPI_PSMKR MMIO32(QUADSPI_BASE + 0x24U)
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/* QUADSPI polling status match */
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#define QUADSPI_PSMAR MMIO32(QUADSPI_BASE + 0x28U)
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/* QUADSPI polling interval register */
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#define QUADSPI_PIR MMIO32(QUADSPI_BASE + 0x2CU)
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/* QUADSPI low power timeout */
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#define QUADSPI_LPTR MMIO32(QUADSPI_BASE + 0x30U
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#endif
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/** @cond */
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#else
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#warning "quadspi_common_v1.h should not be included directly, only via quadspi.h"
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#endif
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/** @endcond */
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@ -20,140 +20,12 @@
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*
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*/
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#ifndef LIBOPENCM3_QUADSPI_H
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#define LIBOPENCM3_QUADSPI_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/stm32/common/quadspi_common_v1.h>
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/* QUADSPI Control register */
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#define QUADSPI_CR MMIO32(QUADSPI_BASE + 0x0U)
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#define QUADSPI_CR_PRESCALE_MASK 0xff
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#define QUADSPI_CR_PRESCALE_SHIFT 24
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#define QUADSPI_CR_PMM (1 << 23)
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#define QUADSPI_CR_APMS (1 << 22)
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/* bit 21 is reserved */
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#define QUADSPI_CR_TOIE (1 << 20)
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#define QUADSPI_CR_SMIE (1 << 19)
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#define QUADSPI_CR_FTIE (1 << 18)
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#define QUADSPI_CR_TCIE (1 << 17)
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#define QUADSPI_CR_TEIE (1 << 16)
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/* bits 15:13 reserved */
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#define QUADSPI_CR_FTHRES_MASK 0x1f
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#define QUADSPI_CR_FTHRES_SHIFT 8
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#define QUADSPI_CR_FSEL (1 << 7)
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#define QUADSPI_CR_DFM (1 << 6)
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/* bit 5 reserved */
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#define QUADSPI_CR_SSHIFT (1 << 4)
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#define QUADSPI_CR_TCEN (1 << 3)
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#define QUADSPI_CR_DMAEN (1 << 2)
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#define QUADSPI_CR_ABORT (1 << 1)
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#define QUADSPI_CR_EN (1 << 0)
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/* QUADSPI Device Configuration */
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#define QUADSPI_DCR MMIO32(QUADSPI_BASE + 0x4U)
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/* bits 31:21 reserved */
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#define QUADSPI_DCR_FSIZE_MASK 0x1f
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#define QUADSPI_DCR_FSIZE_SHIFT 16
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/* bits 15:11 reserved */
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#define QUADSPI_DCR_CSHT_MASK 0x7
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#define QUADSPI_DCR_CSHT_SHIFT 8
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/* bits 7:1 reserved */
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#define QUADSPI_DCR_CKMODE (1 << 0)
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/* QUADSPI Status Register */
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#define QUADSPI_SR MMIO32(QUADSPI_BASE + 0x8U)
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/* bits 31:14 reserved */
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#define QUADSPI_SR_FLEVEL_MASK 0x3f
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#define QUADSPI_SR_FLEVEL_SHIFT 8
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/* bits 7:6 reserved */
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#define QUADSPI_SR_BUSY (1 << 5)
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#define QUADSPI_SR_TOF (1 << 4)
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#define QUADSPI_SR_SMF (1 << 3)
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#define QUADSPI_SR_FTF (1 << 2)
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#define QUADSPI_SR_TCF (1 << 1)
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#define QUADSPI_SR_TEF (1 << 0)
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/* QUADSPI Flag Clear Register */
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#define QUADSPI_FCR MMIO32(QUADSPI_BASE + 0xCU)
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/* bits 31:5 reserved */
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#define QUADSPI_FCR_CTOF (1 << 4)
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#define QUADSPI_FCR_CSMF (1 << 3)
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/* bit 2 reserved */
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#define QUADSPI_FCR_CTCF (1 << 1)
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#define QUADSPI_FCR_CTEF (1 << 0)
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/* QUADSPI Data Length Register */
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#define QUADSPI_DLR MMIO32(QUADSPI_BASE + 0x10U)
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/* QUADSPI Communication Configuration Register */
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#define QUADSPI_CCR MMIO32(QUADSPI_BASE + 0x14U)
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#define QUADSPI_CCR_DDRM (1 << 31)
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#define QUADSPI_CCR_DHHC (1 << 30)
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/* bit 29 reserved */
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#define QUADSPI_CCR_SIOO (1 << 28)
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#define QUADSPI_CCR_FMODE_MASK 0x3
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#define QUADSPI_CCR_FMODE_SHIFT 26
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#define QUADSPI_CCR_DMODE_MASK 0x3
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#define QUADSPI_CCR_DMODE_SHIFT 24
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/* bit 23 reserved */
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#define QUADSPI_CCR_DCYC_MASK 0x1f
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#define QUADSPI_CCR_DCYC_SHIFT 18
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#define QUADSPI_CCR_ABSIZE_MASK 0x3
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#define QUADSPI_CCR_ABSIZE_SHIFT 16
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#define QUADSPI_CCR_ABMODE_MASK 0x3
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#define QUADSPI_CCR_ABMODE_SHIFT 14
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#define QUADSPI_CCR_ADSIZE_MASK 0x3
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#define QUADSPI_CCR_ADSIZE_SHIFT 12
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#define QUADSPI_CCR_ADMODE_MASK 0x3
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#define QUADSPI_CCR_ADMODE_SHIFT 10
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#define QUADSPI_CCR_IMODE_MASK 0x3
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#define QUADSPI_CCR_IMODE_SHIFT 8
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#define QUADSPI_CCR_INST_MASK 0xff
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#define QUADSPI_CCR_INST_SHIFT 0
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/* MODE values */
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#define QUADSPI_CCR_MODE_NONE 0
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#define QUADSPI_CCR_MODE_1LINE 1
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#define QUADSPI_CCR_MODE_2LINE 2
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#define QUADSPI_CCR_MODE_4LINE 3
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/* FMODE values */
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#define QUADSPI_CCR_FMODE_IWRITE 0
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#define QUADSPI_CCR_FMODE_IREAD 1
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#define QUADSPI_CCR_FMODE_APOLL 2
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#define QUADSPI_CCR_FMODE_MEMMAP 3
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/* QUADSPI address register */
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#define QUADSPI_AR MMIO32(QUADSPI_BASE + 0x18U)
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/* QUADSPI alternate bytes register */
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#define QUADSPI_ABR MMIO32(QUADSPI_BASE + 0x1CU)
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/* QUADSPI data register */
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#define QUADSPI_DR MMIO32(QUADSPI_BASE + 0x20U)
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/* BYTE addressable version for fetching bytes from the interface */
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#define QUADSPI_BYTE_DR MMIO8(QUADSPI_BASE + 0x20U)
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/* QUADSPI polling status */
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#define QUADSPI_PSMKR MMIO32(QUADSPI_BASE + 0x24U)
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/* QUADSPI polling status match */
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#define QUADSPI_PSMAR MMIO32(QUADSPI_BASE + 0x28U)
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/* QUADSPI polling interval register */
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#define QUADSPI_PIR MMIO32(QUADSPI_BASE + 0x2CU)
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/* QUADSPI low power timeout */
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#define QUADSPI_LPTR MMIO32(QUADSPI_BASE + 0x30U)
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#define QUADSPI_CR_DMAEN (1 << 2)
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#endif /* LIBOPENCM3_QUADSPI_H */
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@ -0,0 +1,27 @@
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/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_QUADSPI_H
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#define LIBOPENCM3_QUADSPI_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/stm32/common/quadspi_common_v1.h>
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/** Enable free running clock mode, for testing */
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#define QUADSPI_CCR_FRCM (1 << 29)
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#endif /* LIBOPENCM3_QUADSPI_H */
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