stm32f4/7: DCMI: extract common registers
And enable for the f7 Originally filed as: https://github.com/libopencm3/libopencm3/pull/1208 Rviewed-by: Karl Palsson <karlp@tweak.net.au>
This commit is contained in:
Nikolai Smolyaninov
Karl Palsson
parent
81d1b2cfb6
commit
071d4680ec
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/** @addtogroup dcmi_defines
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*
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* @version 1.0.0
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*
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* @author @htmlonly © @endhtmlonly 2020
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* Smolyaninov Nikolay <smolin35@gmail.com>
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* @author @htmlonly © @endhtmlonly 2017
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* Marek Koza <qyx@krtko.org>
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*
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* @date 15 May 2020
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*
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* This library supports the Digital camera interface (DCMI) in the STM32F4xx
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* and STM32F7xx series of ARM Cortex Microcontrollers by ST Microelectronics.
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2020, Smolyaninov Nikolay <smolin35@gmail.com>
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* Copyright (C) 2017, Marek Koza <qyx@krtko.org>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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/** @cond */
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#ifndef LIBOPENCM3_STM32_COMMON_DCMI_COMMON_F47_H_
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/** @endcond */
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#define LIBOPENCM3_STM32_COMMON_DCMI_COMMON_F47_H_
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/stm32/memorymap.h>
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/**
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* DCMI control register 1
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*/
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#define DCMI_CR MMIO32(DCMI_BASE + 0x0U)
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/**
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* @defgroup dcmi_cr_values DCMI_CR Values
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* @ingroup dcmi_defines
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* @{
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*/
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#define DCMI_CR_EN (1 << 14)
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#define DCMI_CR_EDM1 (1 << 11)
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#define DCMI_CR_EDM0 (1 << 10)
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#define DCMI_CR_FCRC1 (1 << 9)
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#define DCMI_CR_FCRC0 (1 << 8)
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#define DCMI_CR_VSPOL (1 << 7)
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#define DCMI_CR_HSPOL (1 << 6)
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#define DCMI_CR_PCKPOL (1 << 5)
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#define DCMI_CR_ESS (1 << 4)
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#define DCMI_CR_JPEG (1 << 3)
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#define DCMI_CR_CROP (1 << 2)
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#define DCMI_CR_CM (1 << 1)
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#define DCMI_CR_CAPTURE (1 << 0)
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/**@}*/
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/**
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* DCMI status register
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*/
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#define DCMI_SR MMIO32(DCMI_BASE + 0x04U)
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/**
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* @defgroup dcmi_sr_values DCMI_SR Values
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* @ingroup dcmi_defines
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* @{
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*/
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#define DCMI_SR_FNE (1 << 2)
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#define DCMI_SR_VSYNCK (1 << 1)
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#define DCMI_SR_HSYNCK (1 << 0)
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/**@}*/
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/**
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* DCMI raw interrupt status register
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*
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* DCMI_RIS gives the raw interrupt status and is accessible in read only. When read, this
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* register returns the status of the corresponding interrupt before masking with the DCMI_IER
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* register value.
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*/
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#define DCMI_RIS MMIO32(DCMI_BASE + 0x08U)
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/**
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* @defgroup dcmi_ris_values DCMI_RIS Values
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* @ingroup dcmi_defines
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* @{
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*/
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#define DCMI_RIS_LINE (1 << 4)
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#define DCMI_RIS_VSYNC (1 << 3)
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#define DCMI_RIS_ERR (1 << 2)
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#define DCMI_RIS_OVR (1 << 1)
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#define DCMI_RIS_FRAME (1 << 0)
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/**@}*/
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/**
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* DCMI interrupt enable register
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*
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* The DCMI_IER register is used to enable interrupts. When one of the DCMI_IER bits is set,
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* the corresponding interrupt is enabled. This register is accessible in both read and write.
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*/
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#define DCMI_IER MMIO32(DCMI_BASE + 0x0CU)
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/**
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* @defgroup dcmi_ier_values DCMI_IER Values
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* @ingroup dcmi_defines
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* @{
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*/
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#define DCMI_IER_LINE (1 << 4)
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#define DCMI_IER_VSYNC (1 << 3)
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#define DCMI_IER_ERR (1 << 2)
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#define DCMI_IER_OVR (1 << 1)
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#define DCMI_IER_FRAME (1 << 0)
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/**@}*/
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/**
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* DCMI masked interrupt status register
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*
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* This DCMI_MIS register is a read-only register. When read, it returns the current masked
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* status value (depending on the value in DCMI_IER) of the corresponding interrupt. A bit in
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* this register is set if the corresponding enable bit in DCMI_IER is set and the corresponding
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* bit in DCMI_RIS is set.
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*/
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#define DCMI_MIS MMIO32(DCMI_BASE + 0x10U)
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/**
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* @defgroup dcmi_mis_values DCMI_MIS Values
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* @ingroup dcmi_defines
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* @{
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*/
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#define DCMI_MIS_LINE (1 << 4)
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#define DCMI_MIS_VSYNC (1 << 3)
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#define DCMI_MIS_ERR (1 << 2)
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#define DCMI_MIS_OVR (1 << 1)
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#define DCMI_MIS_FRAME (1 << 0)
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/**@}*/
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/**
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* DCMI interrupt clear register
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*
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* The DCMI_ICR register is write-only. Writing a ‘1’ into a bit of this register clears the
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* corresponding bit in the DCMI_RIS and DCMI_MIS registers. Writing a ‘0’ has no effect.
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*/
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#define DCMI_ICR MMIO32(DCMI_BASE + 0x14U)
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/**
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* @defgroup dcmi_icr_values DCMI_ICR Values
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* @ingroup dcmi_defines
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* @{
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*/
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#define DCMI_ICR_LINE (1 << 4)
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#define DCMI_ICR_VSYNC (1 << 3)
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#define DCMI_ICR_ERR (1 << 2)
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#define DCMI_ICR_OVR (1 << 1)
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#define DCMI_ICR_FRAME (1 << 0)
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/**@}*/
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/**
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* DCMI embedded synchronization code register
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*/
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#define DCMI_ESCR MMIO32(DCMI_BASE + 0x18U)
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/**
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* @defgroup dcmi_escr_values DCMI_ESCR Values
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* @ingroup dcmi_defines
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* @{
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*/
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#define DCMI_ESCR_FEC_SHIFT 24
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#define DCMI_ESCR_FEC_MASK 0xff
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#define DCMI_ESCR_LEC_SHIFT 16
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#define DCMI_ESCR_LEC_MASK 0xff
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#define DCMI_ESCR_LSC_SHIFT 8
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#define DCMI_ESCR_LSC_MASK 0xff
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#define DCMI_ESCR_FSC_SHIFT 0
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#define DCMI_ESCR_FSC_MASK 0xff
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/**@}*/
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/**
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* DCMI embedded synchronization unmask register
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*/
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#define DCMI_ESUR MMIO32(DCMI_BASE + 0x1CU)
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/**
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* @defgroup dcmi_esur_values DCMI_ESUR Values
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* @ingroup dcmi_defines
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* @{
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*/
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#define DCMI_ESUR_FEU_SHIFT 24
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#define DCMI_ESUR_FEU_MASK 0xff
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#define DCMI_ESUR_LEU_SHIFT 16
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#define DCMI_ESUR_LEU_MASK 0xff
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#define DCMI_ESUR_LSU_SHIFT 8
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#define DCMI_ESUR_LSU_MASK 0xff
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#define DCMI_ESUR_FSU_SHIFT 0
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#define DCMI_ESUR_FSU_MASK 0xff
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/**@}*/
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/**
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* DCMI crop window start
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*/
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#define DCMI_CWSTRT MMIO32(DCMI_BASE + 0x20U)
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/**
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* @defgroup dcmi_cwstrt_values DCMI_CWSTRT Values
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* @ingroup dcmi_defines
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* @{
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*/
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#define DCMI_CWSTRT_VST_SHIFT 16
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#define DCMI_CWSTRT_VST_MASK 0x1fff
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#define DCMI_CWSTRT_HOFFCNT_SHIFT 0
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#define DCMI_CWSTRT_HOFFCNT_MASK 0x3fff
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/**@}*/
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/**
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* DCMI crop window size
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*/
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#define DCMI_CWSIZE MMIO32(DCMI_BASE + 0x24U)
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/**
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* @defgroup dcmi_cwsize_values DCMI_CWSIZE Values
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* @ingroup dcmi_defines
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* @{
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*/
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#define DCMI_CWSIZE_VLINE_SHIFT 16
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#define DCMI_CWSIZE_VLINE_MASK 0x3fff
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#define DCMI_CWSIZE_CAPCNT_SHIFT 0
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#define DCMI_CWSIZE_CAPCNT_MASK 0x3fff
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/**@}*/
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/**
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* DCMI data register
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*
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* The digital camera Interface packages all the received data in 32-bit format before
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* requesting a DMA transfer. A 4-word deep FIFO is available to leave enough time for DMA
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* transfers and avoid DMA overrun conditions.
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*/
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#define DCMI_DR MMIO32(DCMI_BASE + 0x28U)
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/** @cond */
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#endif /* LIBOPENCM3_STM32_COMMON_DCMI_COMMON_F47_H_ */
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/** @endcond */
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/**@}*/
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@ -22,6 +22,8 @@
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#if defined(STM32F4)
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# include <libopencm3/stm32/f4/dcmi.h>
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#elif defined(STM32F7)
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# include <libopencm3/stm32/f7/dcmi.h>
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#else
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# error "stm32 family not defined."
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#endif
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@ -6,15 +6,15 @@
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*
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* @version 1.0.0
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*
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* @date 2017-10-16
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* @date 2020-05-15
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* STM32F4 DCMI Defines
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*
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* Copyright (C) 2017, Marek Koza <qyx@krtko.org>
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* STM32F7 DCMI Defines
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* Copyright (C) 2020, Smolyaninov Nikolay <smolin35@gmail.org>
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*
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* This file is part of the libopencm3 project.
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*
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@ -33,197 +33,9 @@
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*
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*/
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/stm32/memorymap.h>
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#ifndef LIBOPENCM3_DCMI_H
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#define LIBOPENCM3_DCMI_H
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#pragma once
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#include <libopencm3/stm32/common/dcmi_common_f47.h>
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/**@{*/
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/**
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* DCMI control register 1
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*/
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#define DCMI_CR MMIO32(DCMI_BASE + 0x0U)
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/**
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* @defgroup dcmi_cr_values DCMI_CR Values
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* @ingroup dcmi_defines
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* @{
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*/
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#define DCMI_CR_EN (1 << 14)
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#define DCMI_CR_EDM1 (1 << 11)
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#define DCMI_CR_EDM0 (1 << 10)
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#define DCMI_CR_FCRC1 (1 << 9)
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#define DCMI_CR_FCRC0 (1 << 8)
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#define DCMI_CR_VSPOL (1 << 7)
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#define DCMI_CR_HSPOL (1 << 6)
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#define DCMI_CR_PCKPOL (1 << 5)
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#define DCMI_CR_ESS (1 << 4)
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#define DCMI_CR_JPEG (1 << 3)
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#define DCMI_CR_CROP (1 << 2)
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#define DCMI_CR_CM (1 << 1)
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#define DCMI_CR_CAPTURE (1 << 0)
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/**@}*/
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/**
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* DCMI status register
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*/
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#define DCMI_SR MMIO32(DCMI_BASE + 0x04U)
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/**
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* DCMI raw interrupt status register
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*
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* DCMI_RIS gives the raw interrupt status and is accessible in read only. When read, this
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* register returns the status of the corresponding interrupt before masking with the DCMI_IER
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* register value.
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*/
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#define DCMI_RIS MMIO32(DCMI_BASE + 0x08U)
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/**
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* @defgroup dcmi_ris_values DCMI_RIS Values
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* @ingroup dcmi_defines
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* @{
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*/
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#define DCMI_RIS_LINE (1 << 4)
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#define DCMI_RIS_VSYNC (1 << 3)
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#define DCMI_RIS_ERR (1 << 2)
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#define DCMI_RIS_OVR (1 << 1)
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#define DCMI_RIS_FRAME (1 << 0)
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/**@}*/
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/**
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* DCMI interrupt enable register
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*
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* The DCMI_IER register is used to enable interrupts. When one of the DCMI_IER bits is set,
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* the corresponding interrupt is enabled. This register is accessible in both read and write.
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*/
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#define DCMI_IER MMIO32(DCMI_BASE + 0x0CU)
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/**
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* @defgroup dcmi_ier_values DCMI_IER Values
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* @ingroup dcmi_defines
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* @{
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*/
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#define DCMI_IER_LINE (1 << 4)
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#define DCMI_IER_VSYNC (1 << 3)
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#define DCMI_IER_ERR (1 << 2)
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#define DCMI_IER_OVR (1 << 1)
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#define DCMI_IER_FRAME (1 << 0)
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/**@}*/
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/**
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* DCMI masked interrupt status register
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*
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* This DCMI_MIS register is a read-only register. When read, it returns the current masked
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* status value (depending on the value in DCMI_IER) of the corresponding interrupt. A bit in
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* this register is set if the corresponding enable bit in DCMI_IER is set and the corresponding
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* bit in DCMI_RIS is set.
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*/
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#define DCMI_MIS MMIO32(DCMI_BASE + 0x10U)
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/**
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* @defgroup dcmi_mis_values DCMI_MIS Values
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* @ingroup dcmi_defines
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* @{
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*/
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#define DCMI_MIS_LINE (1 << 4)
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#define DCMI_MIS_VSYNC (1 << 3)
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#define DCMI_MIS_ERR (1 << 2)
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#define DCMI_MIS_OVR (1 << 1)
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#define DCMI_MIS_FRAME (1 << 0)
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/**@}*/
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/**
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* DCMI interrupt clear register
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*
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* The DCMI_ICR register is write-only. Writing a ‘1’ into a bit of this register clears the
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* corresponding bit in the DCMI_RIS and DCMI_MIS registers. Writing a ‘0’ has no effect.
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*/
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#define DCMI_ICR MMIO32(DCMI_BASE + 0x14U)
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/**
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* @defgroup dcmi_icr_values DCMI_ICR Values
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* @ingroup dcmi_defines
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* @{
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*/
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#define DCMI_ICR_LINE (1 << 4)
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#define DCMI_ICR_VSYNC (1 << 3)
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#define DCMI_ICR_ERR (1 << 2)
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#define DCMI_ICR_OVR (1 << 1)
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#define DCMI_ICR_FRAME (1 << 0)
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/**@}*/
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/**
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* DCMI embedded synchronization code register
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*/
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#define DCMI_ESCR MMIO32(DCMI_BASE + 0x18U)
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/**
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* @defgroup dcmi_escr_values DCMI_ESCR Values
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* @ingroup dcmi_defines
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* @{
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*/
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#define DCMI_ESCR_FEC_SHIFT 24
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#define DCMI_ESCR_FEC_MASK 0xff
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#define DCMI_ESCR_LEC_SHIFT 16
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#define DCMI_ESCR_LEC_MASK 0xff
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#define DCMI_ESCR_LSC_SHIFT 8
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#define DCMI_ESCR_LSC_MASK 0xff
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#define DCMI_ESCR_FSC_SHIFT 0
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#define DCMI_ESCR_FSC_MASK 0xff
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/**@}*/
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/**
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* DCMI embedded synchronization unmask register
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*/
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#define DCMI_ESUR MMIO32(DCMI_BASE + 0x1CU)
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/**
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* @defgroup dcmi_esur_values DCMI_ESUR Values
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* @ingroup dcmi_defines
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* @{
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*/
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#define DCMI_ESUR_FEU_SHIFT 24
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#define DCMI_ESUR_FEU_MASK 0xff
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#define DCMI_ESUR_LEU_SHIFT 16
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#define DCMI_ESUR_LEU_MASK 0xff
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#define DCMI_ESUR_LSU_SHIFT 8
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#define DCMI_ESUR_LSU_MASK 0xff
|
||||
#define DCMI_ESUR_FSU_SHIFT 0
|
||||
#define DCMI_ESUR_FSU_MASK 0xff
|
||||
/**@}*/
|
||||
|
||||
/**
|
||||
* DCMI crop window start
|
||||
*/
|
||||
#define DCMI_CWSTRT MMIO32(DCMI_BASE + 0x20U)
|
||||
/**
|
||||
* @defgroup dcmi_cwstrt_values DCMI_CWSTRT Values
|
||||
* @ingroup dcmi_defines
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_CWSTRT_VST_SHIFT 16
|
||||
#define DCMI_CWSTRT_VST_MASK 0x1fff
|
||||
#define DCMI_CWSTRT_HOFFCNT_SHIFT 0
|
||||
#define DCMI_CWSTRT_HOFFCNT_MASK 0x3fff
|
||||
/**@}*/
|
||||
|
||||
/**
|
||||
* DCMI crop window size
|
||||
*/
|
||||
#define DCMI_CWSIZE MMIO32(DCMI_BASE + 0x24U)
|
||||
/**
|
||||
* @defgroup dcmi_cwsize_values DCMI_CWSIZE Values
|
||||
* @ingroup dcmi_defines
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_CWSIZE_VLINE_SHIFT 16
|
||||
#define DCMI_CWSIZE_VLINE_MASK 0x3fff
|
||||
#define DCMI_CWSIZE_CAPCNT_SHIFT 0
|
||||
#define DCMI_CWSIZE_CAPCNT_MASK 0x3fff
|
||||
/**@}*/
|
||||
|
||||
/**
|
||||
* DCMI data register
|
||||
*
|
||||
* The digital camera Interface packages all the received data in 32-bit format before
|
||||
* requesting a DMA transfer. A 4-word deep FIFO is available to leave enough time for DMA
|
||||
* transfers and avoid DMA overrun conditions.
|
||||
*/
|
||||
#define DCMI_DR MMIO32(DCMI_BASE + 0x28U)
|
||||
|
||||
/**@}*/
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,57 @@
|
|||
/** @defgroup dcmi_defines DCMI Defines
|
||||
*
|
||||
* @ingroup STM32F7xx_defines
|
||||
*
|
||||
* @brief Defined Constants and Macros for the STM32F7xx DCMI Peripheral
|
||||
*
|
||||
* @version 1.0.0
|
||||
*
|
||||
* @date 2020-05-15
|
||||
*
|
||||
* LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* STM32F7 DCMI Defines
|
||||
* Copyright (C) 2020, Smolyaninov Nikolay <smolin35@gmail.org>
|
||||
*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef LIBOPENCM3_DCMI_H
|
||||
#define LIBOPENCM3_DCMI_H
|
||||
|
||||
#include <libopencm3/stm32/common/dcmi_common_f47.h>
|
||||
|
||||
/**@{*/
|
||||
|
||||
/**
|
||||
* @defgroup dcmi_cr_values DCMI_CR Values
|
||||
* @ingroup dcmi_defines
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_CR_OELS (1 << 20)
|
||||
#define DCMI_CR_LSM (1 << 19)
|
||||
#define DCMI_CR_OEBS (1 << 18)
|
||||
#define DCMI_CR_BSM1 (1 << 17)
|
||||
#define DCMI_CR_BSM0 (1 << 16)
|
||||
|
||||
|
||||
/**@}*/
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue