stm32/f1/rcc: add 25mhz in to 72mhz out clock tree setup function.
also: added support for previously undefined PLLs
This commit is contained in:
Jeff Ciesielski
parent
153e81bc96
commit
069a758f6c
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@ -86,7 +86,7 @@ LGPL License Terms @ref lgpl_license
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#define RCC_CFGR_MCO_SYSCLK 0x4
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#define RCC_CFGR_MCO_HSICLK 0x5
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#define RCC_CFGR_MCO_HSECLK 0x6
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#define RCC_CFGR_RMCO_PLLCLK_DIV2 0x7
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#define RCC_CFGR_MCO_PLLCLK_DIV2 0x7
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#define RCC_CFGR_MCO_PLL2CLK 0x8 /* (**) */
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#define RCC_CFGR_MCO_PLL3CLK_DIV2 0x9 /* (**) */
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#define RCC_CFGR_MCO_XT1 0xa /* (**) */
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@ -448,6 +448,24 @@ LGPL License Terms @ref lgpl_license
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#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL16 0xe
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#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL20 0xf
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/* PREDIV: PREDIV division factor */
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#define RCC_CFGR2_PREDIV_NODIV 0x0
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#define RCC_CFGR2_PREDIV_DIV2 0x1
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#define RCC_CFGR2_PREDIV_DIV3 0x2
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#define RCC_CFGR2_PREDIV_DIV4 0x3
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#define RCC_CFGR2_PREDIV_DIV5 0x4
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#define RCC_CFGR2_PREDIV_DIV6 0x5
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#define RCC_CFGR2_PREDIV_DIV7 0x6
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#define RCC_CFGR2_PREDIV_DIV8 0x7
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#define RCC_CFGR2_PREDIV_DIV9 0x8
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#define RCC_CFGR2_PREDIV_DIV10 0x9
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#define RCC_CFGR2_PREDIV_DIV11 0xa
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#define RCC_CFGR2_PREDIV_DIV12 0xb
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#define RCC_CFGR2_PREDIV_DIV13 0xc
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#define RCC_CFGR2_PREDIV_DIV14 0xd
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#define RCC_CFGR2_PREDIV_DIV15 0xe
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#define RCC_CFGR2_PREDIV_DIV16 0xf
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/* PREDIV2: PREDIV2 division factor */
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#define RCC_CFGR2_PREDIV2_NODIV 0x0
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#define RCC_CFGR2_PREDIV2_DIV2 0x1
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@ -473,7 +491,7 @@ extern u32 rcc_ppre2_frequency;
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/* --- Function prototypes ------------------------------------------------- */
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typedef enum {
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PLL, HSE, HSI, LSE, LSI
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PLL, PLL2, PLL3, HSE, HSI, LSE, LSI
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} osc_t;
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BEGIN_DECLS
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@ -497,6 +515,7 @@ void rcc_peripheral_reset(volatile u32 *reg, u32 reset);
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void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset);
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void rcc_set_sysclk_source(u32 clk);
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void rcc_set_pll_multiplication_factor(u32 mul);
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void rcc_set_pll2_multiplication_factor(u32 mul);
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void rcc_set_pll_source(u32 pllsrc);
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void rcc_set_pllxtpre(u32 pllxtpre);
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void rcc_set_adcpre(u32 adcpre);
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@ -512,6 +531,7 @@ void rcc_clock_setup_in_hse_8mhz_out_24mhz(void);
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void rcc_clock_setup_in_hse_8mhz_out_72mhz(void);
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void rcc_clock_setup_in_hse_12mhz_out_72mhz(void);
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void rcc_clock_setup_in_hse_16mhz_out_72mhz(void);
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void rcc_clock_setup_in_hse_25mhz_out_72mhz(void);
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void rcc_backupdomain_reset(void);
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END_DECLS
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@ -71,6 +71,12 @@ void rcc_osc_ready_int_clear(osc_t osc)
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case PLL:
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RCC_CIR |= RCC_CIR_PLLRDYC;
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break;
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case PLL2:
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RCC_CIR |= RCC_CIR_PLL2RDYC;
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break;
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case PLL3:
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RCC_CIR |= RCC_CIR_PLL3RDYC;
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break;
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case HSE:
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RCC_CIR |= RCC_CIR_HSERDYC;
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break;
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@ -98,6 +104,12 @@ void rcc_osc_ready_int_enable(osc_t osc)
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case PLL:
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RCC_CIR |= RCC_CIR_PLLRDYIE;
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break;
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case PLL2:
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RCC_CIR |= RCC_CIR_PLL2RDYIE;
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break;
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case PLL3:
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RCC_CIR |= RCC_CIR_PLL3RDYIE;
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break;
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case HSE:
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RCC_CIR |= RCC_CIR_HSERDYIE;
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break;
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@ -125,6 +137,12 @@ void rcc_osc_ready_int_disable(osc_t osc)
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case PLL:
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RCC_CIR &= ~RCC_CIR_PLLRDYIE;
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break;
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case PLL2:
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RCC_CIR &= ~RCC_CIR_PLL2RDYIE;
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break;
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case PLL3:
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RCC_CIR &= ~RCC_CIR_PLL3RDYIE;
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break;
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case HSE:
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RCC_CIR &= ~RCC_CIR_HSERDYIE;
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break;
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@ -153,6 +171,12 @@ int rcc_osc_ready_int_flag(osc_t osc)
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case PLL:
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return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0);
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break;
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case PLL2:
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return ((RCC_CIR & RCC_CIR_PLL2RDYF) != 0);
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break;
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case PLL3:
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return ((RCC_CIR & RCC_CIR_PLL3RDYF) != 0);
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break;
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case HSE:
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return ((RCC_CIR & RCC_CIR_HSERDYF) != 0);
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break;
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@ -203,6 +227,12 @@ void rcc_wait_for_osc_ready(osc_t osc)
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case PLL:
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while ((RCC_CR & RCC_CR_PLLRDY) == 0);
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break;
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case PLL2:
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while ((RCC_CR & RCC_CR_PLL2RDY) == 0);
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break;
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case PLL3:
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while ((RCC_CR & RCC_CR_PLL3RDY) == 0);
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break;
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case HSE:
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while ((RCC_CR & RCC_CR_HSERDY) == 0);
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break;
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@ -238,6 +268,12 @@ void rcc_osc_on(osc_t osc)
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case PLL:
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RCC_CR |= RCC_CR_PLLON;
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break;
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case PLL2:
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RCC_CR |= RCC_CR_PLL2ON;
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break;
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case PLL3:
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RCC_CR |= RCC_CR_PLL3ON;
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break;
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case HSE:
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RCC_CR |= RCC_CR_HSEON;
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break;
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@ -273,6 +309,12 @@ void rcc_osc_off(osc_t osc)
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case PLL:
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RCC_CR &= ~RCC_CR_PLLON;
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break;
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case PLL2:
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RCC_CR &= ~RCC_CR_PLL2ON;
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break;
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case PLL3:
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RCC_CR &= ~RCC_CR_PLL3ON;
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break;
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case HSE:
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RCC_CR &= ~RCC_CR_HSEON;
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break;
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@ -331,6 +373,8 @@ void rcc_osc_bypass_enable(osc_t osc)
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RCC_BDCR |= RCC_BDCR_LSEBYP;
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break;
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case PLL:
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case PLL2:
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case PLL3:
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case HSI:
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case LSI:
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/* Do nothing, only HSE/LSE allowed here. */
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@ -361,6 +405,8 @@ void rcc_osc_bypass_disable(osc_t osc)
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RCC_BDCR &= ~RCC_BDCR_LSEBYP;
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break;
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case PLL:
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case PLL2:
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case PLL3:
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case HSI:
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case LSI:
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/* Do nothing, only HSE/LSE allowed here. */
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@ -484,6 +530,40 @@ void rcc_set_pll_multiplication_factor(u32 mul)
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RCC_CFGR = (reg32 | (mul << 18));
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief RCC Set the PLL2 Multiplication Factor.
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@note This only has effect when the PLL is disabled.
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@param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pmf
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*/
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void rcc_set_pll2_multiplication_factor(u32 mul)
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{
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u32 reg32;
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reg32 = RCC_CFGR2;
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reg32 &= ~((1 << 11) | (1 << 10) | (1 << 9) | (1 << 8));
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RCC_CFGR2 = (reg32 | (mul << 8));
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief RCC Set the PLL3 Multiplication Factor.
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@note This only has effect when the PLL is disabled.
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@param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pmf
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*/
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void rcc_set_pll3_multiplication_factor(u32 mul)
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{
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u32 reg32;
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reg32 = RCC_CFGR2;
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reg32 &= ~((1 << 15) | (1 << 14) | (1 << 13) | (1 << 12));
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RCC_CFGR2 = (reg32 | (mul << 12));
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief RCC Set the PLL Clock Source.
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@ -602,6 +682,36 @@ void rcc_set_usbpre(u32 usbpre)
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RCC_CFGR = (reg32 | (usbpre << 22));
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}
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void rcc_set_prediv1(u32 prediv)
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{
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u32 reg32;
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reg32 = RCC_CFGR2;
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reg32 &= ~(1 << 3) | (1 << 2) | (1 << 1) | (1 << 0);
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RCC_CFGR2 |= (reg32 | prediv);
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}
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void rcc_set_prediv2(u32 prediv)
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{
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u32 reg32;
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reg32 = RCC_CFGR2;
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reg32 &= ~(1 << 7) | (1 << 6) | (1 << 5) | (1 << 4);
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RCC_CFGR2 |= (reg32 | (prediv << 4));
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}
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void rcc_set_prediv1_source(u32 rccsrc)
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{
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RCC_CFGR2 &= ~(1 << 16);
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RCC_CFGR2 |= (rccsrc << 16);
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}
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void rcc_set_mco(u32 mcosrc)
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{
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u32 reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 27) | (1 << 26) | (1 << 25) | (1 << 24));
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RCC_CFGR |= (reg32 | (mcosrc << 24));
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief RCC Get the System Clock Source.
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@ -1030,6 +1140,63 @@ void rcc_clock_setup_in_hse_16mhz_out_72mhz(void)
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rcc_ppre2_frequency = 72000000;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief RCC Set System Clock PLL at 72MHz from HSE at 25MHz
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*/
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void rcc_clock_setup_in_hse_25mhz_out_72mhz(void)
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{
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/* Enable external high-speed oscillator 25MHz. */
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rcc_osc_on(HSE);
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rcc_wait_for_osc_ready(HSE);
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rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK);
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/*
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* Sysclk runs with 72MHz -> 2 waitstates.
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* 0WS from 0-24MHz
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* 1WS from 24-48MHz
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* 2WS from 48-72MHz
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*/
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flash_set_ws(FLASH_LATENCY_2WS);
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/*
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* Set prescalers for AHB, ADC, ABP1, ABP2.
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* Do this before touching the PLL (TODO: why?).
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*/
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rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */
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rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */
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rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */
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rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */
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/* Set pll2 prediv and multiplier */
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rcc_set_prediv2(RCC_CFGR2_PREDIV2_DIV5);
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rcc_set_pll2_multiplication_factor(RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL8);
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/* Enable PLL2 oscillator and wait for it to stabilize */
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rcc_osc_on(PLL2);
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rcc_wait_for_osc_ready(PLL2);
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/* Set pll1 prediv/multiplier, prediv1 src, and usb predivider */
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rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK);
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rcc_set_prediv1_source(RCC_CFGR2_PREDIV1SRC_PLL2_CLK);
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rcc_set_prediv1(RCC_CFGR2_PREDIV_DIV5);
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rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL9);
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rcc_set_pll_source(RCC_CFGR_PLLSRC_PREDIV1_CLK);
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rcc_set_usbpre(RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV3);
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/* enable PLL1 and wait for it to stabilize */
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rcc_osc_on(PLL);
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rcc_wait_for_osc_ready(PLL);
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/* Select PLL as SYSCLK source. */
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rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
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/* Set the peripheral clock frequencies used */
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rcc_ppre1_frequency = 36000000;
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rcc_ppre2_frequency = 72000000;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief RCC Reset the backup domain
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