2013-03-10 12:58:21 +00:00
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/** @defgroup gpio_defines General Purpose I/O Defines
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2013-05-16 06:02:43 +00:00
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*
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* @brief <b>Defined Constants and Types for the LM4F General Purpose I/O</b>
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*
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* @ingroup LM4Fxx_defines
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*
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* @version 1.0.0
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*
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2013-05-16 07:18:54 +00:00
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* @author @htmlonly © @endhtmlonly 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
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2013-05-16 06:02:43 +00:00
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*
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* @date 10 March 2013
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*
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* LGPL License Terms @ref lgpl_license
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*/
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2013-03-10 12:58:21 +00:00
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2012-11-22 02:39:36 +00:00
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
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2013-05-16 07:18:54 +00:00
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* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
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2012-11-22 02:39:36 +00:00
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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2012-11-22 22:04:32 +00:00
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#ifndef LM4F_GPIO_H
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#define LM4F_GPIO_H
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2012-11-22 02:39:36 +00:00
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2013-03-10 12:58:21 +00:00
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/**@{*/
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2012-11-22 02:39:36 +00:00
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#include <libopencm3/cm3/common.h>
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2012-11-22 22:04:32 +00:00
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#include <libopencm3/lm4f/memorymap.h>
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2012-11-22 02:39:36 +00:00
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2013-05-16 07:18:54 +00:00
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/* =============================================================================
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* Convenience macros
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* ---------------------------------------------------------------------------*/
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/** @defgroup gpio_reg_base GPIO register base addresses
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* @{*/
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2013-05-16 05:51:47 +00:00
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#define GPIOA GPIOA_BASE
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#define GPIOB GPIOB_BASE
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#define GPIOC GPIOC_BASE
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#define GPIOD GPIOD_BASE
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#define GPIOE GPIOE_BASE
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#define GPIOF GPIOF_BASE
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#define GPIOG GPIOG_BASE
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#define GPIOH GPIOH_BASE
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#define GPIOJ GPIOJ_BASE
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#define GPIOK GPIOK_BASE
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#define GPIOL GPIOL_BASE
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#define GPIOM GPIOM_BASE
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#define GPION GPION_BASE
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#define GPIOP GPIOP_BASE
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#define GPIOQ GPIOQ_BASE
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/** @} */
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2012-11-22 02:39:36 +00:00
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2013-05-16 07:18:54 +00:00
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/* =============================================================================
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* GPIO number definitions (for convenience)
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*
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* These are usable across all GPIO registers,
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* except GPIO_LOCK and GPIO_PCTL
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* ---------------------------------------------------------------------------*/
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2012-11-22 02:39:36 +00:00
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#define GPIO0 (1 << 0)
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#define GPIO1 (1 << 1)
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#define GPIO2 (1 << 2)
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#define GPIO3 (1 << 3)
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#define GPIO4 (1 << 4)
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#define GPIO5 (1 << 5)
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#define GPIO6 (1 << 6)
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#define GPIO7 (1 << 7)
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#define GPIO_ALL 0xff
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2012-11-22 02:39:36 +00:00
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2013-05-16 07:18:54 +00:00
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/* =============================================================================
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* GPIO registers
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* ---------------------------------------------------------------------------*/
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2013-05-16 07:18:54 +00:00
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/* GPIO Data */
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2012-11-22 02:39:36 +00:00
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#define GPIO_DATA(port) ((volatile u32 *)(port + 0x000))
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/* GPIO Direction */
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2012-11-22 02:39:36 +00:00
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#define GPIO_DIR(port) MMIO32(port + 0x400)
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/* GPIO Interrupt Sense */
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2012-11-22 02:39:36 +00:00
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#define GPIO_IS(port) MMIO32(port + 0x404)
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/* GPIO Interrupt Both Edges */
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#define GPIO_IBE(port) MMIO32(port + 0x408)
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/* GPIO Interrupt Event */
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#define GPIO_IEV(port) MMIO32(port + 0x40c)
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/* GPIO Interrupt Mask */
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#define GPIO_IM(port) MMIO32(port + 0x410)
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/* GPIO Raw Interrupt Status */
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2012-11-22 02:39:36 +00:00
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#define GPIO_RIS(port) MMIO32(port + 0x414)
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/* GPIO Masked Interrupt Status */
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#define GPIO_MIS(port) MMIO32(port + 0x418)
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/* GPIO Interrupt Clear */
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#define GPIO_ICR(port) MMIO32(port + 0x41c)
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/* GPIO Alternate Function Select */
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#define GPIO_AFSEL(port) MMIO32(port + 0x420)
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/* GPIO 2-mA Drive Select */
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2012-11-22 02:39:36 +00:00
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#define GPIO_DR2R(port) MMIO32(port + 0x500)
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/* GPIO 4-mA Drive Select */
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#define GPIO_DR4R(port) MMIO32(port + 0x504)
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/* GPIO 8-mA Drive Select */
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#define GPIO_DR8R(port) MMIO32(port + 0x508)
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/* GPIO Open Drain Select */
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#define GPIO_ODR(port) MMIO32(port + 0x50c)
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/* GPIO Pull-Up Select */
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#define GPIO_PUR(port) MMIO32(port + 0x510)
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/* GPIO Pull-Down Select */
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#define GPIO_PDR(port) MMIO32(port + 0x514)
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/* GPIO Slew Rate Control Select */
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#define GPIO_SLR(port) MMIO32(port + 0x518)
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/* GPIO Digital Enable */
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#define GPIO_DEN(port) MMIO32(port + 0x51c)
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/* GPIO Lock */
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#define GPIO_LOCK(port) MMIO32(port + 0x520)
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/* GPIO Commit */
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#define GPIO_CR(port) MMIO32(port + 0x524)
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/* GPIO Analog Mode Select */
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#define GPIO_AMSEL(port) MMIO32(port + 0x528)
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/* GPIO Port Control */
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#define GPIO_PCTL(port) MMIO32(port + 0x52C)
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/* GPIO ADC Control */
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#define GPIO_ADCCTL(port) MMIO32(port + 0x530)
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/* GPIO DMA Control */
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#define GPIO_DMACTL(port) MMIO32(port + 0x534)
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/* GPIO Peripheral Identification */
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#define GPIO_PERIPH_ID4(port) MMIO32(port + 0xFD0)
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#define GPIO_PERIPH_ID5(port) MMIO32(port + 0xFD4)
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#define GPIO_PERIPH_ID6(port) MMIO32(port + 0xFD8)
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#define GPIO_PERIPH_ID7(port) MMIO32(port + 0xFDC)
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#define GPIO_PERIPH_ID0(port) MMIO32(port + 0xFE0)
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#define GPIO_PERIPH_ID1(port) MMIO32(port + 0xFE4)
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#define GPIO_PERIPH_ID2(port) MMIO32(port + 0xFE8)
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#define GPIO_PERIPH_ID3(port) MMIO32(port + 0xFEC)
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/* GPIO PrimeCell Identification */
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#define GPIO_PCELL_ID0(port) MMIO32(port + 0xFF0)
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#define GPIO_PCELL_ID1(port) MMIO32(port + 0xFF4)
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#define GPIO_PCELL_ID2(port) MMIO32(port + 0xFF8)
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#define GPIO_PCELL_ID3(port) MMIO32(port + 0xFFC)
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2012-11-22 02:39:36 +00:00
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BEGIN_DECLS
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void gpio_set(u32 gpioport, u8 gpios);
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void gpio_clear(u32 gpioport, u8 gpios);
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END_DECLS
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#endif
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2013-03-10 12:58:21 +00:00
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/**@}*/
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