2009-07-20 13:29:43 +00:00
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/*
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* This file is part of the libopenstm32 project.
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*
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* Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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2009-07-20 15:54:33 +00:00
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#include <libopenstm32.h>
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2009-07-20 13:29:43 +00:00
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void rcc_osc_ready_int_clear(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CR |= PLLRDYC;
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break;
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case HSE:
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RCC_CR |= HSERDYC;
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break;
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case HSI:
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RCC_CR |= HSIRDYC;
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break;
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case LSE:
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RCC_CIR |= LSERDYC;
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break;
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case LSI:
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RCC_CIR |= LSIRDYC;
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break;
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}
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}
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void rcc_osc_ready_int_enable(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CR |= PLLRDYIE;
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break;
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case HSE:
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RCC_CR |= HSERDYIE;
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break;
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case HSI:
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RCC_CR |= HSIRDYIE;
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break;
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case LSE:
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RCC_CIR |= LSERDYIE;
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break;
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case LSI:
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RCC_CIR |= LSIRDYIE;
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break;
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}
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}
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void rcc_osc_ready_int_disable(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CR &= ~PLLRDYIE;
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break;
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case HSE:
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RCC_CR &= ~HSERDYIE;
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break;
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case HSI:
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RCC_CR &= ~HSIRDYIE;
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break;
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case LSE:
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RCC_CIR &= ~LSERDYIE;
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break;
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case LSI:
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RCC_CIR &= ~LSIRDYIE;
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break;
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}
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}
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int rcc_osc_ready_int_flag(osc_t osc)
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{
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switch (osc) {
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case PLL:
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return ((RCC_CR & PLLRDYF) != 0);
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break;
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case HSE:
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return ((RCC_CR & HSERDYF) != 0);
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break;
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case HSI:
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return ((RCC_CR & HSIRDYF) != 0);
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break;
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case LSE:
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return ((RCC_CIR & LSERDYF) != 0);
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break;
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case LSI:
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return ((RCC_CIR & LSIRDYF) != 0);
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break;
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}
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2009-07-20 13:32:28 +00:00
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/* Shouldn't be reached. */
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return -1;
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2009-07-20 13:29:43 +00:00
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}
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void rcc_css_int_clear(void)
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{
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RCC_CIR |= CSSC;
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}
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int rcc_css_int_flag(void)
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{
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return ((RCC_CIR & CSSF) != 0);
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}
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2009-07-22 00:38:31 +00:00
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void rcc_wait_for_osc_ready(osc_t osc)
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2009-07-20 13:29:43 +00:00
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{
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switch (osc) {
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case PLL:
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2010-01-14 18:34:30 +00:00
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while ((RCC_CR & PLLRDY) == 0);
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2009-07-20 13:29:43 +00:00
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break;
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case HSE:
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2010-01-14 18:34:30 +00:00
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while ((RCC_CR & HSERDY) == 0);
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2009-07-20 13:29:43 +00:00
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break;
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case HSI:
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2010-01-14 18:34:30 +00:00
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while ((RCC_CR & HSIRDY) == 0);
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2009-07-20 13:29:43 +00:00
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break;
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case LSE:
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2010-01-14 18:34:30 +00:00
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while ((RCC_BDCR & LSERDY) == 0);
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2009-07-20 13:29:43 +00:00
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break;
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case LSI:
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2010-01-14 18:34:30 +00:00
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while ((RCC_CSR & LSIRDY) == 0);
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2009-07-20 13:29:43 +00:00
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break;
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}
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}
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void rcc_osc_on(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CR |= PLLON;
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break;
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case HSE:
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RCC_CR |= HSEON;
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break;
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case HSI:
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RCC_CR |= HSION;
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break;
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case LSE:
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RCC_BDCR |= LSEON;
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break;
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case LSI:
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RCC_CSR |= LSION;
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break;
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}
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}
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void rcc_osc_off(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CR &= ~PLLON;
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break;
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case HSE:
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RCC_CR &= ~HSEON;
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break;
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case HSI:
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RCC_CR &= ~HSION;
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break;
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case LSE:
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RCC_BDCR &= ~LSEON;
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break;
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case LSI:
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RCC_CSR &= ~LSION;
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break;
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}
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}
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void rcc_css_enable(void)
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{
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RCC_CR |= CSSON;
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}
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void rcc_css_disable(void)
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{
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RCC_CR &= ~CSSON;
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}
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void rcc_osc_bypass_enable(osc_t osc)
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{
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switch (osc) {
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case HSE:
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RCC_CR |= HSEBYP;
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break;
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case LSE:
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RCC_BDCR |= LSEBYP;
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break;
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2009-07-20 13:32:28 +00:00
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case PLL:
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case HSI:
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case LSI:
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/* Do nothing, only HSE/LSE allowed here. */
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break;
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2009-07-20 13:29:43 +00:00
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}
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}
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void rcc_osc_bypass_disable(osc_t osc)
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{
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switch (osc) {
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case HSE:
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RCC_CR &= ~HSEBYP;
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break;
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case LSE:
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RCC_BDCR &= ~LSEBYP;
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break;
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2009-07-20 13:32:28 +00:00
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case PLL:
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case HSI:
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case LSI:
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/* Do nothing, only HSE/LSE allowed here. */
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break;
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2009-07-20 13:29:43 +00:00
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}
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}
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2009-07-22 00:56:04 +00:00
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2009-08-31 12:47:07 +00:00
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void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en)
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2009-07-22 00:56:04 +00:00
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{
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2009-08-31 12:47:07 +00:00
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*reg |= en;
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2009-07-22 00:56:04 +00:00
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}
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2009-08-31 12:47:07 +00:00
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void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en)
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2009-07-22 00:56:04 +00:00
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{
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2009-08-31 12:47:07 +00:00
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*reg &= ~en;
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}
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void rcc_peripheral_reset(volatile u32 *reg, u32 reset)
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{
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*reg |= reset;
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}
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void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset)
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{
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*reg |= clear_reset;
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2009-07-22 00:56:04 +00:00
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}
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2009-07-22 01:25:14 +00:00
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void rcc_set_sysclk_source(u32 clk)
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{
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u32 reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 1) | (1 << 0));
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RCC_CFGR = (reg32 | clk);
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}
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void rcc_set_pll_multiplication_factor(u32 mul)
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{
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u32 reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 21) | (1 << 20) | (1 << 19) | (1 << 18));
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RCC_CFGR = (reg32 | (mul << 18));
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}
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void rcc_set_pll_source(u32 pllsrc)
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{
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u32 reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(1 << 16);
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RCC_CFGR = (reg32 | (pllsrc << 16));
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}
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void rcc_set_pllxtpre(u32 pllxtpre)
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{
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u32 reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(1 << 17);
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RCC_CFGR = (reg32 | (pllxtpre << 17));
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}
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