2012-05-29 21:12:04 +00:00
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LPC43XX_GPDMA_H
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#define LPC43XX_GPDMA_H
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/lpc43xx/memorymap.h>
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/* --- Convenience macros -------------------------------------------------- */
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/* GPDMA channel base addresses */
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#define GPDMA_CHANNEL0 (GPDMA_PORT_BASE + 0x100)
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#define GPDMA_CHANNEL1 (GPDMA_PORT_BASE + 0x120)
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#define GPDMA_CHANNEL2 (GPDMA_PORT_BASE + 0x140)
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#define GPDMA_CHANNEL3 (GPDMA_PORT_BASE + 0x160)
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#define GPDMA_CHANNEL4 (GPDMA_PORT_BASE + 0x180)
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#define GPDMA_CHANNEL5 (GPDMA_PORT_BASE + 0x1A0)
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#define GPDMA_CHANNEL6 (GPDMA_PORT_BASE + 0x1C0)
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#define GPDMA_CHANNEL7 (GPDMA_PORT_BASE + 0x1E0)
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/* --- GPDMA registers ----------------------------------------------------- */
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/* General registers */
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/* DMA Interrupt Status Register */
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#define GPDMA_NTSTAT MMIO32(GPDMA_BASE + 0x000)
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/* DMA Interrupt Terminal Count Request Status Register */
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#define GPDMA_INTTCSTAT MMIO32(GPDMA_BASE + 0x004)
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/* DMA Interrupt Terminal Count Request Clear Register */
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#define GPDMA_INTTCCLEAR MMIO32(GPDMA_BASE + 0x008)
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/* DMA Interrupt Error Status Register */
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#define GPDMA_INTERRSTAT MMIO32(GPDMA_BASE + 0x00C)
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/* DMA Interrupt Error Clear Register */
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#define GPDMA_INTERRCLR MMIO32(GPDMA_BASE + 0x010)
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/* DMA Raw Interrupt Terminal Count Status Register */
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#define GPDMA_RAWINTTCSTAT MMIO32(GPDMA_BASE + 0x014)
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/* DMA Raw Error Interrupt Status Register */
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#define GPDMA_RAWINTERRSTAT MMIO32(GPDMA_BASE + 0x018)
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/* DMA Enabled Channel Register */
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#define GPDMA_ENBLDCHNS MMIO32(GPDMA_BASE + 0x01C)
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/* DMA Software Burst Request Register */
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#define GPDMA_SOFTBREQ MMIO32(GPDMA_BASE + 0x020)
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/* DMA Software Single Request Register */
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#define GPDMA_SOFTSREQ MMIO32(GPDMA_BASE + 0x024)
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/* DMA Software Last Burst Request Register */
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#define GPDMA_SOFTLBREQ MMIO32(GPDMA_BASE + 0x028)
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/* DMA Software Last Single Request Register */
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#define GPDMA_SOFTLSREQ MMIO32(GPDMA_BASE + 0x02C)
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/* DMA Configuration Register */
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#define GPDMA_CONFIG MMIO32(GPDMA_BASE + 0x030)
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/* DMA Synchronization Register */
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#define GPDMA_SYNC MMIO32(GPDMA_BASE + 0x034)
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/* Channel registers */
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/* Source Address Register */
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#define GPDMA_SRCADDR(channel) MMIO32(channel + 0x000)
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2012-06-01 18:49:06 +00:00
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#define GPDMA_C0SRCADDR GPDMA_SRCADDR(GPDMA_CHANNEL0)
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#define GPDMA_C1SRCADDR GPDMA_SRCADDR(GPDMA_CHANNEL1)
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#define GPDMA_C2SRCADDR GPDMA_SRCADDR(GPDMA_CHANNEL2)
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#define GPDMA_C3SRCADDR GPDMA_SRCADDR(GPDMA_CHANNEL3)
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#define GPDMA_C4SRCADDR GPDMA_SRCADDR(GPDMA_CHANNEL4)
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#define GPDMA_C5SRCADDR GPDMA_SRCADDR(GPDMA_CHANNEL5)
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#define GPDMA_C6SRCADDR GPDMA_SRCADDR(GPDMA_CHANNEL6)
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#define GPDMA_C7SRCADDR GPDMA_SRCADDR(GPDMA_CHANNEL7)
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2012-05-29 21:12:04 +00:00
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/* Destination Address Register */
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#define GPDMA_DESTADDR(channel) MMIO32(channel + 0x004)
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2012-06-01 18:49:06 +00:00
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#define GPDMA_C0DESTADDR GPDMA_DESTADDR(GPDMA_CHANNEL0)
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#define GPDMA_C1DESTADDR GPDMA_DESTADDR(GPDMA_CHANNEL1)
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#define GPDMA_C2DESTADDR GPDMA_DESTADDR(GPDMA_CHANNEL2)
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#define GPDMA_C3DESTADDR GPDMA_DESTADDR(GPDMA_CHANNEL3)
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#define GPDMA_C4DESTADDR GPDMA_DESTADDR(GPDMA_CHANNEL4)
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#define GPDMA_C5DESTADDR GPDMA_DESTADDR(GPDMA_CHANNEL5)
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#define GPDMA_C6DESTADDR GPDMA_DESTADDR(GPDMA_CHANNEL6)
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#define GPDMA_C7DESTADDR GPDMA_DESTADDR(GPDMA_CHANNEL7)
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2012-05-29 21:12:04 +00:00
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/* Linked List Item Register */
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#define GPDMA_LLI(channel) MMIO32(channel + 0x008)
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2012-06-01 18:49:06 +00:00
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#define GPDMA_C0LLI GPDMA_LLI(GPDMA_CHANNEL0)
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#define GPDMA_C1LLI GPDMA_LLI(GPDMA_CHANNEL1)
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#define GPDMA_C2LLI GPDMA_LLI(GPDMA_CHANNEL2)
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#define GPDMA_C3LLI GPDMA_LLI(GPDMA_CHANNEL3)
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#define GPDMA_C4LLI GPDMA_LLI(GPDMA_CHANNEL4)
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#define GPDMA_C5LLI GPDMA_LLI(GPDMA_CHANNEL5)
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#define GPDMA_C6LLI GPDMA_LLI(GPDMA_CHANNEL6)
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#define GPDMA_C7LLI GPDMA_LLI(GPDMA_CHANNEL7)
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2012-05-29 21:12:04 +00:00
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/* Control Register */
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#define GPDMA_CONTROL(channel) MMIO32(channel + 0x00C)
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2012-06-01 18:49:06 +00:00
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#define GPDMA_C0CONTROL GPDMA_CONTROL(GPDMA_CHANNEL0)
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#define GPDMA_C1CONTROL GPDMA_CONTROL(GPDMA_CHANNEL1)
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#define GPDMA_C2CONTROL GPDMA_CONTROL(GPDMA_CHANNEL2)
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#define GPDMA_C3CONTROL GPDMA_CONTROL(GPDMA_CHANNEL3)
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#define GPDMA_C4CONTROL GPDMA_CONTROL(GPDMA_CHANNEL4)
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#define GPDMA_C5CONTROL GPDMA_CONTROL(GPDMA_CHANNEL5)
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#define GPDMA_C6CONTROL GPDMA_CONTROL(GPDMA_CHANNEL6)
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#define GPDMA_C7CONTROL GPDMA_CONTROL(GPDMA_CHANNEL7)
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2012-05-29 21:12:04 +00:00
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/* Configuration Register */
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#define GPDMA_CONFIG(channel) MMIO32(channel + 0x010)
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2012-06-01 18:49:06 +00:00
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#define GPDMA_C0CONFIG GPDMA_CONFIG(GPDMA_CHANNEL0)
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#define GPDMA_C1CONFIG GPDMA_CONFIG(GPDMA_CHANNEL1)
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#define GPDMA_C2CONFIG GPDMA_CONFIG(GPDMA_CHANNEL2)
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#define GPDMA_C3CONFIG GPDMA_CONFIG(GPDMA_CHANNEL3)
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#define GPDMA_C4CONFIG GPDMA_CONFIG(GPDMA_CHANNEL4)
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#define GPDMA_C5CONFIG GPDMA_CONFIG(GPDMA_CHANNEL5)
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#define GPDMA_C6CONFIG GPDMA_CONFIG(GPDMA_CHANNEL6)
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#define GPDMA_C7CONFIG GPDMA_CONFIG(GPDMA_CHANNEL7)
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2012-05-29 21:12:04 +00:00
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#endif
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