431 lines
15 KiB
C
431 lines
15 KiB
C
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2019 Brian Viele <vielster@allocor.tech>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_RCC_H
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#define LIBOPENCM3_RCC_H
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#include <libopencm3/stm32/h7/pwr.h>
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/**@{*/
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/* --- RCC registers ------------------------------------------------------- */
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#define RCC_CR MMIO32(RCC_BASE + 0x000)
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#define RCC_CFGR MMIO32(RCC_BASE + 0x010)
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/** @addtogroup rcc_cr_values RCC_CR_VALUES
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* @ingroup rcc_registers
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@{*/
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#define RCC_CR_PLL3AIRDY (1 << 29)
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#define RCC_CR_PLL3AION (1 << 28)
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#define RCC_CR_PLL2RDY (1 << 27)
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#define RCC_CR_PLL2ON (1 << 26)
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#define RCC_CR_PLL1RDY (1 << 25)
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#define RCC_CR_PLL1ON (1 << 24)
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#define RCC_CR_HSECSSON (1 << 19)
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#define RCC_CR_HSEBYP (1 << 18)
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#define RCC_CR_HSERDY (1 << 17)
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#define RCC_CR_HSEON (1 << 16)
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#define RCC_CR_D2CKRDY (1 << 15)
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#define RCC_CR_D1CKRDY (1 << 14)
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#define RCC_CR_HSI48RDY (1 << 13)
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#define RCC_CR_HSI48ON (1 << 12)
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#define RCC_CR_CSIKERON (1 << 9)
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#define RCC_CR_CSIRDY (1 << 8)
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#define RCC_CR_CSION (1 << 7)
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#define RCC_CR_HSIDIVF (1 << 5)
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#define RCC_CR_HSIDIV_MASK (0x03)
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#define RCC_CR_HSIDIV_SHIFT 3
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#define RCC_CR_HSIDIV(n) (((n) & RCC_CR_HSIDIV_MASK) << RCC_CR_HSIDIV_MASK)
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#define RCC_CR_HSIRDY (1 << 2)
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#define RCC_CR_HSIKERON (1 << 1)
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#define RCC_CR_HSION (1 << 0)
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/**@}*/
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/** @addtogroup rcc_rstr_values RCC_RSTR_VALUES
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* @ingroup rcc_registers
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@{*/
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#define RCC_AHB1RSTR MMIO32(RCC_BASE + 0x080)
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#define RCC_AHB2RSTR MMIO32(RCC_BASE + 0x084)
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#define RCC_AHB3RSTR MMIO32(RCC_BASE + 0x07C)
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#define RCC_AHB4RSTR MMIO32(RCC_BASE + 0x088)
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#define RCC_APB1LRSTR MMIO32(RCC_BASE + 0x090)
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#define RCC_APB1HRSTR MMIO32(RCC_BASE + 0x094)
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#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x098)
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#define RCC_APB3RSTR MMIO32(RCC_BASE + 0x08C)
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#define RCC_APB4RSTR MMIO32(RCC_BASE + 0x09C)
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#define RCC_AHB1ENR MMIO32(RCC_BASE + 0x0D8)
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#define RCC_AHB2ENR MMIO32(RCC_BASE + 0x0DC)
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#define RCC_AHB3ENR MMIO32(RCC_BASE + 0x0D4)
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#define RCC_AHB4ENR MMIO32(RCC_BASE + 0x0E0)
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#define RCC_APB1LENR MMIO32(RCC_BASE + 0x0E8)
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#define RCC_APB1HENR MMIO32(RCC_BASE + 0x0EC)
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#define RCC_APB2ENR MMIO32(RCC_BASE + 0x0F0)
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#define RCC_APB3ENR MMIO32(RCC_BASE + 0x0E4)
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#define RCC_APB4ENR MMIO32(RCC_BASE + 0x0F4)
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#define RCC_AHB1LPENR MMIO32(RCC_BASE + 0x100)
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#define RCC_AHB2LPENR MMIO32(RCC_BASE + 0x104)
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#define RCC_AHB4LPENR MMIO32(RCC_BASE + 0x108)
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#define RCC_APB1LLPENR MMIO32(RCC_BASE + 0x110)
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#define RCC_APB1HLPENR MMIO32(RCC_BASE + 0x114)
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#define RCC_APB2LPENR MMIO32(RCC_BASE + 0x118)
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#define RCC_APB3LPENR MMIO32(RCC_BASE + 0x10C)
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#define RCC_APB4LPENR MMIO32(RCC_BASE + 0x11C)
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#define RCC_BDCR MMIO32(RCC_BASE + 0x70)
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#define RCC_CSR MMIO32(RCC_BASE + 0x74)
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#define RCC_SSCGR MMIO32(RCC_BASE + 0x80)
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#define RCC_PLLI2SCFGR MMIO32(RCC_BASE + 0x84)
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#define RCC_PLLSAICFGR MMIO32(RCC_BASE + 0x88)
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#define RCC_DCKCFGR1 MMIO32(RCC_BASE + 0x8C)
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#define RCC_DCKCFGR2 MMIO32(RCC_BASE + 0x90)
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/**@}*/
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/** @addtogroup rcc_cfgr_values RCC_CFGR_VALUES
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* @ingroup rcc_registers
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@{*/
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/* MCO2: Microcontroller clock output 2 */
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#define RCC_CFGR_MCO2_MASK 0x7
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#define RCC_CFGR_MCO2_SHIFT 29
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#define RCC_CFGR_MCO2_SYSCLK 0x0
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#define RCC_CFGR_MCO2_PLL2 0x1
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#define RCC_CFGR_MCO2_HSE 0x2
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#define RCC_CFGR_MCO2_PLL1 0x3
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#define RCC_CFGR_MCO2_CSI 0x4
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#define RCC_CFGR_MCO2_LSI 0x5
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/* MCO1/2PRE: MCO Prescalers */
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#define RCC_CFGR_MCOPRE_MASK 0xf
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#define RCC_CFGR_MCO2PRE_SHIFT 25
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#define RCC_CFGR_MCO1PRE_SHIFT 18
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#define RCC_CFGR_MCOPRE_DIV_NONE 0x0
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#define RCC_CFGR_MCOPRE_DIV_BYP 0x1
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#define RCC_CFGR_MCOPRE_DIV_2 0x2
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#define RCC_CFGR_MCOPRE_DIV_3 0x3
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#define RCC_CFGR_MCOPRE_DIV_4 0x4
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/* Note: MCOPRE_DIV can go from 1 - 15 */
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/* MCO1: Microcontroller clock output 1 */
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#define RCC_CFGR_MCO1_MASK 0x7
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#define RCC_CFGR_MCO1_SHIFT 22
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#define RCC_CFGR_MCO1_HSI 0x0
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#define RCC_CFGR_MCO1_LSE 0x1
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#define RCC_CFGR_MCO1_HSE 0x2
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#define RCC_CFGR_MCO1_PLL1 0x3
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#define RCC_CFGR_MCO1_HSI48 0x4
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#define RCC_CFGR_MCO_SHIFT RCC_CFGR_MCO1_SHIFT
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#define RCC_CFGR_MCO_MASK RCC_CFGR_MCO1_MASK
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/* RTCPRE: HSE division factor for RTC clock */
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#define RCC_CFGR_RTCPRE_SHIFT 8
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#define RCC_CFGR_RTCPRE_MASK 0x3f
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/* SWS: System clock switch status */
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#define RCC_CFGR_SWS_SHIFT 3
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#define RCC_CFGR_SWS_MASK 0x7
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#define RCC_CFGR_SWS_HSI 0x0
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#define RCC_CFGR_SWS_CSI 0x1
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#define RCC_CFGR_SWS_HSE 0x2
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#define RCC_CFGR_SWS_PLL1 0x3
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/* SW: System clock switch */
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#define RCC_CFGR_SW_SHIFT 0
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#define RCC_CFGR_SW_MASK 0x7
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#define RCC_CFGR_SW_HSI 0x0
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#define RCC_CFGR_SW_CSI 0x1
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#define RCC_CFGR_SW_HSE 0x2
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#define RCC_CFGR_SW_PLL1 0x3
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/**@}*/
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/** @addtogroup rcc_bdcr_values RCC_BDCR_VALUES
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* @ingroup rcc_registers
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@{*/
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#define RCC_BDCR_BDRST (1 << 16)
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#define RCC_BDCR_RTCEN (1 << 15)
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#define RCC_BDCR_RTCSEL_MASK 0x3
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#define RCC_BDCR_RTCSEL_SHIFT 8
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#define RCC_BDCR_RTCSEL_NONE 0
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#define RCC_BDCR_RTCSEL_LSE 1
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#define RCC_BDCR_RTCSEL_LSI 2
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#define RCC_BDCR_RTCSEL_HSE 3
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#define RCC_BDCR_LSEDRV_MASK 0x3
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#define RCC_BDCR_LSEDRV_SHIFT 3
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#define RCC_BDCR_LSEDRV_LOW 0
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#define RCC_BDCR_LSEDRV_MEDH 1 /* good job st */
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#define RCC_BDCR_LSEDRV_MEDL 2
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#define RCC_BDCR_LSEDRV_HIGH 3
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#define RCC_BDCR_LSEBYP (1 << 2)
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#define RCC_BDCR_LSERDY (1 << 1)
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#define RCC_BDCR_LSEON (1 << 0)
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/**@}*/
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/** @addtogroup rcc_bdcr_values RCC_CSR_VALUES
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* @ingroup rcc_registers
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@{*/
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#define RCC_CSR_LSIRDY (1 << 1)
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#define RCC_CSR_LSION (1 << 0)
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/**@}*/
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extern uint32_t rcc_ahb_frequency;
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extern uint32_t rcc_apb1_frequency;
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extern uint32_t rcc_apb2_frequency;
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enum rcc_osc {
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RCC_PLL,
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RCC_HSE,
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RCC_HSI,
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RCC_LSE,
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RCC_LSI
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};
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#define _REG_BIT(base, bit) (((base) << 5) + (bit))
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enum rcc_periph_clken {
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/* AHB1 peripherals */
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RCC_DMA1 = _REG_BIT(0xD8, 0),
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RCC_DMA2 = _REG_BIT(0xD8, 1),
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RCC_ADC12 = _REG_BIT(0xD8, 5),
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RCC_ETH1MAC = _REG_BIT(0xD8, 15),
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RCC_ETH1TX = _REG_BIT(0xD8, 16),
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RCC_ETH1RX = _REG_BIT(0xD8, 17),
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RCC_USB2OTGHSULPIEN = _REG_BIT(0xD8, 18),
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RCC_USB1OTGHSEN = _REG_BIT(0xD8, 25),
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RCC_USB1OTGHSULPIEN = _REG_BIT(0xD8, 26),
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RCC_USB2OTGHSEN = _REG_BIT(0xD8, 27),
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/* AHB2 peripherals */
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RCC_DCMI = _REG_BIT(0xDC, 0),
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RCC_CRYP = _REG_BIT(0xDC, 4),
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RCC_HASH = _REG_BIT(0xDC, 5),
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RCC_RNG = _REG_BIT(0xDC, 6),
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RCC_SDMMC2 = _REG_BIT(0xDC, 9),
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RCC_SRAM1 = _REG_BIT(0xDC, 29),
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RCC_SRAM2 = _REG_BIT(0xDC, 30),
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RCC_SRAM3 = _REG_BIT(0xDC, 31),
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/* AHB3 peripherals */
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RCC_MDMA = _REG_BIT(0xD4, 0),
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RCC_DMA2D = _REG_BIT(0xD4, 4),
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RCC_JPGDEC = _REG_BIT(0xD4, 5),
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RCC_FMC = _REG_BIT(0xD4, 12),
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RCC_QSPI = _REG_BIT(0xD4, 14),
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RCC_SDMMC1 = _REG_BIT(0xD4, 16),
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/* AHB4 peripherals*/
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RCC_GPIOA = _REG_BIT(0xE0, 0),
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RCC_GPIOB = _REG_BIT(0xE0, 1),
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RCC_GPIOC = _REG_BIT(0xE0, 2),
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RCC_GPIOD = _REG_BIT(0xE0, 3),
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RCC_GPIOE = _REG_BIT(0xE0, 4),
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RCC_GPIOF = _REG_BIT(0xE0, 5),
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RCC_GPIOG = _REG_BIT(0xE0, 6),
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RCC_GPIOH = _REG_BIT(0xE0, 7),
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RCC_GPIOI = _REG_BIT(0xE0, 8),
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RCC_GPIOJ = _REG_BIT(0xE0, 9),
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RCC_GPIOK = _REG_BIT(0xE0, 10),
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RCC_CRC = _REG_BIT(0xE0, 19),
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RCC_BDMA = _REG_BIT(0xE0, 21),
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RCC_ADC3 = _REG_BIT(0xE0, 24),
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RCC_HSEM = _REG_BIT(0xE0, 25),
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RCC_BKPSRAM = _REG_BIT(0xE0, 28),
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/* APB1L peripherals*/
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RCC_TIM2 = _REG_BIT(0xE8, 0),
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RCC_TIM3 = _REG_BIT(0xE8, 1),
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RCC_TIM4 = _REG_BIT(0xE8, 2),
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RCC_TIM5 = _REG_BIT(0xE8, 3),
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RCC_TIM6 = _REG_BIT(0xE8, 4),
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RCC_TIM7 = _REG_BIT(0xE8, 5),
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RCC_TIM12 = _REG_BIT(0xE8, 6),
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RCC_TIM13 = _REG_BIT(0xE8, 7),
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RCC_TIM14 = _REG_BIT(0xE8, 8),
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RCC_LPTIM1 = _REG_BIT(0xE8, 9),
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RCC_SPI2 = _REG_BIT(0xE8, 14),
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RCC_SPI3 = _REG_BIT(0xE8, 15),
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RCC_SPDIFRX = _REG_BIT(0xE8, 16),
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RCC_USART2 = _REG_BIT(0xE8, 17),
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RCC_USART3 = _REG_BIT(0xE8, 18),
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RCC_UART4 = _REG_BIT(0xE8, 19),
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RCC_UART5 = _REG_BIT(0xE8, 20),
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RCC_I2C1 = _REG_BIT(0xE8, 21),
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RCC_I2C2 = _REG_BIT(0xE8, 22),
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RCC_I2C3 = _REG_BIT(0xE8, 23),
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RCC_CEC = _REG_BIT(0xE8, 27),
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RCC_DAC = _REG_BIT(0xE8, 29),
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RCC_UART7 = _REG_BIT(0xE8, 30),
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RCC_UART8 = _REG_BIT(0xE8, 31),
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/* APB1H peripherals*/
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RCC_CRS = _REG_BIT(0xEC, 1),
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RCC_SWP = _REG_BIT(0xEC, 2),
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RCC_OPAMP = _REG_BIT(0xEC, 4),
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RCC_MDIO = _REG_BIT(0xEC, 5),
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RCC_FDCAN = _REG_BIT(0xEC, 8),
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/* APB2 peripherals */
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RCC_TIM1 = _REG_BIT(0xF0, 0),
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RCC_TIM8 = _REG_BIT(0xF0, 1),
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RCC_USART1 = _REG_BIT(0xF0, 4),
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RCC_USART6 = _REG_BIT(0xF0, 5),
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RCC_SPI1 = _REG_BIT(0xF0, 12),
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RCC_SPI4 = _REG_BIT(0xF0, 13),
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RCC_TIM15 = _REG_BIT(0xF0, 16),
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RCC_TIM16 = _REG_BIT(0xF0, 17),
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RCC_TIM17 = _REG_BIT(0xF0, 18),
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RCC_SPI5 = _REG_BIT(0xF0, 20),
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RCC_SAI1 = _REG_BIT(0xF0, 22),
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RCC_SAI2 = _REG_BIT(0xF0, 23),
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RCC_SAI3 = _REG_BIT(0xF0, 24),
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RCC_DFSDM = _REG_BIT(0xF0, 28),
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RCC_HRTIM = _REG_BIT(0xF0, 29),
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/* APB3 peripherals */
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RCC_LTDCEN = _REG_BIT(0xE4, 3),
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RCC_WWDG1EN = _REG_BIT(0xE4, 6),
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/* APB4 peripherals */
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RCC_SYSCFG = _REG_BIT(0xF4, 1),
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RCC_LPUART1 = _REG_BIT(0xF4, 3),
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RCC_SPI6 = _REG_BIT(0xF4, 5),
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RCC_I2C4 = _REG_BIT(0xF4, 7),
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RCC_LPTIM2 = _REG_BIT(0xF4, 9),
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RCC_LPTIM3 = _REG_BIT(0xF4, 10),
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RCC_LPTIM4 = _REG_BIT(0xF4, 11),
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RCC_LPTIM5 = _REG_BIT(0xF4, 12),
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RCC_COMP12 = _REG_BIT(0xF4, 14),
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RCC_VREF = _REG_BIT(0xF4, 15),
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RCC_RTCAPB = _REG_BIT(0xF4, 16),
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RCC_SAI4 = _REG_BIT(0xF4, 21),
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};
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enum rcc_periph_rst {
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/* AHB1 peripherals */
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RST_DMA1 = _REG_BIT(0x80, 0),
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RST_DMA2 = _REG_BIT(0x80, 1),
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RST_ADC12 = _REG_BIT(0x80, 5),
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RST_ETH1MAC = _REG_BIT(0x80, 15),
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RST_USB1OTGRST = _REG_BIT(0x80, 25),
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RST_USB2OTGRST = _REG_BIT(0x80, 27),
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/* AHB2 peripherals */
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RST_DCMI = _REG_BIT(0xDC, 0),
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RST_CRYP = _REG_BIT(0xDC, 4),
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RST_HASH = _REG_BIT(0xDC, 5),
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RST_RNG = _REG_BIT(0xDC, 6),
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RST_SDMMC2 = _REG_BIT(0xDC, 9),
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/* AHB3 peripherals */
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RST_MDMA = _REG_BIT(0x7C, 0),
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|
RST_DMA2D = _REG_BIT(0x7C, 4),
|
||
|
RST_JPGDEC = _REG_BIT(0x7C, 5),
|
||
|
RST_FMC = _REG_BIT(0x7C, 12),
|
||
|
RST_QSPI = _REG_BIT(0x7C, 14),
|
||
|
RST_SDMMC1 = _REG_BIT(0x7C, 16),
|
||
|
|
||
|
/* AHB4 peripherals*/
|
||
|
RST_GPIOA = _REG_BIT(0x88, 0),
|
||
|
RST_GPIOB = _REG_BIT(0x88, 1),
|
||
|
RST_GPIOC = _REG_BIT(0x88, 2),
|
||
|
RST_GPIOD = _REG_BIT(0x88, 3),
|
||
|
RST_GPIOE = _REG_BIT(0x88, 4),
|
||
|
RST_GPIOF = _REG_BIT(0x88, 5),
|
||
|
RST_GPIOG = _REG_BIT(0x88, 6),
|
||
|
RST_GPIOH = _REG_BIT(0x88, 7),
|
||
|
RST_GPIOI = _REG_BIT(0x88, 8),
|
||
|
RST_GPIOJ = _REG_BIT(0x88, 9),
|
||
|
RST_GPIOK = _REG_BIT(0x88, 10),
|
||
|
RST_CRC = _REG_BIT(0x88, 19),
|
||
|
RST_BDMA = _REG_BIT(0x88, 21),
|
||
|
RST_ADC3 = _REG_BIT(0x88, 24),
|
||
|
RST_HSEM = _REG_BIT(0x88, 25),
|
||
|
|
||
|
/* APB1L peripherals*/
|
||
|
RST_TIM2 = _REG_BIT(0x90, 0),
|
||
|
RST_TIM3 = _REG_BIT(0x90, 1),
|
||
|
RST_TIM4 = _REG_BIT(0x90, 2),
|
||
|
RST_TIM5 = _REG_BIT(0x90, 3),
|
||
|
RST_TIM6 = _REG_BIT(0x90, 4),
|
||
|
RST_TIM7 = _REG_BIT(0x90, 5),
|
||
|
RST_TIM12 = _REG_BIT(0x90, 6),
|
||
|
RST_TIM13 = _REG_BIT(0x90, 7),
|
||
|
RST_TIM14 = _REG_BIT(0x90, 8),
|
||
|
RST_LPTIM1 = _REG_BIT(0x90, 9),
|
||
|
RST_SPI2 = _REG_BIT(0x90, 14),
|
||
|
RST_SPI3 = _REG_BIT(0x90, 15),
|
||
|
RST_SPDIFRX = _REG_BIT(0x90, 16),
|
||
|
RST_USART2 = _REG_BIT(0x90, 17),
|
||
|
RST_USART3 = _REG_BIT(0x90, 18),
|
||
|
RST_UART4 = _REG_BIT(0x90, 19),
|
||
|
RST_UART5 = _REG_BIT(0x90, 20),
|
||
|
RST_I2C1 = _REG_BIT(0x90, 21),
|
||
|
RST_I2C2 = _REG_BIT(0x90, 22),
|
||
|
RST_I2C3 = _REG_BIT(0x90, 23),
|
||
|
RST_CEC = _REG_BIT(0x90, 27),
|
||
|
RST_DAC = _REG_BIT(0x90, 29),
|
||
|
RST_UART7 = _REG_BIT(0x90, 30),
|
||
|
RST_UART8 = _REG_BIT(0x90, 31),
|
||
|
|
||
|
/* APB1H peripherals*/
|
||
|
RST_CRS = _REG_BIT(0x94, 1),
|
||
|
RST_SWP = _REG_BIT(0x94, 2),
|
||
|
RST_OPAMP = _REG_BIT(0x94, 4),
|
||
|
RST_MDIO = _REG_BIT(0x94, 5),
|
||
|
RST_FDCAN = _REG_BIT(0x94, 8),
|
||
|
|
||
|
/* APB2 peripherals */
|
||
|
RST_TIM1 = _REG_BIT(0x98, 0),
|
||
|
RST_TIM8 = _REG_BIT(0x98, 1),
|
||
|
RST_USART1 = _REG_BIT(0x98, 4),
|
||
|
RST_USART6 = _REG_BIT(0x98, 5),
|
||
|
RST_SPI1 = _REG_BIT(0x98, 12),
|
||
|
RST_SPI4 = _REG_BIT(0x98, 13),
|
||
|
RST_TIM15 = _REG_BIT(0x98, 16),
|
||
|
RST_TIM16 = _REG_BIT(0x98, 17),
|
||
|
RST_TIM17 = _REG_BIT(0x98, 18),
|
||
|
RST_SPI5 = _REG_BIT(0x98, 20),
|
||
|
RST_SAI1 = _REG_BIT(0x98, 22),
|
||
|
RST_SAI2 = _REG_BIT(0x98, 23),
|
||
|
RST_SAI3 = _REG_BIT(0x98, 24),
|
||
|
RST_DFSDM = _REG_BIT(0x98, 28),
|
||
|
RST_HRTIM = _REG_BIT(0x98, 29),
|
||
|
|
||
|
/* APB3 peripherals */
|
||
|
RST_LTDCRST = _REG_BIT(0x8C, 3),
|
||
|
|
||
|
/* APB4 peripherals */
|
||
|
RST_SYSCFG = _REG_BIT(0x9C, 1),
|
||
|
RST_LPUART1 = _REG_BIT(0x9C, 3),
|
||
|
RST_SPI6 = _REG_BIT(0x9C, 5),
|
||
|
RST_I2C4 = _REG_BIT(0x9C, 7),
|
||
|
RST_LPTIM2 = _REG_BIT(0x9C, 9),
|
||
|
RST_LPTIM3 = _REG_BIT(0x9C, 10),
|
||
|
RST_LPTIM4 = _REG_BIT(0x9C, 11),
|
||
|
RST_LPTIM5 = _REG_BIT(0x9C, 12),
|
||
|
RST_COMP12 = _REG_BIT(0x9C, 14),
|
||
|
RST_VREF = _REG_BIT(0x9C, 15),
|
||
|
RST_SAI4 = _REG_BIT(0x9C, 21),
|
||
|
};
|
||
|
|
||
|
#undef _REG_BIT
|
||
|
|
||
|
#include <libopencm3/stm32/common/rcc_common_all.h>
|
||
|
|
||
|
/**@}*/
|
||
|
|
||
|
#endif
|