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ice40-usbtrace
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hardware: connect VBUS_DUT to U3 (IP4234CZ6)

This commit is contained in:
Martin Schramm 2022-08-24 11:18:51 +02:00
parent a1480d3d46
commit 8c360f3a6e
3 changed files with 18 additions and 14 deletions
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hardware/eagle/ice40-usbtrace-schema.pdf
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15
hardware/eagle/ice40-usbtrace.brd
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@ -3036,7 +3036,11 @@ design rules under a new name.</description>
<wire x1="50.165" y1="118.4275" x2="55.03846875" y2="113.55403125" width="1" layer="1"/>
<wire x1="55.03846875" y1="112.49379375" x2="55.03846875" y2="113.55403125" width="1" layer="1"/>
<wire x1="60.96" y1="102.235" x2="55.03846875" y2="108.15653125" width="0.8128" layer="1"/>
<wire x1="55.03846875" y1="112.49379375" x2="55.03846875" y2="108.15653125" width="0.8128" layer="1"/>
<wire x1="55.03846875" y1="112.49379375" x2="55.03846875" y2="108.2675" width="0.8128" layer="1"/>
<contactref element="U4" pad="5"/>
<wire x1="55.03846875" y1="108.2675" x2="55.03846875" y2="108.15653125" width="0.8128" layer="1"/>
<wire x1="38.59" y1="106.3625" x2="53.13346875" y2="106.3625" width="0.6" layer="1"/>
<wire x1="53.13346875" y1="106.3625" x2="55.03846875" y2="108.2675" width="0.6" layer="1"/>
</signal>
<signal name="N$3_N" class="1">
<contactref element="J2" pad="2"/>
@ -3121,13 +3125,15 @@ design rules under a new name.</description>
<contactref element="IC3" pad="4"/>
<contactref element="R11" pad="1"/>
<wire x1="36.515" y1="99.82375" x2="36.515" y2="97.983" width="0.3048" layer="1"/>
<wire x1="36.515" y1="97.983" x2="36.5125" y2="97.663" width="0" layer="19" extent="1-1"/>
<wire x1="36.515" y1="97.983" x2="36.515" y2="97.6655" width="0.3" layer="1"/>
<wire x1="36.515" y1="97.6655" x2="36.5125" y2="97.663" width="0.3" layer="1"/>
</signal>
<signal name="N$13">
<contactref element="IC3" pad="6"/>
<contactref element="R10" pad="1"/>
<wire x1="38.415" y1="99.82375" x2="38.415" y2="97.983" width="0.3048" layer="1"/>
<wire x1="38.415" y1="97.983" x2="38.4175" y2="97.663" width="0" layer="19" extent="1-1"/>
<wire x1="38.415" y1="97.983" x2="38.415" y2="97.6655" width="0.3" layer="1"/>
<wire x1="38.415" y1="97.6655" x2="38.4175" y2="97.663" width="0.3" layer="1"/>
</signal>
<signal name="TAP_D_P" class="1">
<contactref element="R10" pad="2"/>
@ -3341,9 +3347,6 @@ design rules under a new name.</description>
<wire x1="36.515" y1="102.42375" x2="36.515" y2="105.2375" width="0.3" layer="1"/>
<wire x1="36.515" y1="105.2375" x2="36.34" y2="105.4125" width="0.3" layer="1"/>
</signal>
<signal name="N$16">
<contactref element="U4" pad="5"/>
</signal>
</signals>
</board>
</drawing>

17
hardware/eagle/ice40-usbtrace.sch
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@ -7712,9 +7712,16 @@ round, layers 1 + 16 + 21 + 39 + 49</description>
<pinref part="J3" gate="G$1" pin="VBUS"/>
<wire x1="157.48" y1="157.48" x2="160.02" y2="157.48" width="0.1524" layer="91"/>
<wire x1="160.02" y1="157.48" x2="175.26" y2="157.48" width="0.1524" layer="91"/>
<wire x1="160.02" y1="157.48" x2="160.02" y2="175.26" width="0.1524" layer="91"/>
<wire x1="160.02" y1="157.48" x2="160.02" y2="185.42" width="0.1524" layer="91"/>
<junction x="160.02" y="157.48"/>
<label x="160.02" y="175.26" size="1.27" layer="95" rot="R90" xref="yes"/>
<label x="160.02" y="187.96" size="1.27" layer="95" rot="R90" xref="yes"/>
<pinref part="U4" gate="G$1" pin="VCC"/>
<wire x1="160.02" y1="185.42" x2="160.02" y2="187.96" width="0.1524" layer="91"/>
<wire x1="185.42" y1="187.96" x2="185.42" y2="190.5" width="0.1524" layer="91"/>
<wire x1="185.42" y1="190.5" x2="165.1" y2="190.5" width="0.1524" layer="91"/>
<wire x1="165.1" y1="190.5" x2="165.1" y2="185.42" width="0.1524" layer="91"/>
<wire x1="165.1" y1="185.42" x2="160.02" y2="185.42" width="0.1524" layer="91"/>
<junction x="160.02" y="185.42"/>
</segment>
<segment>
<pinref part="JP1" gate="1" pin="3"/>
@ -8032,12 +8039,6 @@ round, layers 1 + 16 + 21 + 39 + 49</description>
<wire x1="200.66" y1="172.72" x2="203.2" y2="172.72" width="0.1524" layer="91"/>
</segment>
</net>
<net name="N$16" class="0">
<segment>
<pinref part="U4" gate="G$1" pin="VCC"/>
<wire x1="185.42" y1="187.96" x2="185.42" y2="190.5" width="0.1524" layer="91"/>
</segment>
</net>
</nets>
</sheet>
</sheets>