62550cd7c0
It might be not good to use software defined version to identify sdma device type, when hardware does not define such version. Instead, soc name is stable enough to define the device type. The patch uses platform_device_id rather than version number passed by platform data to identify sdma device type/version. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Cc: Vinod Koul <vinod.koul@intel.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Vinod Koul <vinod.koul@intel.com>
631 lines
18 KiB
C
631 lines
18 KiB
C
/*
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* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/clkdev.h>
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#include <asm/div64.h>
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#include <mach/clock.h>
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#include <mach/hardware.h>
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#include <mach/mx31.h>
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#include <mach/common.h>
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#include "crmregs-imx31.h"
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#define PRE_DIV_MIN_FREQ 10000000 /* Minimum Frequency after Predivider */
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static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post)
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{
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u32 min_pre, temp_pre, old_err, err;
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if (div >= 512) {
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*pre = 8;
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*post = 64;
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} else if (div >= 64) {
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min_pre = (div - 1) / 64 + 1;
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old_err = 8;
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for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
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err = div % temp_pre;
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if (err == 0) {
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*pre = temp_pre;
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break;
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}
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err = temp_pre - err;
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if (err < old_err) {
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old_err = err;
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*pre = temp_pre;
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}
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}
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*post = (div + *pre - 1) / *pre;
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} else if (div <= 8) {
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*pre = div;
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*post = 1;
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} else {
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*pre = 1;
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*post = div;
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}
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}
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static struct clk mcu_pll_clk;
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static struct clk serial_pll_clk;
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static struct clk ipg_clk;
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static struct clk ckih_clk;
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static int cgr_enable(struct clk *clk)
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{
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u32 reg;
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if (!clk->enable_reg)
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return 0;
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reg = __raw_readl(clk->enable_reg);
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reg |= 3 << clk->enable_shift;
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__raw_writel(reg, clk->enable_reg);
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return 0;
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}
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static void cgr_disable(struct clk *clk)
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{
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u32 reg;
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if (!clk->enable_reg)
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return;
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reg = __raw_readl(clk->enable_reg);
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reg &= ~(3 << clk->enable_shift);
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/* special case for EMI clock */
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if (clk->enable_reg == MXC_CCM_CGR2 && clk->enable_shift == 8)
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reg |= (1 << clk->enable_shift);
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__raw_writel(reg, clk->enable_reg);
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}
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static unsigned long pll_ref_get_rate(void)
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{
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unsigned long ccmr;
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unsigned int prcs;
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ccmr = __raw_readl(MXC_CCM_CCMR);
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prcs = (ccmr & MXC_CCM_CCMR_PRCS_MASK) >> MXC_CCM_CCMR_PRCS_OFFSET;
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if (prcs == 0x1)
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return CKIL_CLK_FREQ * 1024;
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else
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return clk_get_rate(&ckih_clk);
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}
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static unsigned long usb_pll_get_rate(struct clk *clk)
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{
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unsigned long reg;
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reg = __raw_readl(MXC_CCM_UPCTL);
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return mxc_decode_pll(reg, pll_ref_get_rate());
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}
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static unsigned long serial_pll_get_rate(struct clk *clk)
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{
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unsigned long reg;
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reg = __raw_readl(MXC_CCM_SRPCTL);
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return mxc_decode_pll(reg, pll_ref_get_rate());
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}
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static unsigned long mcu_pll_get_rate(struct clk *clk)
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{
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unsigned long reg, ccmr;
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ccmr = __raw_readl(MXC_CCM_CCMR);
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if (!(ccmr & MXC_CCM_CCMR_MPE) || (ccmr & MXC_CCM_CCMR_MDS))
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return clk_get_rate(&ckih_clk);
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reg = __raw_readl(MXC_CCM_MPCTL);
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return mxc_decode_pll(reg, pll_ref_get_rate());
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}
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static int usb_pll_enable(struct clk *clk)
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{
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u32 reg;
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reg = __raw_readl(MXC_CCM_CCMR);
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reg |= MXC_CCM_CCMR_UPE;
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__raw_writel(reg, MXC_CCM_CCMR);
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/* No lock bit on MX31, so using max time from spec */
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udelay(80);
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return 0;
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}
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static void usb_pll_disable(struct clk *clk)
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{
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u32 reg;
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reg = __raw_readl(MXC_CCM_CCMR);
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reg &= ~MXC_CCM_CCMR_UPE;
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__raw_writel(reg, MXC_CCM_CCMR);
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}
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static int serial_pll_enable(struct clk *clk)
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{
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u32 reg;
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reg = __raw_readl(MXC_CCM_CCMR);
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reg |= MXC_CCM_CCMR_SPE;
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__raw_writel(reg, MXC_CCM_CCMR);
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/* No lock bit on MX31, so using max time from spec */
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udelay(80);
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return 0;
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}
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static void serial_pll_disable(struct clk *clk)
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{
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u32 reg;
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reg = __raw_readl(MXC_CCM_CCMR);
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reg &= ~MXC_CCM_CCMR_SPE;
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__raw_writel(reg, MXC_CCM_CCMR);
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}
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#define PDR0(mask, off) ((__raw_readl(MXC_CCM_PDR0) & mask) >> off)
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#define PDR1(mask, off) ((__raw_readl(MXC_CCM_PDR1) & mask) >> off)
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#define PDR2(mask, off) ((__raw_readl(MXC_CCM_PDR2) & mask) >> off)
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static unsigned long mcu_main_get_rate(struct clk *clk)
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{
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u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0);
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if ((pmcr0 & MXC_CCM_PMCR0_DFSUP1) == MXC_CCM_PMCR0_DFSUP1_SPLL)
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return clk_get_rate(&serial_pll_clk);
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else
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return clk_get_rate(&mcu_pll_clk);
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}
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static unsigned long ahb_get_rate(struct clk *clk)
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{
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unsigned long max_pdf;
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max_pdf = PDR0(MXC_CCM_PDR0_MAX_PODF_MASK,
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MXC_CCM_PDR0_MAX_PODF_OFFSET);
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return clk_get_rate(clk->parent) / (max_pdf + 1);
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}
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static unsigned long ipg_get_rate(struct clk *clk)
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{
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unsigned long ipg_pdf;
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ipg_pdf = PDR0(MXC_CCM_PDR0_IPG_PODF_MASK,
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MXC_CCM_PDR0_IPG_PODF_OFFSET);
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return clk_get_rate(clk->parent) / (ipg_pdf + 1);
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}
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static unsigned long nfc_get_rate(struct clk *clk)
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{
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unsigned long nfc_pdf;
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nfc_pdf = PDR0(MXC_CCM_PDR0_NFC_PODF_MASK,
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MXC_CCM_PDR0_NFC_PODF_OFFSET);
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return clk_get_rate(clk->parent) / (nfc_pdf + 1);
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}
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static unsigned long hsp_get_rate(struct clk *clk)
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{
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unsigned long hsp_pdf;
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hsp_pdf = PDR0(MXC_CCM_PDR0_HSP_PODF_MASK,
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MXC_CCM_PDR0_HSP_PODF_OFFSET);
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return clk_get_rate(clk->parent) / (hsp_pdf + 1);
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}
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static unsigned long usb_get_rate(struct clk *clk)
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{
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unsigned long usb_pdf, usb_prepdf;
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usb_pdf = PDR1(MXC_CCM_PDR1_USB_PODF_MASK,
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MXC_CCM_PDR1_USB_PODF_OFFSET);
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usb_prepdf = PDR1(MXC_CCM_PDR1_USB_PRDF_MASK,
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MXC_CCM_PDR1_USB_PRDF_OFFSET);
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return clk_get_rate(clk->parent) / (usb_prepdf + 1) / (usb_pdf + 1);
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}
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static unsigned long csi_get_rate(struct clk *clk)
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{
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u32 reg, pre, post;
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reg = __raw_readl(MXC_CCM_PDR0);
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pre = (reg & MXC_CCM_PDR0_CSI_PRDF_MASK) >>
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MXC_CCM_PDR0_CSI_PRDF_OFFSET;
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pre++;
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post = (reg & MXC_CCM_PDR0_CSI_PODF_MASK) >>
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MXC_CCM_PDR0_CSI_PODF_OFFSET;
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post++;
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return clk_get_rate(clk->parent) / (pre * post);
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}
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static unsigned long csi_round_rate(struct clk *clk, unsigned long rate)
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{
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u32 pre, post, parent = clk_get_rate(clk->parent);
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u32 div = parent / rate;
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if (parent % rate)
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div++;
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__calc_pre_post_dividers(div, &pre, &post);
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return parent / (pre * post);
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}
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static int csi_set_rate(struct clk *clk, unsigned long rate)
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{
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u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
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div = parent / rate;
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if ((parent / div) != rate)
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return -EINVAL;
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__calc_pre_post_dividers(div, &pre, &post);
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/* Set CSI clock divider */
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reg = __raw_readl(MXC_CCM_PDR0) &
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~(MXC_CCM_PDR0_CSI_PODF_MASK | MXC_CCM_PDR0_CSI_PRDF_MASK);
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reg |= (post - 1) << MXC_CCM_PDR0_CSI_PODF_OFFSET;
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reg |= (pre - 1) << MXC_CCM_PDR0_CSI_PRDF_OFFSET;
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__raw_writel(reg, MXC_CCM_PDR0);
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return 0;
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}
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static unsigned long ssi1_get_rate(struct clk *clk)
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{
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unsigned long ssi1_pdf, ssi1_prepdf;
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ssi1_pdf = PDR1(MXC_CCM_PDR1_SSI1_PODF_MASK,
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MXC_CCM_PDR1_SSI1_PODF_OFFSET);
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ssi1_prepdf = PDR1(MXC_CCM_PDR1_SSI1_PRE_PODF_MASK,
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MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET);
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return clk_get_rate(clk->parent) / (ssi1_prepdf + 1) / (ssi1_pdf + 1);
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}
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static unsigned long ssi2_get_rate(struct clk *clk)
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{
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unsigned long ssi2_pdf, ssi2_prepdf;
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ssi2_pdf = PDR1(MXC_CCM_PDR1_SSI2_PODF_MASK,
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MXC_CCM_PDR1_SSI2_PODF_OFFSET);
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ssi2_prepdf = PDR1(MXC_CCM_PDR1_SSI2_PRE_PODF_MASK,
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MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET);
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return clk_get_rate(clk->parent) / (ssi2_prepdf + 1) / (ssi2_pdf + 1);
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}
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static unsigned long firi_get_rate(struct clk *clk)
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{
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unsigned long firi_pdf, firi_prepdf;
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firi_pdf = PDR1(MXC_CCM_PDR1_FIRI_PODF_MASK,
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MXC_CCM_PDR1_FIRI_PODF_OFFSET);
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firi_prepdf = PDR1(MXC_CCM_PDR1_FIRI_PRE_PODF_MASK,
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MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET);
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return clk_get_rate(clk->parent) / (firi_prepdf + 1) / (firi_pdf + 1);
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}
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static unsigned long firi_round_rate(struct clk *clk, unsigned long rate)
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{
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u32 pre, post;
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u32 parent = clk_get_rate(clk->parent);
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u32 div = parent / rate;
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if (parent % rate)
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div++;
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__calc_pre_post_dividers(div, &pre, &post);
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return parent / (pre * post);
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}
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static int firi_set_rate(struct clk *clk, unsigned long rate)
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{
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u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
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div = parent / rate;
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if ((parent / div) != rate)
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return -EINVAL;
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__calc_pre_post_dividers(div, &pre, &post);
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/* Set FIRI clock divider */
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reg = __raw_readl(MXC_CCM_PDR1) &
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~(MXC_CCM_PDR1_FIRI_PODF_MASK | MXC_CCM_PDR1_FIRI_PRE_PODF_MASK);
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reg |= (pre - 1) << MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET;
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reg |= (post - 1) << MXC_CCM_PDR1_FIRI_PODF_OFFSET;
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__raw_writel(reg, MXC_CCM_PDR1);
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return 0;
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}
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static unsigned long mbx_get_rate(struct clk *clk)
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{
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return clk_get_rate(clk->parent) / 2;
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}
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static unsigned long mstick1_get_rate(struct clk *clk)
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{
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unsigned long msti_pdf;
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msti_pdf = PDR2(MXC_CCM_PDR2_MST1_PDF_MASK,
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MXC_CCM_PDR2_MST1_PDF_OFFSET);
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return clk_get_rate(clk->parent) / (msti_pdf + 1);
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}
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static unsigned long mstick2_get_rate(struct clk *clk)
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{
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unsigned long msti_pdf;
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msti_pdf = PDR2(MXC_CCM_PDR2_MST2_PDF_MASK,
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MXC_CCM_PDR2_MST2_PDF_OFFSET);
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return clk_get_rate(clk->parent) / (msti_pdf + 1);
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}
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static unsigned long ckih_rate;
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static unsigned long clk_ckih_get_rate(struct clk *clk)
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{
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return ckih_rate;
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}
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static unsigned long clk_ckil_get_rate(struct clk *clk)
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{
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return CKIL_CLK_FREQ;
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}
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static struct clk ckih_clk = {
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.get_rate = clk_ckih_get_rate,
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};
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static struct clk mcu_pll_clk = {
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.parent = &ckih_clk,
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.get_rate = mcu_pll_get_rate,
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};
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static struct clk mcu_main_clk = {
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.parent = &mcu_pll_clk,
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.get_rate = mcu_main_get_rate,
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};
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static struct clk serial_pll_clk = {
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.parent = &ckih_clk,
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.get_rate = serial_pll_get_rate,
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.enable = serial_pll_enable,
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.disable = serial_pll_disable,
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};
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static struct clk usb_pll_clk = {
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.parent = &ckih_clk,
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.get_rate = usb_pll_get_rate,
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.enable = usb_pll_enable,
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.disable = usb_pll_disable,
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};
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static struct clk ahb_clk = {
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.parent = &mcu_main_clk,
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.get_rate = ahb_get_rate,
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};
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#define DEFINE_CLOCK(name, i, er, es, gr, s, p) \
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static struct clk name = { \
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.id = i, \
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.enable_reg = er, \
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.enable_shift = es, \
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.get_rate = gr, \
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.enable = cgr_enable, \
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.disable = cgr_disable, \
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.secondary = s, \
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.parent = p, \
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}
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#define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p) \
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static struct clk name = { \
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.id = i, \
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.enable_reg = er, \
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.enable_shift = es, \
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.get_rate = getsetround##_get_rate, \
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.set_rate = getsetround##_set_rate, \
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.round_rate = getsetround##_round_rate, \
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.enable = cgr_enable, \
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.disable = cgr_disable, \
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.secondary = s, \
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.parent = p, \
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}
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DEFINE_CLOCK(perclk_clk, 0, NULL, 0, NULL, NULL, &ipg_clk);
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DEFINE_CLOCK(ckil_clk, 0, NULL, 0, clk_ckil_get_rate, NULL, NULL);
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DEFINE_CLOCK(sdhc1_clk, 0, MXC_CCM_CGR0, 0, NULL, NULL, &perclk_clk);
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DEFINE_CLOCK(sdhc2_clk, 1, MXC_CCM_CGR0, 2, NULL, NULL, &perclk_clk);
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DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CGR0, 4, NULL, NULL, &perclk_clk);
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DEFINE_CLOCK(epit1_clk, 0, MXC_CCM_CGR0, 6, NULL, NULL, &perclk_clk);
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DEFINE_CLOCK(epit2_clk, 1, MXC_CCM_CGR0, 8, NULL, NULL, &perclk_clk);
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DEFINE_CLOCK(iim_clk, 0, MXC_CCM_CGR0, 10, NULL, NULL, &ipg_clk);
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DEFINE_CLOCK(ata_clk, 0, MXC_CCM_CGR0, 12, NULL, NULL, &ipg_clk);
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DEFINE_CLOCK(sdma_clk1, 0, MXC_CCM_CGR0, 14, NULL, NULL, &ahb_clk);
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DEFINE_CLOCK(cspi3_clk, 2, MXC_CCM_CGR0, 16, NULL, NULL, &ipg_clk);
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DEFINE_CLOCK(rng_clk, 0, MXC_CCM_CGR0, 18, NULL, NULL, &ipg_clk);
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DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CGR0, 20, NULL, NULL, &perclk_clk);
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DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CGR0, 22, NULL, NULL, &perclk_clk);
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DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CGR0, 24, ssi1_get_rate, NULL, &serial_pll_clk);
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DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CGR0, 26, NULL, NULL, &perclk_clk);
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DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CGR0, 28, NULL, NULL, &perclk_clk);
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DEFINE_CLOCK(i2c3_clk, 2, MXC_CCM_CGR0, 30, NULL, NULL, &perclk_clk);
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|
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DEFINE_CLOCK(mpeg4_clk, 0, MXC_CCM_CGR1, 0, NULL, NULL, &ahb_clk);
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DEFINE_CLOCK(mstick1_clk, 0, MXC_CCM_CGR1, 2, mstick1_get_rate, NULL, &usb_pll_clk);
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DEFINE_CLOCK(mstick2_clk, 1, MXC_CCM_CGR1, 4, mstick2_get_rate, NULL, &usb_pll_clk);
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DEFINE_CLOCK1(csi_clk, 0, MXC_CCM_CGR1, 6, csi, NULL, &serial_pll_clk);
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DEFINE_CLOCK(rtc_clk, 0, MXC_CCM_CGR1, 8, NULL, NULL, &ckil_clk);
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DEFINE_CLOCK(wdog_clk, 0, MXC_CCM_CGR1, 10, NULL, NULL, &ipg_clk);
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DEFINE_CLOCK(pwm_clk, 0, MXC_CCM_CGR1, 12, NULL, NULL, &perclk_clk);
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|
DEFINE_CLOCK(usb_clk2, 0, MXC_CCM_CGR1, 18, usb_get_rate, NULL, &ahb_clk);
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DEFINE_CLOCK(kpp_clk, 0, MXC_CCM_CGR1, 20, NULL, NULL, &ipg_clk);
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DEFINE_CLOCK(ipu_clk, 0, MXC_CCM_CGR1, 22, hsp_get_rate, NULL, &mcu_main_clk);
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|
DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CGR1, 24, NULL, NULL, &perclk_clk);
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|
DEFINE_CLOCK(uart4_clk, 3, MXC_CCM_CGR1, 26, NULL, NULL, &perclk_clk);
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|
DEFINE_CLOCK(uart5_clk, 4, MXC_CCM_CGR1, 28, NULL, NULL, &perclk_clk);
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|
DEFINE_CLOCK(owire_clk, 0, MXC_CCM_CGR1, 30, NULL, NULL, &perclk_clk);
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|
|
|
DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CGR2, 0, ssi2_get_rate, NULL, &serial_pll_clk);
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|
DEFINE_CLOCK(cspi1_clk, 0, MXC_CCM_CGR2, 2, NULL, NULL, &ipg_clk);
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|
DEFINE_CLOCK(cspi2_clk, 1, MXC_CCM_CGR2, 4, NULL, NULL, &ipg_clk);
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|
DEFINE_CLOCK(mbx_clk, 0, MXC_CCM_CGR2, 6, mbx_get_rate, NULL, &ahb_clk);
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|
DEFINE_CLOCK(emi_clk, 0, MXC_CCM_CGR2, 8, NULL, NULL, &ahb_clk);
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|
DEFINE_CLOCK(rtic_clk, 0, MXC_CCM_CGR2, 10, NULL, NULL, &ahb_clk);
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|
DEFINE_CLOCK1(firi_clk, 0, MXC_CCM_CGR2, 12, firi, NULL, &usb_pll_clk);
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|
|
|
DEFINE_CLOCK(sdma_clk2, 0, NULL, 0, NULL, NULL, &ipg_clk);
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|
DEFINE_CLOCK(usb_clk1, 0, NULL, 0, usb_get_rate, NULL, &usb_pll_clk);
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|
DEFINE_CLOCK(nfc_clk, 0, NULL, 0, nfc_get_rate, NULL, &ahb_clk);
|
|
DEFINE_CLOCK(scc_clk, 0, NULL, 0, NULL, NULL, &ipg_clk);
|
|
DEFINE_CLOCK(ipg_clk, 0, NULL, 0, ipg_get_rate, NULL, &ahb_clk);
|
|
|
|
#define _REGISTER_CLOCK(d, n, c) \
|
|
{ \
|
|
.dev_id = d, \
|
|
.con_id = n, \
|
|
.clk = &c, \
|
|
},
|
|
|
|
static struct clk_lookup lookups[] = {
|
|
_REGISTER_CLOCK(NULL, "emi", emi_clk)
|
|
_REGISTER_CLOCK("imx31-cspi.0", NULL, cspi1_clk)
|
|
_REGISTER_CLOCK("imx31-cspi.1", NULL, cspi2_clk)
|
|
_REGISTER_CLOCK("imx31-cspi.2", NULL, cspi3_clk)
|
|
_REGISTER_CLOCK(NULL, "gpt", gpt_clk)
|
|
_REGISTER_CLOCK(NULL, "pwm", pwm_clk)
|
|
_REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
|
|
_REGISTER_CLOCK(NULL, "rtc", rtc_clk)
|
|
_REGISTER_CLOCK(NULL, "epit", epit1_clk)
|
|
_REGISTER_CLOCK(NULL, "epit", epit2_clk)
|
|
_REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
|
|
_REGISTER_CLOCK("ipu-core", NULL, ipu_clk)
|
|
_REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk)
|
|
_REGISTER_CLOCK(NULL, "kpp", kpp_clk)
|
|
_REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk1)
|
|
_REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk2)
|
|
_REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk1)
|
|
_REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk2)
|
|
_REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk1)
|
|
_REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk2)
|
|
_REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk1)
|
|
_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk2)
|
|
_REGISTER_CLOCK("mx3-camera.0", NULL, csi_clk)
|
|
/* i.mx31 has the i.mx21 type uart */
|
|
_REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
|
|
_REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
|
|
_REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
|
|
_REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk)
|
|
_REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk)
|
|
_REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
|
|
_REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
|
|
_REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk)
|
|
_REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk)
|
|
_REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
|
|
_REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
|
|
_REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
|
|
_REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
|
|
_REGISTER_CLOCK(NULL, "firi", firi_clk)
|
|
_REGISTER_CLOCK(NULL, "ata", ata_clk)
|
|
_REGISTER_CLOCK(NULL, "rtic", rtic_clk)
|
|
_REGISTER_CLOCK(NULL, "rng", rng_clk)
|
|
_REGISTER_CLOCK("imx31-sdma", NULL, sdma_clk1)
|
|
_REGISTER_CLOCK(NULL, "sdma_ipg", sdma_clk2)
|
|
_REGISTER_CLOCK(NULL, "mstick", mstick1_clk)
|
|
_REGISTER_CLOCK(NULL, "mstick", mstick2_clk)
|
|
_REGISTER_CLOCK(NULL, "scc", scc_clk)
|
|
_REGISTER_CLOCK(NULL, "iim", iim_clk)
|
|
_REGISTER_CLOCK(NULL, "mpeg4", mpeg4_clk)
|
|
_REGISTER_CLOCK(NULL, "mbx", mbx_clk)
|
|
};
|
|
|
|
int __init mx31_clocks_init(unsigned long fref)
|
|
{
|
|
u32 reg;
|
|
|
|
ckih_rate = fref;
|
|
|
|
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
|
|
|
/* change the csi_clk parent if necessary */
|
|
reg = __raw_readl(MXC_CCM_CCMR);
|
|
if (!(reg & MXC_CCM_CCMR_CSCS))
|
|
if (clk_set_parent(&csi_clk, &usb_pll_clk))
|
|
pr_err("%s: error changing csi_clk parent\n", __func__);
|
|
|
|
|
|
/* Turn off all possible clocks */
|
|
__raw_writel((3 << 4), MXC_CCM_CGR0);
|
|
__raw_writel(0, MXC_CCM_CGR1);
|
|
__raw_writel((3 << 8) | (3 << 14) | (3 << 16)|
|
|
1 << 27 | 1 << 28, /* Bit 27 and 28 are not defined for
|
|
MX32, but still required to be set */
|
|
MXC_CCM_CGR2);
|
|
|
|
/*
|
|
* Before turning off usb_pll make sure ipg_per_clk is generated
|
|
* by ipg_clk and not usb_pll.
|
|
*/
|
|
__raw_writel(__raw_readl(MXC_CCM_CCMR) | (1 << 24), MXC_CCM_CCMR);
|
|
|
|
usb_pll_disable(&usb_pll_clk);
|
|
|
|
pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk));
|
|
|
|
clk_enable(&gpt_clk);
|
|
clk_enable(&emi_clk);
|
|
clk_enable(&iim_clk);
|
|
|
|
clk_enable(&serial_pll_clk);
|
|
|
|
mx31_read_cpu_rev();
|
|
|
|
if (mx31_revision() >= IMX_CHIP_REVISION_2_0) {
|
|
reg = __raw_readl(MXC_CCM_PMCR1);
|
|
/* No PLL restart on DVFS switch; enable auto EMI handshake */
|
|
reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN;
|
|
__raw_writel(reg, MXC_CCM_PMCR1);
|
|
}
|
|
|
|
mxc_timer_init(&ipg_clk, MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR),
|
|
MX31_INT_GPT);
|
|
|
|
return 0;
|
|
}
|