585 lines
22 KiB
C
585 lines
22 KiB
C
/*
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* Copyright (c) 2011 Broadcom Corporation
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
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* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _BRCM_AIUTILS_H_
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#define _BRCM_AIUTILS_H_
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#include "types.h"
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/*
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* SOC Interconnect Address Map.
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* All regions may not exist on all chips.
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*/
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/* Physical SDRAM */
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#define SI_SDRAM_BASE 0x00000000
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/* Host Mode sb2pcitranslation0 (64 MB) */
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#define SI_PCI_MEM 0x08000000
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#define SI_PCI_MEM_SZ (64 * 1024 * 1024)
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/* Host Mode sb2pcitranslation1 (64 MB) */
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#define SI_PCI_CFG 0x0c000000
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/* Byteswapped Physical SDRAM */
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#define SI_SDRAM_SWAPPED 0x10000000
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/* Region 2 for sdram (512 MB) */
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#define SI_SDRAM_R2 0x80000000
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#ifdef SI_ENUM_BASE_VARIABLE
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#define SI_ENUM_BASE (sii->pub.si_enum_base)
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#else
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#define SI_ENUM_BASE 0x18000000 /* Enumeration space base */
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#endif /* SI_ENUM_BASE_VARIABLE */
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/* Wrapper space base */
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#define SI_WRAP_BASE 0x18100000
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/* each core gets 4Kbytes for registers */
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#define SI_CORE_SIZE 0x1000
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/*
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* Max cores (this is arbitrary, for software
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* convenience and could be changed if we
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* make any larger chips
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*/
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#define SI_MAXCORES 16
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/* On-chip RAM on chips that also have DDR */
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#define SI_FASTRAM 0x19000000
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#define SI_FASTRAM_SWAPPED 0x19800000
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/* Flash Region 2 (region 1 shadowed here) */
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#define SI_FLASH2 0x1c000000
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/* Size of Flash Region 2 */
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#define SI_FLASH2_SZ 0x02000000
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/* ARM Cortex-M3 ROM */
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#define SI_ARMCM3_ROM 0x1e000000
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/* MIPS Flash Region 1 */
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#define SI_FLASH1 0x1fc00000
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/* MIPS Size of Flash Region 1 */
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#define SI_FLASH1_SZ 0x00400000
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/* ARM7TDMI-S ROM */
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#define SI_ARM7S_ROM 0x20000000
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/* ARM Cortex-M3 SRAM Region 2 */
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#define SI_ARMCM3_SRAM2 0x60000000
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/* ARM7TDMI-S SRAM Region 2 */
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#define SI_ARM7S_SRAM2 0x80000000
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/* ARM Flash Region 1 */
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#define SI_ARM_FLASH1 0xffff0000
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/* ARM Size of Flash Region 1 */
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#define SI_ARM_FLASH1_SZ 0x00010000
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/* Client Mode sb2pcitranslation2 (1 GB) */
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#define SI_PCI_DMA 0x40000000
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/* Client Mode sb2pcitranslation2 (1 GB) */
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#define SI_PCI_DMA2 0x80000000
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/* Client Mode sb2pcitranslation2 size in bytes */
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#define SI_PCI_DMA_SZ 0x40000000
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/* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
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#define SI_PCIE_DMA_L32 0x00000000
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/* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
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#define SI_PCIE_DMA_H32 0x80000000
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/* core codes */
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#define NODEV_CORE_ID 0x700 /* Invalid coreid */
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#define CC_CORE_ID 0x800 /* chipcommon core */
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#define ILINE20_CORE_ID 0x801 /* iline20 core */
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#define SRAM_CORE_ID 0x802 /* sram core */
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#define SDRAM_CORE_ID 0x803 /* sdram core */
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#define PCI_CORE_ID 0x804 /* pci core */
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#define MIPS_CORE_ID 0x805 /* mips core */
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#define ENET_CORE_ID 0x806 /* enet mac core */
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#define CODEC_CORE_ID 0x807 /* v90 codec core */
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#define USB_CORE_ID 0x808 /* usb 1.1 host/device core */
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#define ADSL_CORE_ID 0x809 /* ADSL core */
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#define ILINE100_CORE_ID 0x80a /* iline100 core */
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#define IPSEC_CORE_ID 0x80b /* ipsec core */
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#define UTOPIA_CORE_ID 0x80c /* utopia core */
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#define PCMCIA_CORE_ID 0x80d /* pcmcia core */
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#define SOCRAM_CORE_ID 0x80e /* internal memory core */
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#define MEMC_CORE_ID 0x80f /* memc sdram core */
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#define OFDM_CORE_ID 0x810 /* OFDM phy core */
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#define EXTIF_CORE_ID 0x811 /* external interface core */
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#define D11_CORE_ID 0x812 /* 802.11 MAC core */
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#define APHY_CORE_ID 0x813 /* 802.11a phy core */
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#define BPHY_CORE_ID 0x814 /* 802.11b phy core */
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#define GPHY_CORE_ID 0x815 /* 802.11g phy core */
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#define MIPS33_CORE_ID 0x816 /* mips3302 core */
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#define USB11H_CORE_ID 0x817 /* usb 1.1 host core */
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#define USB11D_CORE_ID 0x818 /* usb 1.1 device core */
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#define USB20H_CORE_ID 0x819 /* usb 2.0 host core */
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#define USB20D_CORE_ID 0x81a /* usb 2.0 device core */
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#define SDIOH_CORE_ID 0x81b /* sdio host core */
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#define ROBO_CORE_ID 0x81c /* roboswitch core */
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#define ATA100_CORE_ID 0x81d /* parallel ATA core */
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#define SATAXOR_CORE_ID 0x81e /* serial ATA & XOR DMA core */
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#define GIGETH_CORE_ID 0x81f /* gigabit ethernet core */
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#define PCIE_CORE_ID 0x820 /* pci express core */
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#define NPHY_CORE_ID 0x821 /* 802.11n 2x2 phy core */
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#define SRAMC_CORE_ID 0x822 /* SRAM controller core */
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#define MINIMAC_CORE_ID 0x823 /* MINI MAC/phy core */
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#define ARM11_CORE_ID 0x824 /* ARM 1176 core */
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#define ARM7S_CORE_ID 0x825 /* ARM7tdmi-s core */
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#define LPPHY_CORE_ID 0x826 /* 802.11a/b/g phy core */
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#define PMU_CORE_ID 0x827 /* PMU core */
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#define SSNPHY_CORE_ID 0x828 /* 802.11n single-stream phy core */
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#define SDIOD_CORE_ID 0x829 /* SDIO device core */
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#define ARMCM3_CORE_ID 0x82a /* ARM Cortex M3 core */
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#define HTPHY_CORE_ID 0x82b /* 802.11n 4x4 phy core */
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#define MIPS74K_CORE_ID 0x82c /* mips 74k core */
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#define GMAC_CORE_ID 0x82d /* Gigabit MAC core */
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#define DMEMC_CORE_ID 0x82e /* DDR1/2 memory controller core */
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#define PCIERC_CORE_ID 0x82f /* PCIE Root Complex core */
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#define OCP_CORE_ID 0x830 /* OCP2OCP bridge core */
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#define SC_CORE_ID 0x831 /* shared common core */
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#define AHB_CORE_ID 0x832 /* OCP2AHB bridge core */
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#define SPIH_CORE_ID 0x833 /* SPI host core */
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#define I2S_CORE_ID 0x834 /* I2S core */
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#define DMEMS_CORE_ID 0x835 /* SDR/DDR1 memory controller core */
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#define DEF_SHIM_COMP 0x837 /* SHIM component in ubus/6362 */
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#define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */
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#define DEF_AI_COMP 0xfff /* Default component, in ai chips it
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* maps all unused address ranges
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*/
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/* chipcommon being the first core: */
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#define SI_CC_IDX 0
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/* SOC Interconnect types (aka chip types) */
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#define SOCI_AI 1
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/* Common core control flags */
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#define SICF_BIST_EN 0x8000
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#define SICF_PME_EN 0x4000
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#define SICF_CORE_BITS 0x3ffc
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#define SICF_FGC 0x0002
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#define SICF_CLOCK_EN 0x0001
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/* Common core status flags */
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#define SISF_BIST_DONE 0x8000
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#define SISF_BIST_ERROR 0x4000
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#define SISF_GATED_CLK 0x2000
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#define SISF_DMA64 0x1000
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#define SISF_CORE_BITS 0x0fff
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/* A register that is common to all cores to
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* communicate w/PMU regarding clock control.
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*/
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#define SI_CLK_CTL_ST 0x1e0 /* clock control and status */
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/* clk_ctl_st register */
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#define CCS_FORCEALP 0x00000001 /* force ALP request */
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#define CCS_FORCEHT 0x00000002 /* force HT request */
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#define CCS_FORCEILP 0x00000004 /* force ILP request */
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#define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */
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#define CCS_HTAREQ 0x00000010 /* HT Avail Request */
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#define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */
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#define CCS_ERSRC_REQ_MASK 0x00000700 /* external resource requests */
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#define CCS_ERSRC_REQ_SHIFT 8
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#define CCS_ALPAVAIL 0x00010000 /* ALP is available */
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#define CCS_HTAVAIL 0x00020000 /* HT is available */
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#define CCS_BP_ON_APL 0x00040000 /* RO: running on ALP clock */
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#define CCS_BP_ON_HT 0x00080000 /* RO: running on HT clock */
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#define CCS_ERSRC_STS_MASK 0x07000000 /* external resource status */
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#define CCS_ERSRC_STS_SHIFT 24
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/* HT avail in chipc and pcmcia on 4328a0 */
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#define CCS0_HTAVAIL 0x00010000
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/* ALP avail in chipc and pcmcia on 4328a0 */
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#define CCS0_ALPAVAIL 0x00020000
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/* Not really related to SOC Interconnect, but a couple of software
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* conventions for the use the flash space:
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*/
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/* Minumum amount of flash we support */
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#define FLASH_MIN 0x00020000 /* Minimum flash size */
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/* A boot/binary may have an embedded block that describes its size */
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#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
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#define BISZ_MAGIC 0x4249535a /* Marked with value: 'BISZ' */
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#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
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#define BISZ_TXTST_IDX 1 /* 1: text start */
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#define BISZ_TXTEND_IDX 2 /* 2: text end */
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#define BISZ_DATAST_IDX 3 /* 3: data start */
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#define BISZ_DATAEND_IDX 4 /* 4: data end */
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#define BISZ_BSSST_IDX 5 /* 5: bss start */
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#define BISZ_BSSEND_IDX 6 /* 6: bss end */
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#define BISZ_SIZE 7 /* descriptor size in 32-bit integers */
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#define CC_SROM_OTP 0x800 /* SROM/OTP address space */
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/* gpiotimerval */
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#define GPIO_ONTIME_SHIFT 16
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/* Fields in clkdiv */
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#define CLKD_OTP 0x000f0000
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#define CLKD_OTP_SHIFT 16
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/* When Srom support present, fields in sromcontrol */
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#define SRC_START 0x80000000
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#define SRC_BUSY 0x80000000
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#define SRC_OPCODE 0x60000000
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#define SRC_OP_READ 0x00000000
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#define SRC_OP_WRITE 0x20000000
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#define SRC_OP_WRDIS 0x40000000
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#define SRC_OP_WREN 0x60000000
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#define SRC_OTPSEL 0x00000010
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#define SRC_LOCK 0x00000008
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#define SRC_SIZE_MASK 0x00000006
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#define SRC_SIZE_1K 0x00000000
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#define SRC_SIZE_4K 0x00000002
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#define SRC_SIZE_16K 0x00000004
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#define SRC_SIZE_SHIFT 1
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#define SRC_PRESENT 0x00000001
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/* 4330 chip-specific ChipStatus register bits */
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#define CST4330_CHIPMODE_SDIOD(cs) (((cs) & 0x7) < 6) /* SDIO || gSPI */
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#define CST4330_CHIPMODE_USB20D(cs) (((cs) & 0x7) >= 6) /* USB || USBDA */
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#define CST4330_CHIPMODE_SDIO(cs) (((cs) & 0x4) == 0) /* SDIO */
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#define CST4330_CHIPMODE_GSPI(cs) (((cs) & 0x6) == 4) /* gSPI */
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#define CST4330_CHIPMODE_USB(cs) (((cs) & 0x7) == 6) /* USB packet-oriented */
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#define CST4330_CHIPMODE_USBDA(cs) (((cs) & 0x7) == 7) /* USB Direct Access */
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#define CST4330_OTP_PRESENT 0x00000010
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#define CST4330_LPO_AUTODET_EN 0x00000020
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#define CST4330_ARMREMAP_0 0x00000040
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#define CST4330_SPROM_PRESENT 0x00000080 /* takes priority over OTP if both set */
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#define CST4330_ILPDIV_EN 0x00000100
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#define CST4330_LPO_SEL 0x00000200
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#define CST4330_RES_INIT_MODE_SHIFT 10
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#define CST4330_RES_INIT_MODE_MASK 0x00000c00
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#define CST4330_CBUCK_MODE_SHIFT 12
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#define CST4330_CBUCK_MODE_MASK 0x00003000
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#define CST4330_CBUCK_POWER_OK 0x00004000
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#define CST4330_BB_PLL_LOCKED 0x00008000
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/* Package IDs */
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#define BCM4329_289PIN_PKG_ID 0 /* 4329 289-pin package id */
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#define BCM4329_182PIN_PKG_ID 1 /* 4329N 182-pin package id */
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#define BCM4717_PKG_ID 9 /* 4717 package id */
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#define BCM4718_PKG_ID 10 /* 4718 package id */
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#define HDLSIM_PKG_ID 14 /* HDL simulator package id */
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#define HWSIM_PKG_ID 15 /* Hardware simulator package id */
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#define BCM43224_FAB_SMIC 0xa /* the chip is manufactured by SMIC */
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/* these are router chips */
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#define BCM4716_CHIP_ID 0x4716 /* 4716 chipcommon chipid */
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#define BCM47162_CHIP_ID 47162 /* 47162 chipcommon chipid */
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#define BCM4748_CHIP_ID 0x4748 /* 4716 chipcommon chipid (OTP, RBBU) */
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#define BCM5356_CHIP_ID 0x5356 /* 5356 chipcommon chipid */
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#define BCM5357_CHIP_ID 0x5357 /* 5357 chipcommon chipid */
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#define SI_INFO(sih) ((struct si_info *)sih)
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#define GOODCOREADDR(x, b) \
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(((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
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IS_ALIGNED((x), SI_CORE_SIZE))
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#define GOODREGS(regs) \
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((regs) != NULL && IS_ALIGNED((unsigned long)(regs), SI_CORE_SIZE))
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#define BADCOREADDR 0
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#define GOODIDX(idx) (((uint)idx) < SI_MAXCORES)
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#define NOREV -1 /* Invalid rev */
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/* Newer chips can access PCI/PCIE and CC core without requiring to change
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* PCI BAR0 WIN
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*/
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#define SI_FAST(si) (((si)->pub.buscoretype == PCIE_CORE_ID) || \
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(((si)->pub.buscoretype == PCI_CORE_ID) && \
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(si)->pub.buscorerev >= 13))
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#define PCIEREGS(si) (((char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET))
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#define CCREGS_FAST(si) (((char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET))
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/*
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* Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts
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* before after core switching to avoid invalid register accesss inside ISR.
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*/
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#define INTR_OFF(si, intr_val) \
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if ((si)->intrsoff_fn && \
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(si)->coreid[(si)->curidx] == (si)->dev_coreid) \
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intr_val = (*(si)->intrsoff_fn)((si)->intr_arg)
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#define INTR_RESTORE(si, intr_val) \
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if ((si)->intrsrestore_fn && \
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(si)->coreid[(si)->curidx] == (si)->dev_coreid) \
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(*(si)->intrsrestore_fn)((si)->intr_arg, intr_val)
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/* dynamic clock control defines */
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#define LPOMINFREQ 25000 /* low power oscillator min */
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#define LPOMAXFREQ 43000 /* low power oscillator max */
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#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
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#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
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#define PCIMINFREQ 25000000 /* 25 MHz */
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#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
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#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
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#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
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#define PCI(si) (((si)->pub.bustype == PCI_BUS) && \
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((si)->pub.buscoretype == PCI_CORE_ID))
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#define PCIE(si) (((si)->pub.bustype == PCI_BUS) && \
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((si)->pub.buscoretype == PCIE_CORE_ID))
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#define PCI_FORCEHT(si) \
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(PCIE(si) && (si->pub.chip == BCM4716_CHIP_ID))
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/* GPIO Based LED powersave defines */
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#define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */
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#define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */
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#ifndef DEFAULT_GPIOTIMERVAL
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#define DEFAULT_GPIOTIMERVAL \
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((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
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#endif
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/*
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* Data structure to export all chip specific common variables
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* public (read-only) portion of aiutils handle returned by si_attach()
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*/
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struct si_pub {
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uint bustype; /* SI_BUS, PCI_BUS */
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uint buscoretype; /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
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uint buscorerev; /* buscore rev */
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uint buscoreidx; /* buscore index */
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int ccrev; /* chip common core rev */
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u32 cccaps; /* chip common capabilities */
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u32 cccaps_ext; /* chip common capabilities extension */
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int pmurev; /* pmu core rev */
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u32 pmucaps; /* pmu capabilities */
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uint boardtype; /* board type */
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uint boardvendor; /* board vendor */
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uint boardflags; /* board flags */
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uint boardflags2; /* board flags2 */
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uint chip; /* chip number */
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uint chiprev; /* chip revision */
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uint chippkg; /* chip package option */
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u32 chipst; /* chip status */
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bool issim; /* chip is in simulation or emulation */
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uint socirev; /* SOC interconnect rev */
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bool pci_pr32414;
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};
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/*
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* Many of the routines below take an 'sih' handle as their first arg.
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* Allocate this by calling si_attach(). Free it by calling si_detach().
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* At any one time, the sih is logically focused on one particular si core
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* (the "current core").
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* Use si_setcore() or si_setcoreidx() to change the association to another core
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*/
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#define BADIDX (SI_MAXCORES + 1)
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/* clkctl xtal what flags */
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#define XTAL 0x1 /* primary crystal oscillator (2050) */
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#define PLL 0x2 /* main chip pll */
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/* clkctl clk mode */
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#define CLK_FAST 0 /* force fast (pll) clock */
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#define CLK_DYNAMIC 2 /* enable dynamic clock control */
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/* GPIO usage priorities */
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#define GPIO_DRV_PRIORITY 0 /* Driver */
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#define GPIO_APP_PRIORITY 1 /* Application */
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#define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO
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* reservation
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*/
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/* GPIO pull up/down */
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#define GPIO_PULLUP 0
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#define GPIO_PULLDN 1
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/* GPIO event regtype */
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#define GPIO_REGEVT 0 /* GPIO register event */
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#define GPIO_REGEVT_INTMSK 1 /* GPIO register event int mask */
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#define GPIO_REGEVT_INTPOL 2 /* GPIO register event int polarity */
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/* device path */
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#define SI_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
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/* SI routine enumeration: to be used by update function with multiple hooks */
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#define SI_DOATTACH 1
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#define SI_PCIDOWN 2
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#define SI_PCIUP 3
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/* PMU clock/power control */
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#if defined(BCMPMUCTL)
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#define PMUCTL_ENAB(sih) (BCMPMUCTL)
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#else
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#define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU)
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#endif
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/* chipcommon clock/power control (exclusive with PMU's) */
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#if defined(BCMPMUCTL) && BCMPMUCTL
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#define CCCTL_ENAB(sih) (0)
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#define CCPLL_ENAB(sih) (0)
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#else
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#define CCCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PWR_CTL)
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#define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK)
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#endif
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typedef void (*gpio_handler_t) (u32 stat, void *arg);
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/* External PA enable mask */
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#define GPIO_CTRL_EPA_EN_MASK 0x40
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#define SI_ERROR(args)
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#ifdef BCMDBG
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#define SI_MSG(args) printk args
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#else
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#define SI_MSG(args)
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#endif /* BCMDBG */
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/* Define SI_VMSG to printf for verbose debugging, but don't check it in */
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#define SI_VMSG(args)
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#define IS_SIM(chippkg) \
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((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
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typedef u32(*si_intrsoff_t) (void *intr_arg);
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typedef void (*si_intrsrestore_t) (void *intr_arg, u32 arg);
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typedef bool(*si_intrsenabled_t) (void *intr_arg);
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struct gpioh_item {
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void *arg;
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bool level;
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gpio_handler_t handler;
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u32 event;
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struct gpioh_item *next;
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};
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/* misc si info needed by some of the routines */
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struct si_info {
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struct si_pub pub; /* back plane public state (must be first) */
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void *pbus; /* handle to bus (pci/sdio/..) */
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uint dev_coreid; /* the core provides driver functions */
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void *intr_arg; /* interrupt callback function arg */
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si_intrsoff_t intrsoff_fn; /* turns chip interrupts off */
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si_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */
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si_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */
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void *pch; /* PCI/E core handle */
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|
|
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char *vars;
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uint varsz;
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|
|
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void *curmap; /* current regs va */
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void *regs[SI_MAXCORES]; /* other regs va */
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|
|
|
uint curidx; /* current core index */
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|
uint numcores; /* # discovered cores */
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|
uint coreid[SI_MAXCORES]; /* id of each core */
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|
u32 coresba[SI_MAXCORES]; /* backplane address of each core */
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|
void *regs2[SI_MAXCORES]; /* 2nd virtual address per core (usbh20) */
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|
u32 coresba2[SI_MAXCORES]; /* 2nd phys address per core (usbh20) */
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|
u32 coresba_size[SI_MAXCORES]; /* backplane address space size */
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|
u32 coresba2_size[SI_MAXCORES]; /* second address space size */
|
|
|
|
void *curwrap; /* current wrapper va */
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|
void *wrappers[SI_MAXCORES]; /* other cores wrapper va */
|
|
u32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */
|
|
|
|
u32 cia[SI_MAXCORES]; /* erom cia entry for each core */
|
|
u32 cib[SI_MAXCORES]; /* erom cia entry for each core */
|
|
u32 oob_router; /* oob router registers for axi */
|
|
};
|
|
|
|
/* AMBA Interconnect exported externs */
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|
extern void ai_scan(struct si_pub *sih, void *regs);
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|
|
|
extern uint ai_flag(struct si_pub *sih);
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|
extern void ai_setint(struct si_pub *sih, int siflag);
|
|
extern uint ai_coreidx(struct si_pub *sih);
|
|
extern uint ai_corevendor(struct si_pub *sih);
|
|
extern uint ai_corerev(struct si_pub *sih);
|
|
extern bool ai_iscoreup(struct si_pub *sih);
|
|
extern void *ai_setcoreidx(struct si_pub *sih, uint coreidx);
|
|
extern u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val);
|
|
extern void ai_core_cflags_wo(struct si_pub *sih, u32 mask, u32 val);
|
|
extern u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val);
|
|
extern uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask,
|
|
uint val);
|
|
extern void ai_core_reset(struct si_pub *sih, u32 bits, u32 resetbits);
|
|
extern void ai_core_disable(struct si_pub *sih, u32 bits);
|
|
extern int ai_numaddrspaces(struct si_pub *sih);
|
|
extern u32 ai_addrspace(struct si_pub *sih, uint asidx);
|
|
extern u32 ai_addrspacesize(struct si_pub *sih, uint asidx);
|
|
extern void ai_write_wrap_reg(struct si_pub *sih, u32 offset, u32 val);
|
|
|
|
/* === exported functions === */
|
|
extern struct si_pub *ai_attach(void *regs, uint bustype,
|
|
void *sdh, char **vars, uint *varsz);
|
|
|
|
extern void ai_detach(struct si_pub *sih);
|
|
extern bool ai_pci_war16165(struct si_pub *sih);
|
|
|
|
extern uint ai_coreid(struct si_pub *sih);
|
|
extern uint ai_corerev(struct si_pub *sih);
|
|
extern uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask,
|
|
uint val);
|
|
extern void ai_write_wrapperreg(struct si_pub *sih, u32 offset, u32 val);
|
|
extern u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val);
|
|
extern u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val);
|
|
extern bool ai_iscoreup(struct si_pub *sih);
|
|
extern uint ai_findcoreidx(struct si_pub *sih, uint coreid, uint coreunit);
|
|
extern void *ai_setcoreidx(struct si_pub *sih, uint coreidx);
|
|
extern void *ai_setcore(struct si_pub *sih, uint coreid, uint coreunit);
|
|
extern void *ai_switch_core(struct si_pub *sih, uint coreid, uint *origidx,
|
|
uint *intr_val);
|
|
extern void ai_restore_core(struct si_pub *sih, uint coreid, uint intr_val);
|
|
extern void ai_core_reset(struct si_pub *sih, u32 bits, u32 resetbits);
|
|
extern void ai_core_disable(struct si_pub *sih, u32 bits);
|
|
extern u32 ai_alp_clock(struct si_pub *sih);
|
|
extern u32 ai_ilp_clock(struct si_pub *sih);
|
|
extern void ai_pci_setup(struct si_pub *sih, uint coremask);
|
|
extern void ai_setint(struct si_pub *sih, int siflag);
|
|
extern bool ai_backplane64(struct si_pub *sih);
|
|
extern void ai_register_intr_callback(struct si_pub *sih, void *intrsoff_fn,
|
|
void *intrsrestore_fn,
|
|
void *intrsenabled_fn, void *intr_arg);
|
|
extern void ai_deregister_intr_callback(struct si_pub *sih);
|
|
extern void ai_clkctl_init(struct si_pub *sih);
|
|
extern u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih);
|
|
extern bool ai_clkctl_cc(struct si_pub *sih, uint mode);
|
|
extern int ai_clkctl_xtal(struct si_pub *sih, uint what, bool on);
|
|
extern bool ai_deviceremoved(struct si_pub *sih);
|
|
extern u32 ai_gpiocontrol(struct si_pub *sih, u32 mask, u32 val,
|
|
u8 priority);
|
|
|
|
/* OTP status */
|
|
extern bool ai_is_otp_disabled(struct si_pub *sih);
|
|
|
|
/* SPROM availability */
|
|
extern bool ai_is_sprom_available(struct si_pub *sih);
|
|
|
|
/*
|
|
* Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
|
|
* The returned path is NULL terminated and has trailing '/'.
|
|
* Return 0 on success, nonzero otherwise.
|
|
*/
|
|
extern int ai_devpath(struct si_pub *sih, char *path, int size);
|
|
/* Read variable with prepending the devpath to the name */
|
|
extern char *ai_getdevpathvar(struct si_pub *sih, const char *name);
|
|
extern int ai_getdevpathintvar(struct si_pub *sih, const char *name);
|
|
|
|
extern void ai_pci_sleep(struct si_pub *sih);
|
|
extern void ai_pci_down(struct si_pub *sih);
|
|
extern void ai_pci_up(struct si_pub *sih);
|
|
extern int ai_pci_fixcfg(struct si_pub *sih);
|
|
|
|
extern void ai_chipcontrl_epa4331(struct si_pub *sih, bool on);
|
|
/* Enable Ex-PA for 4313 */
|
|
extern void ai_epa_4313war(struct si_pub *sih);
|
|
|
|
char *ai_getnvramflvar(struct si_pub *sih, const char *name);
|
|
|
|
#endif /* _BRCM_AIUTILS_H_ */
|