![Kuninori Morimoto](/assets/img/avatar_default.png)
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
369 lines
12 KiB
C
369 lines
12 KiB
C
/*
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* arch/sh/kernel/cpu/sh4a/clock-sh7724.c
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*
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* SH7724 clock framework support
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*
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* Copyright (C) 2009 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <asm/clock.h>
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#include <asm/hwblk.h>
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#include <cpu/sh7724.h>
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/* SH7724 registers */
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#define FRQCRA 0xa4150000
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#define FRQCRB 0xa4150004
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#define VCLKCR 0xa4150048
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#define FCLKACR 0xa4150008
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#define FCLKBCR 0xa415000c
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#define IRDACLKCR 0xa4150018
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#define PLLCR 0xa4150024
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#define SPUCLKCR 0xa415003c
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#define FLLFRQ 0xa4150050
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#define LSTATS 0xa4150060
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/* Fixed 32 KHz root clock for RTC and Power Management purposes */
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static struct clk r_clk = {
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.rate = 32768,
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};
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/*
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* Default rate for the root input clock, reset this with clk_set_rate()
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* from the platform code.
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*/
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static struct clk extal_clk = {
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.rate = 33333333,
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};
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/* The fll multiplies the 32khz r_clk, may be used instead of extal */
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static unsigned long fll_recalc(struct clk *clk)
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{
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unsigned long mult = 0;
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unsigned long div = 1;
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if (__raw_readl(PLLCR) & 0x1000)
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mult = __raw_readl(FLLFRQ) & 0x3ff;
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if (__raw_readl(FLLFRQ) & 0x4000)
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div = 2;
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return (clk->parent->rate * mult) / div;
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}
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static struct clk_ops fll_clk_ops = {
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.recalc = fll_recalc,
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};
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static struct clk fll_clk = {
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.ops = &fll_clk_ops,
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.parent = &r_clk,
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.flags = CLK_ENABLE_ON_INIT,
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};
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static unsigned long pll_recalc(struct clk *clk)
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{
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unsigned long mult = 1;
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if (__raw_readl(PLLCR) & 0x4000)
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mult = (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1) * 2;
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return clk->parent->rate * mult;
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}
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static struct clk_ops pll_clk_ops = {
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.recalc = pll_recalc,
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};
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static struct clk pll_clk = {
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.ops = &pll_clk_ops,
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.flags = CLK_ENABLE_ON_INIT,
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};
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/* A fixed divide-by-3 block use by the div6 clocks */
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static unsigned long div3_recalc(struct clk *clk)
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{
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return clk->parent->rate / 3;
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}
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static struct clk_ops div3_clk_ops = {
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.recalc = div3_recalc,
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};
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static struct clk div3_clk = {
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.ops = &div3_clk_ops,
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.parent = &pll_clk,
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};
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/* External input clock (pin name: FSIMCKA/FSIMCKB ) */
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struct clk sh7724_fsimcka_clk = {
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};
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struct clk sh7724_fsimckb_clk = {
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};
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static struct clk *main_clks[] = {
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&r_clk,
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&extal_clk,
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&fll_clk,
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&pll_clk,
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&div3_clk,
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&sh7724_fsimcka_clk,
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&sh7724_fsimckb_clk,
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};
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static void div4_kick(struct clk *clk)
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{
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unsigned long value;
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/* set KICK bit in FRQCRA to update hardware setting */
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value = __raw_readl(FRQCRA);
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value |= (1 << 31);
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__raw_writel(value, FRQCRA);
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}
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static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 };
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static struct clk_div_mult_table div4_div_mult_table = {
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.divisors = divisors,
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.nr_divisors = ARRAY_SIZE(divisors),
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};
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static struct clk_div4_table div4_table = {
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.div_mult_table = &div4_div_mult_table,
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.kick = div4_kick,
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};
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enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR };
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#define DIV4(_reg, _bit, _mask, _flags) \
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SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
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struct clk div4_clks[DIV4_NR] = {
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[DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
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[DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
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[DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
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[DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0),
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[DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
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};
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enum { DIV6_V, DIV6_I, DIV6_S, DIV6_NR };
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static struct clk div6_clks[DIV6_NR] = {
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[DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0),
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[DIV6_I] = SH_CLK_DIV6(&div3_clk, IRDACLKCR, 0),
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[DIV6_S] = SH_CLK_DIV6(&div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT),
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};
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enum { DIV6_FA, DIV6_FB, DIV6_REPARENT_NR };
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/* Indices are important - they are the actual src selecting values */
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static struct clk *fclkacr_parent[] = {
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[0] = &div3_clk,
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[1] = NULL,
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[2] = &sh7724_fsimcka_clk,
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[3] = NULL,
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};
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static struct clk *fclkbcr_parent[] = {
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[0] = &div3_clk,
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[1] = NULL,
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[2] = &sh7724_fsimckb_clk,
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[3] = NULL,
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};
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static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
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[DIV6_FA] = SH_CLK_DIV6_EXT(&div3_clk, FCLKACR, 0,
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fclkacr_parent, ARRAY_SIZE(fclkacr_parent), 6, 2),
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[DIV6_FB] = SH_CLK_DIV6_EXT(&div3_clk, FCLKBCR, 0,
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fclkbcr_parent, ARRAY_SIZE(fclkbcr_parent), 6, 2),
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};
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static struct clk mstp_clks[HWBLK_NR] = {
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SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
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SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
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SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
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SH_HWBLK_CLK(HWBLK_RSMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
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SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
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SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
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SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
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SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_P], CLK_ENABLE_ON_INIT),
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SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
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SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0),
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SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0),
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SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0),
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SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
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SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
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SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0),
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SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
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SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
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SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
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SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
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SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
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SH_HWBLK_CLK(HWBLK_IIC0, &div4_clks[DIV4_P], 0),
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SH_HWBLK_CLK(HWBLK_IIC1, &div4_clks[DIV4_P], 0),
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SH_HWBLK_CLK(HWBLK_MMC, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_ETHER, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0),
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SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_USB1, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_USB0, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_VEU1, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_CEU1, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_BEU1, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_2DDMAC, &div4_clks[DIV4_SH], 0),
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SH_HWBLK_CLK(HWBLK_SPU, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_BEU0, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_CEU0, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_VEU0, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
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SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0),
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};
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static struct clk_lookup lookups[] = {
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/* main clocks */
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CLKDEV_CON_ID("rclk", &r_clk),
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CLKDEV_CON_ID("extal", &extal_clk),
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CLKDEV_CON_ID("fll_clk", &fll_clk),
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CLKDEV_CON_ID("pll_clk", &pll_clk),
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CLKDEV_CON_ID("div3_clk", &div3_clk),
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/* DIV4 clocks */
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CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
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CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
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CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
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CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
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CLKDEV_CON_ID("vpu_clk", &div4_clks[DIV4_M1]),
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/* DIV6 clocks */
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CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
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CLKDEV_CON_ID("fsia_clk", &div6_reparent_clks[DIV6_FA]),
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CLKDEV_CON_ID("fsib_clk", &div6_reparent_clks[DIV6_FB]),
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CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]),
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CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]),
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/* MSTP clocks */
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CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]),
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CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]),
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CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]),
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CLKDEV_CON_ID("rs0", &mstp_clks[HWBLK_RSMEM]),
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CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
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CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
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CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
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CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
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CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]),
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CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
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CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
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CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
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CLKDEV_ICK_ID("tmu_fck", "sh_tmu.0", &mstp_clks[HWBLK_TMU0]),
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CLKDEV_ICK_ID("tmu_fck", "sh_tmu.1", &mstp_clks[HWBLK_TMU0]),
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CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[HWBLK_TMU0]),
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CLKDEV_ICK_ID("tmu_fck", "sh_tmu.3", &mstp_clks[HWBLK_TMU1]),
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CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
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CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
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CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]),
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CLKDEV_ICK_ID("tmu_fck", "sh_tmu.4", &mstp_clks[HWBLK_TMU1]),
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CLKDEV_ICK_ID("tmu_fck", "sh_tmu.5", &mstp_clks[HWBLK_TMU1]),
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CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[HWBLK_SCIF0]),
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CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[HWBLK_SCIF1]),
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CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[HWBLK_SCIF2]),
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CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[HWBLK_SCIF3]),
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CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[HWBLK_SCIF4]),
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CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[HWBLK_SCIF5]),
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CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]),
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CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]),
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CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
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CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
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CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC0]),
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CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[HWBLK_IIC1]),
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CLKDEV_CON_ID("mmc0", &mstp_clks[HWBLK_MMC]),
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CLKDEV_CON_ID("eth0", &mstp_clks[HWBLK_ETHER]),
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CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
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CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]),
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CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
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CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]),
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CLKDEV_CON_ID("usb1", &mstp_clks[HWBLK_USB1]),
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CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB0]),
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CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
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CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]),
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CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]),
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CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU1]),
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CLKDEV_CON_ID("ceu1", &mstp_clks[HWBLK_CEU1]),
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CLKDEV_CON_ID("beu1", &mstp_clks[HWBLK_BEU1]),
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CLKDEV_CON_ID("2ddmac0", &mstp_clks[HWBLK_2DDMAC]),
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CLKDEV_CON_ID("spu0", &mstp_clks[HWBLK_SPU]),
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CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
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CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
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CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU0]),
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CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU0]),
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CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU0]),
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CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
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CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
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};
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int __init arch_clk_init(void)
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{
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int k, ret = 0;
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/* autodetect extal or fll configuration */
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if (__raw_readl(PLLCR) & 0x1000)
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pll_clk.parent = &fll_clk;
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else
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pll_clk.parent = &extal_clk;
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for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
|
|
ret = clk_register(main_clks[k]);
|
|
|
|
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
|
|
|
if (!ret)
|
|
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
|
|
|
|
if (!ret)
|
|
ret = sh_clk_div6_register(div6_clks, DIV6_NR);
|
|
|
|
if (!ret)
|
|
ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR);
|
|
|
|
if (!ret)
|
|
ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
|
|
|
|
return ret;
|
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}
|