52393ccc0a
set_wmb should not be used in the kernel because it just confuses the
code more and has no benefit. Since it is not currently used in the
kernel this patch removes it so that new code does not include it.
All archs define set_wmb(var, value) to do { var = value; wmb(); }
while(0) except ia64 and sparc which use a mb() instead. But this is
still moot since it is not used anyway.
Hasn't been tested on any archs but x86 and x86_64 (and only compiled
tested)
Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
195 lines
5.5 KiB
C
195 lines
5.5 KiB
C
#ifndef __PARISC_SYSTEM_H
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#define __PARISC_SYSTEM_H
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#include <asm/psw.h>
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/* The program status word as bitfields. */
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struct pa_psw {
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unsigned int y:1;
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unsigned int z:1;
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unsigned int rv:2;
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unsigned int w:1;
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unsigned int e:1;
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unsigned int s:1;
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unsigned int t:1;
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unsigned int h:1;
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unsigned int l:1;
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unsigned int n:1;
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unsigned int x:1;
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unsigned int b:1;
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unsigned int c:1;
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unsigned int v:1;
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unsigned int m:1;
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unsigned int cb:8;
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unsigned int o:1;
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unsigned int g:1;
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unsigned int f:1;
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unsigned int r:1;
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unsigned int q:1;
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unsigned int p:1;
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unsigned int d:1;
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unsigned int i:1;
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};
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#ifdef __LP64__
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#define pa_psw(task) ((struct pa_psw *) ((char *) (task) + TASK_PT_PSW + 4))
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#else
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#define pa_psw(task) ((struct pa_psw *) ((char *) (task) + TASK_PT_PSW))
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#endif
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struct task_struct;
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extern struct task_struct *_switch_to(struct task_struct *, struct task_struct *);
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#define switch_to(prev, next, last) do { \
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(last) = _switch_to(prev, next); \
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} while(0)
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/*
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* On SMP systems, when the scheduler does migration-cost autodetection,
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* it needs a way to flush as much of the CPU's caches as possible.
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*
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* TODO: fill this in!
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*/
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static inline void sched_cacheflush(void)
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{
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}
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/* interrupt control */
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#define local_save_flags(x) __asm__ __volatile__("ssm 0, %0" : "=r" (x) : : "memory")
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#define local_irq_disable() __asm__ __volatile__("rsm %0,%%r0\n" : : "i" (PSW_I) : "memory" )
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#define local_irq_enable() __asm__ __volatile__("ssm %0,%%r0\n" : : "i" (PSW_I) : "memory" )
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#define local_irq_save(x) \
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__asm__ __volatile__("rsm %1,%0" : "=r" (x) :"i" (PSW_I) : "memory" )
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#define local_irq_restore(x) \
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__asm__ __volatile__("mtsm %0" : : "r" (x) : "memory" )
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#define irqs_disabled() \
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({ \
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unsigned long flags; \
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local_save_flags(flags); \
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(flags & PSW_I) == 0; \
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})
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#define mfctl(reg) ({ \
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unsigned long cr; \
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__asm__ __volatile__( \
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"mfctl " #reg ",%0" : \
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"=r" (cr) \
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); \
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cr; \
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})
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#define mtctl(gr, cr) \
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__asm__ __volatile__("mtctl %0,%1" \
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: /* no outputs */ \
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: "r" (gr), "i" (cr) : "memory")
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/* these are here to de-mystefy the calling code, and to provide hooks */
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/* which I needed for debugging EIEM problems -PB */
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#define get_eiem() mfctl(15)
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static inline void set_eiem(unsigned long val)
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{
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mtctl(val, 15);
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}
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#define mfsp(reg) ({ \
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unsigned long cr; \
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__asm__ __volatile__( \
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"mfsp " #reg ",%0" : \
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"=r" (cr) \
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); \
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cr; \
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})
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#define mtsp(gr, cr) \
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__asm__ __volatile__("mtsp %0,%1" \
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: /* no outputs */ \
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: "r" (gr), "i" (cr) : "memory")
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/*
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** This is simply the barrier() macro from linux/kernel.h but when serial.c
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** uses tqueue.h uses smp_mb() defined using barrier(), linux/kernel.h
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** hasn't yet been included yet so it fails, thus repeating the macro here.
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**
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** PA-RISC architecture allows for weakly ordered memory accesses although
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** none of the processors use it. There is a strong ordered bit that is
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** set in the O-bit of the page directory entry. Operating systems that
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** can not tolerate out of order accesses should set this bit when mapping
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** pages. The O-bit of the PSW should also be set to 1 (I don't believe any
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** of the processor implemented the PSW O-bit). The PCX-W ERS states that
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** the TLB O-bit is not implemented so the page directory does not need to
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** have the O-bit set when mapping pages (section 3.1). This section also
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** states that the PSW Y, Z, G, and O bits are not implemented.
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** So it looks like nothing needs to be done for parisc-linux (yet).
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** (thanks to chada for the above comment -ggg)
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**
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** The __asm__ op below simple prevents gcc/ld from reordering
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** instructions across the mb() "call".
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*/
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#define mb() __asm__ __volatile__("":::"memory") /* barrier() */
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#define rmb() mb()
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#define wmb() mb()
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#define smp_mb() mb()
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#define smp_rmb() mb()
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#define smp_wmb() mb()
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#define smp_read_barrier_depends() do { } while(0)
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#define read_barrier_depends() do { } while(0)
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#define set_mb(var, value) do { var = value; mb(); } while (0)
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#ifndef CONFIG_PA20
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/* Because kmalloc only guarantees 8-byte alignment for kmalloc'd data,
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and GCC only guarantees 8-byte alignment for stack locals, we can't
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be assured of 16-byte alignment for atomic lock data even if we
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specify "__attribute ((aligned(16)))" in the type declaration. So,
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we use a struct containing an array of four ints for the atomic lock
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type and dynamically select the 16-byte aligned int from the array
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for the semaphore. */
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#define __PA_LDCW_ALIGNMENT 16
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#define __ldcw_align(a) ({ \
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unsigned long __ret = (unsigned long) &(a)->lock[0]; \
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__ret = (__ret + __PA_LDCW_ALIGNMENT - 1) \
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& ~(__PA_LDCW_ALIGNMENT - 1); \
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(volatile unsigned int *) __ret; \
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})
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#define __LDCW "ldcw"
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#else /*CONFIG_PA20*/
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/* From: "Jim Hull" <jim.hull of hp.com>
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I've attached a summary of the change, but basically, for PA 2.0, as
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long as the ",CO" (coherent operation) completer is specified, then the
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16-byte alignment requirement for ldcw and ldcd is relaxed, and instead
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they only require "natural" alignment (4-byte for ldcw, 8-byte for
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ldcd). */
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#define __PA_LDCW_ALIGNMENT 4
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#define __ldcw_align(a) ((volatile unsigned int *)a)
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#define __LDCW "ldcw,co"
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#endif /*!CONFIG_PA20*/
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/* LDCW, the only atomic read-write operation PA-RISC has. *sigh*. */
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#define __ldcw(a) ({ \
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unsigned __ret; \
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__asm__ __volatile__(__LDCW " 0(%1),%0" \
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: "=r" (__ret) : "r" (a)); \
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__ret; \
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})
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#ifdef CONFIG_SMP
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# define __lock_aligned __attribute__((__section__(".data.lock_aligned")))
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#endif
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#define KERNEL_START (0x10100000 - 0x1000)
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#define arch_align_stack(x) (x)
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#endif
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