![Tzachi Perelstein](/assets/img/avatar_default.png)
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces, and, depending on the specific model, PCI-E interface, PCI-X interface, SATA controllers, crypto unit, SPI interface, SDIO interface, device bus, NAND controller, DMA engine and/or XOR engine. This contains the basic structure and architecture register definitions. Signed-off-by: Tzachi Perelstein <tzachi@marvell.com> Reviewed-by: Nicolas Pitre <nico@marvell.com> Reviewed-by: Lennert Buytenhek <buytenh@marvell.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
16 lines
267 B
C
16 lines
267 B
C
/*
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* include/asm-arm/arch-orion/memory.h
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*
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* Marvell Orion memory definitions
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*/
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#ifndef __ASM_ARCH_MMU_H
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#define __ASM_ARCH_MMU_H
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#define PHYS_OFFSET UL(0x00000000)
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#define __virt_to_bus(x) __virt_to_phys(x)
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#define __bus_to_virt(x) __phys_to_virt(x)
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#endif
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