![Florian Schilhabel](/assets/img/avatar_default.png)
Because the Firmware is loaded from RTL8192SU/rtl8192sfw.bin, it it save, to remove it from r8192SU_HWImg.c Signed-off-by: Florian Schilhabel <florian.c.schilhabel@googlemail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
201 lines
5.9 KiB
C
201 lines
5.9 KiB
C
#ifndef __INC_FIRMWARE_H
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#define __INC_FIRMWARE_H
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//#define RTL8190_CPU_START_OFFSET 0x80
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/* TODO: this definition is TBD */
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//#define USB_HWDESC_HEADER_LEN 0
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/* It should be double word alignment */
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//#if DEV_BUS_TYPE==PCI_INTERFACE
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//#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) 4*(v/4) - 8
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//#else
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//#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) (4*(v/4) - 8 - USB_HWDESC_HEADER_LEN)
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//#endif
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//typedef enum _firmware_init_step{
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// FW_INIT_STEP0_BOOT = 0,
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// FW_INIT_STEP1_MAIN = 1,
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// FW_INIT_STEP2_DATA = 2,
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//}firmware_init_step_e;
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//typedef enum _DESC_PACKET_TYPE{
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// DESC_PACKET_TYPE_INIT = 0,
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// DESC_PACKET_TYPE_NORMAL = 1,
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//}DESC_PACKET_TYPE;
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#define RTL8192S_FW_PKT_FRAG_SIZE 0xFF00 // 64K
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#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k
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#define MAX_FIRMWARE_CODE_SIZE 0xFF00 // Firmware Local buffer size.
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#define RTL8190_CPU_START_OFFSET 0x80
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#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) (4*(v/4) - 8 - USB_HWDESC_HEADER_LEN)
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//typedef enum _DESC_PACKET_TYPE{
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// DESC_PACKET_TYPE_INIT = 0,
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// DESC_PACKET_TYPE_NORMAL = 1,
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//}DESC_PACKET_TYPE;
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// Forward declaration.
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//typedef struct _ADAPTER ADAPTER, *PADAPTER;
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#ifdef RTL8192S
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typedef enum _firmware_init_step{
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FW_INIT_STEP0_IMEM = 0,
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FW_INIT_STEP1_MAIN = 1,
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FW_INIT_STEP2_DATA = 2,
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}firmware_init_step_e;
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#else
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typedef enum _firmware_init_step{
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FW_INIT_STEP0_BOOT = 0,
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FW_INIT_STEP1_MAIN = 1,
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FW_INIT_STEP2_DATA = 2,
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}firmware_init_step_e;
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#endif
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/* due to rtl8192 firmware */
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typedef enum _desc_packet_type_e{
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DESC_PACKET_TYPE_INIT = 0,
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DESC_PACKET_TYPE_NORMAL = 1,
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}desc_packet_type_e;
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typedef enum _opt_rst_type{
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OPT_SYSTEM_RESET = 0,
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OPT_FIRMWARE_RESET = 1,
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}opt_rst_type_e;
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/*typedef enum _FIRMWARE_STATUS{
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FW_STATUS_0_INIT = 0,
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FW_STATUS_1_MOVE_BOOT_CODE = 1,
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FW_STATUS_2_MOVE_MAIN_CODE = 2,
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FW_STATUS_3_TURNON_CPU = 3,
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FW_STATUS_4_MOVE_DATA_CODE = 4,
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FW_STATUS_5_READY = 5,
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}FIRMWARE_STATUS;
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*/
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//--------------------------------------------------------------------------------
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// RTL8192S Firmware related, Revised by Roger, 2008.12.18.
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//--------------------------------------------------------------------------------
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typedef struct _RT_8192S_FIRMWARE_PRIV { //8-bytes alignment required
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//--- long word 0 ----
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u8 signature_0; //0x12: CE product, 0x92: IT product
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u8 signature_1; //0x87: CE product, 0x81: IT product
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u8 hci_sel; //0x81: PCI-AP, 01:PCIe, 02: 92S-U, 0x82: USB-AP, 0x12: 72S-U, 03:SDIO
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u8 chip_version; //the same value as reigster value
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u8 customer_ID_0; //customer ID low byte
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u8 customer_ID_1; //customer ID high byte
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u8 rf_config; //0x11: 1T1R, 0x12: 1T2R, 0x92: 1T2R turbo, 0x22: 2T2R
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u8 usb_ep_num; // 4: 4EP, 6: 6EP, 11: 11EP
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//--- long word 1 ----
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u8 regulatory_class_0; //regulatory class bit map 0
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u8 regulatory_class_1; //regulatory class bit map 1
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u8 regulatory_class_2; //regulatory class bit map 2
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u8 regulatory_class_3; //regulatory class bit map 3
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u8 rfintfs; // 0:SWSI, 1:HWSI, 2:HWPI
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u8 def_nettype;
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u8 rsvd010;
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u8 rsvd011;
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//--- long word 2 ----
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u8 lbk_mode; //0x00: normal, 0x03: MACLBK, 0x01: PHYLBK
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u8 mp_mode; // 1: for MP use, 0: for normal driver (to be discussed)
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u8 rsvd020;
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u8 rsvd021;
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u8 rsvd022;
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u8 rsvd023;
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u8 rsvd024;
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u8 rsvd025;
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//--- long word 3 ----
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u8 qos_en; // QoS enable
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u8 bw_40MHz_en; // 40MHz BW enable
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u8 AMSDU2AMPDU_en; // 4181 convert AMSDU to AMPDU, 0: disable
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u8 AMPDU_en; // 11n AMPDU enable
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u8 rate_control_offload;//FW offloads, 0: driver handles
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u8 aggregation_offload; // FW offloads, 0: driver handles
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u8 rsvd030;
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u8 rsvd031;
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//--- long word 4 ----
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unsigned char beacon_offload; // 1. FW offloads, 0: driver handles
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unsigned char MLME_offload; // 2. FW offloads, 0: driver handles
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unsigned char hwpc_offload; // 3. FW offloads, 0: driver handles
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unsigned char tcp_checksum_offload; // 4. FW offloads, 0: driver handles
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unsigned char tcp_offload; // 5. FW offloads, 0: driver handles
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unsigned char ps_control_offload; // 6. FW offloads, 0: driver handles
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unsigned char WWLAN_offload; // 7. FW offloads, 0: driver handles
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unsigned char rsvd040;
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//--- long word 5 ----
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u8 tcp_tx_frame_len_L; //tcp tx packet length low byte
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u8 tcp_tx_frame_len_H; //tcp tx packet length high byte
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u8 tcp_rx_frame_len_L; //tcp rx packet length low byte
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u8 tcp_rx_frame_len_H; //tcp rx packet length high byte
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u8 rsvd050;
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u8 rsvd051;
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u8 rsvd052;
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u8 rsvd053;
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}RT_8192S_FIRMWARE_PRIV, *PRT_8192S_FIRMWARE_PRIV;
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typedef struct _RT_8192S_FIRMWARE_HDR {//8-byte alinment required
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//--- LONG WORD 0 ----
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u16 Signature;
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u16 Version; //0x8000 ~ 0x8FFF for FPGA version, 0x0000 ~ 0x7FFF for ASIC version,
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u32 DMEMSize; //define the size of boot loader
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//--- LONG WORD 1 ----
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u32 IMG_IMEM_SIZE; //define the size of FW in IMEM
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u32 IMG_SRAM_SIZE; //define the size of FW in SRAM
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//--- LONG WORD 2 ----
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u32 FW_PRIV_SIZE; //define the size of DMEM variable
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u32 Rsvd0;
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//--- LONG WORD 3 ----
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u32 Rsvd1;
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u32 Rsvd2;
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RT_8192S_FIRMWARE_PRIV FWPriv;
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}RT_8192S_FIRMWARE_HDR, *PRT_8192S_FIRMWARE_HDR;
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#define RT_8192S_FIRMWARE_HDR_SIZE 80
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#define RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE 32
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typedef enum _FIRMWARE_8192S_STATUS{
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FW_STATUS_INIT = 0,
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FW_STATUS_LOAD_IMEM = 1,
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FW_STATUS_LOAD_EMEM = 2,
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FW_STATUS_LOAD_DMEM = 3,
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FW_STATUS_READY = 4,
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}FIRMWARE_8192S_STATUS;
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#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k
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typedef struct _rt_firmware{
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PRT_8192S_FIRMWARE_HDR pFwHeader;
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FIRMWARE_8192S_STATUS FWStatus;
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u16 FirmwareVersion;
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u8 FwIMEM[RTL8190_MAX_FIRMWARE_CODE_SIZE];
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u8 FwEMEM[RTL8190_MAX_FIRMWARE_CODE_SIZE];
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u32 FwIMEMLen;
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u32 FwEMEMLen;
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u8 szFwTmpBuffer[164000];
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u32 szFwTmpBufferLen;
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u16 CmdPacketFragThresold;
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}rt_firmware, *prt_firmware;
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//typedef struct _RT_FIRMWARE_INFO_8192SU{
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// u8 szInfo[16];
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//}RT_FIRMWARE_INFO_8192SU, *PRT_FIRMWARE_INFO_8192SU;
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bool FirmwareDownload92S(struct net_device *dev);
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#endif
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