![David Daney](/assets/img/avatar_default.png)
The octeon-ethernet driver supports the sgmii, rgmii, spi, and xaui ports present on the Cavium OCTEON family of SOCs. These SOCs are multi-core mips64 processors with existing support over in arch/mips. The driver files can be categorized into three basic groups: 1) Register definitions, these are named cvmx-*-defs.h 2) Main driver code, these have names that don't start cvmx-. 3) Interface specific functions and other utility code, names starting with cvmx- Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
114 lines
3.3 KiB
C
114 lines
3.3 KiB
C
/***********************license start***************
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* Author: Cavium Networks
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*
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2008 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Networks for more information
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***********************license end**************************************/
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/*
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* Functions for NPI initialization, configuration,
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* and monitoring.
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*/
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#include <asm/octeon/octeon.h>
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#include "cvmx-config.h"
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#include "cvmx-helper.h"
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#include "cvmx-pip-defs.h"
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/**
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* Probe a NPI interface and determine the number of ports
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* connected to it. The NPI interface should still be down
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* after this call.
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*
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* @interface: Interface to probe
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*
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* Returns Number of ports on the interface. Zero to disable.
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*/
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int __cvmx_helper_npi_probe(int interface)
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{
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#if CVMX_PKO_QUEUES_PER_PORT_PCI > 0
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if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
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return 4;
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else if (OCTEON_IS_MODEL(OCTEON_CN56XX)
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&& !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
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/* The packet engines didn't exist before pass 2 */
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return 4;
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else if (OCTEON_IS_MODEL(OCTEON_CN52XX)
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&& !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X))
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/* The packet engines didn't exist before pass 2 */
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return 4;
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#if 0
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/*
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* Technically CN30XX, CN31XX, and CN50XX contain packet
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* engines, but nobody ever uses them. Since this is the case,
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* we disable them here.
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*/
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else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
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|| OCTEON_IS_MODEL(OCTEON_CN50XX))
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return 2;
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else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
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return 1;
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#endif
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#endif
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return 0;
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}
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/**
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* Bringup and enable a NPI interface. After this call packet
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* I/O should be fully functional. This is called with IPD
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* enabled but PKO disabled.
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*
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* @interface: Interface to bring up
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*
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* Returns Zero on success, negative on failure
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*/
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int __cvmx_helper_npi_enable(int interface)
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{
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/*
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* On CN50XX, CN52XX, and CN56XX we need to disable length
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* checking so packet < 64 bytes and jumbo frames don't get
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* errors.
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*/
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if (!OCTEON_IS_MODEL(OCTEON_CN3XXX) &&
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!OCTEON_IS_MODEL(OCTEON_CN58XX)) {
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int num_ports = cvmx_helper_ports_on_interface(interface);
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int port;
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for (port = 0; port < num_ports; port++) {
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union cvmx_pip_prt_cfgx port_cfg;
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int ipd_port =
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cvmx_helper_get_ipd_port(interface, port);
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port_cfg.u64 =
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cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));
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port_cfg.s.maxerr_en = 0;
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port_cfg.s.minerr_en = 0;
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cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port),
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port_cfg.u64);
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}
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}
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/* Enables are controlled by the remote host, so nothing to do here */
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return 0;
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}
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