9d20015391
Qualcomm development of the MSM SOC framebuffer driver has diverged significantly from the driver used by Android. This is a snapshot of our current driver, in all it's agony. We are putting this in staging to help with the process of converging the two drivers. At this point, the driver has been tested only in dumb framebuffer mode. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org> Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> [dwalker@codeaurora.org: added a small compile fix and TODO.] Signed-off-by: Daniel Walker <dwalker@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
143 lines
3.7 KiB
C
143 lines
3.7 KiB
C
/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/time.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/hrtimer.h>
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#include <linux/delay.h>
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#include <mach/hardware.h>
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#include <linux/io.h>
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#include <asm/system.h>
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#include <asm/mach-types.h>
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#include <linux/semaphore.h>
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#include <linux/spinlock.h>
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#include <linux/fb.h>
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#include "mdp.h"
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#include "msm_fb.h"
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extern spinlock_t mdp_spin_lock;
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extern uint32 mdp_intr_mask;
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int mdp_dma3_on(struct platform_device *pdev)
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{
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struct msm_fb_data_type *mfd;
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struct fb_info *fbi;
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uint8 *buf;
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int bpp;
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int ret = 0;
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mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
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if (!mfd)
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return -ENODEV;
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if (mfd->key != MFD_KEY)
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return -EINVAL;
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fbi = mfd->fbi;
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/* MDP cmd block enable */
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mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
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bpp = fbi->var.bits_per_pixel / 8;
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buf = (uint8 *) fbi->fix.smem_start;
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buf += fbi->var.xoffset * bpp +
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fbi->var.yoffset * fbi->fix.line_length;
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/* starting address[31..8] of Video frame buffer is CS0 */
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MDP_OUTP(MDP_BASE + 0xC0008, (uint32) buf >> 3);
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mdp_pipe_ctrl(MDP_DMA3_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
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MDP_OUTP(MDP_BASE + 0xC0004, 0x4c60674); /* flicker filter enabled */
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MDP_OUTP(MDP_BASE + 0xC0010, 0x20); /* sobel treshold */
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MDP_OUTP(MDP_BASE + 0xC0018, 0xeb0010); /* Y Max, Y min */
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MDP_OUTP(MDP_BASE + 0xC001C, 0xf00010); /* Cb Max, Cb min */
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MDP_OUTP(MDP_BASE + 0xC0020, 0xf00010); /* Cb Max, Cb min */
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MDP_OUTP(MDP_BASE + 0xC000C, 0x67686970); /* add a few chars for CC */
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MDP_OUTP(MDP_BASE + 0xC0000, 0x1); /* MDP tv out enable */
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/* MDP cmd block disable */
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mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
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ret = panel_next_on(pdev);
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return ret;
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}
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int mdp_dma3_off(struct platform_device *pdev)
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{
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int ret = 0;
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ret = panel_next_off(pdev);
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if (ret)
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return ret;
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/* MDP cmd block enable */
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mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
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MDP_OUTP(MDP_BASE + 0xC0000, 0x0);
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/* MDP cmd block disable */
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mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
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mdp_pipe_ctrl(MDP_DMA3_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
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/* delay to make sure the last frame finishes */
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mdelay(100);
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return ret;
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}
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void mdp_dma3_update(struct msm_fb_data_type *mfd)
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{
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struct fb_info *fbi = mfd->fbi;
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uint8 *buf;
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int bpp;
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unsigned long flag;
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if (!mfd->panel_power_on)
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return;
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/* no need to power on cmd block since dma3 is running */
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bpp = fbi->var.bits_per_pixel / 8;
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buf = (uint8 *) fbi->fix.smem_start;
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buf += fbi->var.xoffset * bpp +
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fbi->var.yoffset * fbi->fix.line_length;
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MDP_OUTP(MDP_BASE + 0xC0008, (uint32) buf >> 3);
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spin_lock_irqsave(&mdp_spin_lock, flag);
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mdp_enable_irq(MDP_DMA3_TERM);
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INIT_COMPLETION(mfd->dma->comp);
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mfd->dma->waiting = TRUE;
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outp32(MDP_INTR_CLEAR, TV_OUT_DMA3_START);
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mdp_intr_mask |= TV_OUT_DMA3_START;
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outp32(MDP_INTR_ENABLE, mdp_intr_mask);
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spin_unlock_irqrestore(&mdp_spin_lock, flag);
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wait_for_completion_killable(&mfd->dma->comp);
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mdp_disable_irq(MDP_DMA3_TERM);
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}
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