4b3073e1c5
On VIVT ARM, when we have multiple shared mappings of the same file in the same MM, we need to ensure that we have coherency across all copies. We do this via make_coherent() by making the pages uncacheable. This used to work fine, until we allowed highmem with highpte - we now have a page table which is mapped as required, and is not available for modification via update_mmu_cache(). Ralf Beache suggested getting rid of the PTE value passed to update_mmu_cache(): On MIPS update_mmu_cache() calls __update_tlb() which walks pagetables to construct a pointer to the pte again. Passing a pte_t * is much more elegant. Maybe we might even replace the pte argument with the pte_t? Ben Herrenschmidt would also like the pte pointer for PowerPC: Passing the ptep in there is exactly what I want. I want that -instead- of the PTE value, because I have issue on some ppc cases, for I$/D$ coherency, where set_pte_at() may decide to mask out the _PAGE_EXEC. So, pass in the mapped page table pointer into update_mmu_cache(), and remove the PTE value, updating all implementations and call sites to suit. Includes a fix from Stephen Rothwell: sparc: fix fallout from update_mmu_cache API change Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
166 lines
4.3 KiB
C
166 lines
4.3 KiB
C
#ifndef _M68K_PGTABLE_H
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#define _M68K_PGTABLE_H
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#include <asm-generic/4level-fixup.h>
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#include <asm/setup.h>
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#ifndef __ASSEMBLY__
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#include <asm/processor.h>
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#include <linux/sched.h>
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#include <linux/threads.h>
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/*
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* This file contains the functions and defines necessary to modify and use
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* the m68k page table tree.
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*/
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#include <asm/virtconvert.h>
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/* Certain architectures need to do special things when pte's
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* within a page table are directly modified. Thus, the following
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* hook is made available.
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*/
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#define set_pte(pteptr, pteval) \
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do{ \
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*(pteptr) = (pteval); \
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} while(0)
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#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
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/* PMD_SHIFT determines the size of the area a second-level page table can map */
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#ifdef CONFIG_SUN3
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#define PMD_SHIFT 17
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#else
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#define PMD_SHIFT 22
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#endif
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#define PMD_SIZE (1UL << PMD_SHIFT)
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#define PMD_MASK (~(PMD_SIZE-1))
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/* PGDIR_SHIFT determines what a third-level page table entry can map */
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#ifdef CONFIG_SUN3
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#define PGDIR_SHIFT 17
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#else
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#define PGDIR_SHIFT 25
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#endif
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/*
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* entries per page directory level: the m68k is configured as three-level,
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* so we do have PMD level physically.
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*/
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#ifdef CONFIG_SUN3
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#define PTRS_PER_PTE 16
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#define PTRS_PER_PMD 1
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#define PTRS_PER_PGD 2048
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#else
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#define PTRS_PER_PTE 1024
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#define PTRS_PER_PMD 8
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#define PTRS_PER_PGD 128
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#endif
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#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
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#define FIRST_USER_ADDRESS 0
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/* Virtual address region for use by kernel_map() */
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#ifdef CONFIG_SUN3
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#define KMAP_START 0x0DC00000
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#define KMAP_END 0x0E000000
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#else
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#define KMAP_START 0xd0000000
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#define KMAP_END 0xf0000000
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#endif
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#ifndef CONFIG_SUN3
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/* Just any arbitrary offset to the start of the vmalloc VM area: the
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* current 8MB value just means that there will be a 8MB "hole" after the
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* physical memory until the kernel virtual memory starts. That means that
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* any out-of-bounds memory accesses will hopefully be caught.
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* The vmalloc() routines leaves a hole of 4kB between each vmalloced
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* area for the same reason. ;)
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*/
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#define VMALLOC_OFFSET (8*1024*1024)
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#define VMALLOC_START (((unsigned long) high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
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#define VMALLOC_END KMAP_START
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#else
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extern unsigned long m68k_vmalloc_end;
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#define VMALLOC_START 0x0f800000
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#define VMALLOC_END m68k_vmalloc_end
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#endif /* CONFIG_SUN3 */
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/* zero page used for uninitialized stuff */
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extern void *empty_zero_page;
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/*
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* ZERO_PAGE is a global shared page that is always zero: used
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* for zero-mapped memory areas etc..
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*/
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#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
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/* number of bits that fit into a memory pointer */
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#define BITS_PER_PTR (8*sizeof(unsigned long))
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/* to align the pointer to a pointer address */
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#define PTR_MASK (~(sizeof(void*)-1))
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/* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */
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/* 64-bit machines, beware! SRB. */
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#define SIZEOF_PTR_LOG2 2
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extern void kernel_set_cachemode(void *addr, unsigned long size, int cmode);
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/*
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* The m68k doesn't have any external MMU info: the kernel page
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* tables contain all the necessary information. The Sun3 does, but
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* they are updated on demand.
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*/
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static inline void update_mmu_cache(struct vm_area_struct *vma,
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unsigned long address, pte_t *ptep)
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{
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}
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#endif /* !__ASSEMBLY__ */
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#define kern_addr_valid(addr) (1)
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#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
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remap_pfn_range(vma, vaddr, pfn, size, prot)
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/* MMU-specific headers */
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#ifdef CONFIG_SUN3
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#include <asm/sun3_pgtable.h>
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#else
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#include <asm/motorola_pgtable.h>
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#endif
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#ifndef __ASSEMBLY__
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/*
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* Macro to mark a page protection value as "uncacheable".
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*/
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#ifdef SUN3_PAGE_NOCACHE
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# define __SUN3_PAGE_NOCACHE SUN3_PAGE_NOCACHE
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#else
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# define __SUN3_PAGE_NOCACHE 0
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#endif
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#define pgprot_noncached(prot) \
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(MMU_IS_SUN3 \
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? (__pgprot(pgprot_val(prot) | __SUN3_PAGE_NOCACHE)) \
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: ((MMU_IS_851 || MMU_IS_030) \
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? (__pgprot(pgprot_val(prot) | _PAGE_NOCACHE030)) \
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: (MMU_IS_040 || MMU_IS_060) \
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? (__pgprot((pgprot_val(prot) & _CACHEMASK040) | _PAGE_NOCACHE_S)) \
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: (prot)))
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#include <asm-generic/pgtable.h>
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#endif /* !__ASSEMBLY__ */
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/*
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* No page table caches to initialise
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*/
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#define pgtable_cache_init() do { } while (0)
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#define check_pgt_cache() do { } while (0)
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#endif /* _M68K_PGTABLE_H */
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