344 lines
16 KiB
C
344 lines
16 KiB
C
#ifndef __NOUVEAU_CLASS_H__
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#define __NOUVEAU_CLASS_H__
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/* Device class
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*
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* 0080: NV_DEVICE
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*/
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#define NV_DEVICE_CLASS 0x00000080
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#define NV_DEVICE_DISABLE_IDENTIFY 0x0000000000000001ULL
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#define NV_DEVICE_DISABLE_MMIO 0x0000000000000002ULL
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#define NV_DEVICE_DISABLE_VBIOS 0x0000000000000004ULL
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#define NV_DEVICE_DISABLE_CORE 0x0000000000000008ULL
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#define NV_DEVICE_DISABLE_DISP 0x0000000000010000ULL
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#define NV_DEVICE_DISABLE_FIFO 0x0000000000020000ULL
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#define NV_DEVICE_DISABLE_GRAPH 0x0000000100000000ULL
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#define NV_DEVICE_DISABLE_MPEG 0x0000000200000000ULL
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#define NV_DEVICE_DISABLE_ME 0x0000000400000000ULL
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#define NV_DEVICE_DISABLE_VP 0x0000000800000000ULL
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#define NV_DEVICE_DISABLE_CRYPT 0x0000001000000000ULL
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#define NV_DEVICE_DISABLE_BSP 0x0000002000000000ULL
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#define NV_DEVICE_DISABLE_PPP 0x0000004000000000ULL
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#define NV_DEVICE_DISABLE_COPY0 0x0000008000000000ULL
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#define NV_DEVICE_DISABLE_COPY1 0x0000010000000000ULL
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#define NV_DEVICE_DISABLE_UNK1C1 0x0000020000000000ULL
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#define NV_DEVICE_DISABLE_VENC 0x0000040000000000ULL
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struct nv_device_class {
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u64 device; /* device identifier, ~0 for client default */
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u64 disable; /* disable particular subsystems */
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u64 debug0; /* as above, but *internal* ids, and *NOT* ABI */
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};
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/* DMA object classes
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*
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* 0002: NV_DMA_FROM_MEMORY
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* 0003: NV_DMA_TO_MEMORY
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* 003d: NV_DMA_IN_MEMORY
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*/
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#define NV_DMA_FROM_MEMORY_CLASS 0x00000002
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#define NV_DMA_TO_MEMORY_CLASS 0x00000003
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#define NV_DMA_IN_MEMORY_CLASS 0x0000003d
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#define NV_DMA_TARGET_MASK 0x000000ff
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#define NV_DMA_TARGET_VM 0x00000000
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#define NV_DMA_TARGET_VRAM 0x00000001
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#define NV_DMA_TARGET_PCI 0x00000002
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#define NV_DMA_TARGET_PCI_US 0x00000003
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#define NV_DMA_TARGET_AGP 0x00000004
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#define NV_DMA_ACCESS_MASK 0x00000f00
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#define NV_DMA_ACCESS_VM 0x00000000
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#define NV_DMA_ACCESS_RD 0x00000100
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#define NV_DMA_ACCESS_WR 0x00000200
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#define NV_DMA_ACCESS_RDWR 0x00000300
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/* NV50:NVC0 */
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#define NV50_DMA_CONF0_ENABLE 0x80000000
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#define NV50_DMA_CONF0_PRIV 0x00300000
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#define NV50_DMA_CONF0_PRIV_VM 0x00000000
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#define NV50_DMA_CONF0_PRIV_US 0x00100000
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#define NV50_DMA_CONF0_PRIV__S 0x00200000
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#define NV50_DMA_CONF0_PART 0x00030000
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#define NV50_DMA_CONF0_PART_VM 0x00000000
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#define NV50_DMA_CONF0_PART_256 0x00010000
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#define NV50_DMA_CONF0_PART_1KB 0x00020000
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#define NV50_DMA_CONF0_COMP 0x00000180
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#define NV50_DMA_CONF0_COMP_NONE 0x00000000
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#define NV50_DMA_CONF0_COMP_VM 0x00000180
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#define NV50_DMA_CONF0_TYPE 0x0000007f
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#define NV50_DMA_CONF0_TYPE_LINEAR 0x00000000
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#define NV50_DMA_CONF0_TYPE_VM 0x0000007f
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/* NVC0:NVD9 */
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#define NVC0_DMA_CONF0_ENABLE 0x80000000
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#define NVC0_DMA_CONF0_PRIV 0x00300000
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#define NVC0_DMA_CONF0_PRIV_VM 0x00000000
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#define NVC0_DMA_CONF0_PRIV_US 0x00100000
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#define NVC0_DMA_CONF0_PRIV__S 0x00200000
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#define NVC0_DMA_CONF0_UNKN /* PART? */ 0x00030000
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#define NVC0_DMA_CONF0_TYPE 0x000000ff
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#define NVC0_DMA_CONF0_TYPE_LINEAR 0x00000000
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#define NVC0_DMA_CONF0_TYPE_VM 0x000000ff
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/* NVD9- */
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#define NVD0_DMA_CONF0_ENABLE 0x80000000
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#define NVD0_DMA_CONF0_PAGE 0x00000400
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#define NVD0_DMA_CONF0_PAGE_LP 0x00000000
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#define NVD0_DMA_CONF0_PAGE_SP 0x00000400
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#define NVD0_DMA_CONF0_TYPE 0x000000ff
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#define NVD0_DMA_CONF0_TYPE_LINEAR 0x00000000
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#define NVD0_DMA_CONF0_TYPE_VM 0x000000ff
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struct nv_dma_class {
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u32 flags;
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u32 pad0;
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u64 start;
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u64 limit;
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u32 conf0;
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};
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/* DMA FIFO channel classes
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*
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* 006b: NV03_CHANNEL_DMA
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* 006e: NV10_CHANNEL_DMA
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* 176e: NV17_CHANNEL_DMA
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* 406e: NV40_CHANNEL_DMA
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* 506e: NV50_CHANNEL_DMA
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* 826e: NV84_CHANNEL_DMA
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*/
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#define NV03_CHANNEL_DMA_CLASS 0x0000006b
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#define NV10_CHANNEL_DMA_CLASS 0x0000006e
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#define NV17_CHANNEL_DMA_CLASS 0x0000176e
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#define NV40_CHANNEL_DMA_CLASS 0x0000406e
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#define NV50_CHANNEL_DMA_CLASS 0x0000506e
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#define NV84_CHANNEL_DMA_CLASS 0x0000826e
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struct nv03_channel_dma_class {
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u32 pushbuf;
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u32 pad0;
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u64 offset;
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};
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/* Indirect FIFO channel classes
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*
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* 506f: NV50_CHANNEL_IND
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* 826f: NV84_CHANNEL_IND
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* 906f: NVC0_CHANNEL_IND
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* a06f: NVE0_CHANNEL_IND
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*/
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#define NV50_CHANNEL_IND_CLASS 0x0000506f
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#define NV84_CHANNEL_IND_CLASS 0x0000826f
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#define NVC0_CHANNEL_IND_CLASS 0x0000906f
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#define NVE0_CHANNEL_IND_CLASS 0x0000a06f
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struct nv50_channel_ind_class {
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u32 pushbuf;
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u32 ilength;
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u64 ioffset;
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};
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#define NVE0_CHANNEL_IND_ENGINE_GR 0x00000001
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#define NVE0_CHANNEL_IND_ENGINE_VP 0x00000002
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#define NVE0_CHANNEL_IND_ENGINE_PPP 0x00000004
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#define NVE0_CHANNEL_IND_ENGINE_BSP 0x00000008
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#define NVE0_CHANNEL_IND_ENGINE_CE0 0x00000010
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#define NVE0_CHANNEL_IND_ENGINE_CE1 0x00000020
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#define NVE0_CHANNEL_IND_ENGINE_ENC 0x00000040
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struct nve0_channel_ind_class {
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u32 pushbuf;
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u32 ilength;
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u64 ioffset;
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u32 engine;
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};
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/* 5070: NV50_DISP
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* 8270: NV84_DISP
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* 8370: NVA0_DISP
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* 8870: NV94_DISP
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* 8570: NVA3_DISP
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* 9070: NVD0_DISP
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* 9170: NVE0_DISP
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*/
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#define NV50_DISP_CLASS 0x00005070
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#define NV84_DISP_CLASS 0x00008270
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#define NVA0_DISP_CLASS 0x00008370
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#define NV94_DISP_CLASS 0x00008870
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#define NVA3_DISP_CLASS 0x00008570
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#define NVD0_DISP_CLASS 0x00009070
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#define NVE0_DISP_CLASS 0x00009170
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#define NV50_DISP_SOR_MTHD 0x00010000
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#define NV50_DISP_SOR_MTHD_TYPE 0x0000f000
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#define NV50_DISP_SOR_MTHD_HEAD 0x00000018
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#define NV50_DISP_SOR_MTHD_LINK 0x00000004
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#define NV50_DISP_SOR_MTHD_OR 0x00000003
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#define NV50_DISP_SOR_PWR 0x00010000
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#define NV50_DISP_SOR_PWR_STATE 0x00000001
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#define NV50_DISP_SOR_PWR_STATE_ON 0x00000001
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#define NV50_DISP_SOR_PWR_STATE_OFF 0x00000000
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#define NVA3_DISP_SOR_HDA_ELD 0x00010100
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#define NV84_DISP_SOR_HDMI_PWR 0x00012000
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#define NV84_DISP_SOR_HDMI_PWR_STATE 0x40000000
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#define NV84_DISP_SOR_HDMI_PWR_STATE_OFF 0x00000000
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#define NV84_DISP_SOR_HDMI_PWR_STATE_ON 0x40000000
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#define NV84_DISP_SOR_HDMI_PWR_MAX_AC_PACKET 0x001f0000
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#define NV84_DISP_SOR_HDMI_PWR_REKEY 0x0000007f
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#define NV50_DISP_SOR_LVDS_SCRIPT 0x00013000
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#define NV50_DISP_SOR_LVDS_SCRIPT_ID 0x0000ffff
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#define NV94_DISP_SOR_DP_TRAIN 0x00016000
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#define NV94_DISP_SOR_DP_TRAIN_OP 0xf0000000
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#define NV94_DISP_SOR_DP_TRAIN_OP_PATTERN 0x00000000
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#define NV94_DISP_SOR_DP_TRAIN_OP_INIT 0x10000000
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#define NV94_DISP_SOR_DP_TRAIN_OP_FINI 0x20000000
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#define NV94_DISP_SOR_DP_TRAIN_INIT_SPREAD 0x00000001
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#define NV94_DISP_SOR_DP_TRAIN_INIT_SPREAD_OFF 0x00000000
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#define NV94_DISP_SOR_DP_TRAIN_INIT_SPREAD_ON 0x00000001
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#define NV94_DISP_SOR_DP_TRAIN_PATTERN 0x00000003
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#define NV94_DISP_SOR_DP_TRAIN_PATTERN_DISABLED 0x00000000
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#define NV94_DISP_SOR_DP_LNKCTL 0x00016040
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#define NV94_DISP_SOR_DP_LNKCTL_FRAME 0x80000000
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#define NV94_DISP_SOR_DP_LNKCTL_FRAME_STD 0x00000000
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#define NV94_DISP_SOR_DP_LNKCTL_FRAME_ENH 0x80000000
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#define NV94_DISP_SOR_DP_LNKCTL_WIDTH 0x00001f00
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#define NV94_DISP_SOR_DP_LNKCTL_COUNT 0x00000007
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#define NV94_DISP_SOR_DP_DRVCTL(l) ((l) * 0x40 + 0x00016100)
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#define NV94_DISP_SOR_DP_DRVCTL_VS 0x00000300
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#define NV94_DISP_SOR_DP_DRVCTL_PE 0x00000003
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#define NV50_DISP_DAC_MTHD 0x00020000
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#define NV50_DISP_DAC_MTHD_TYPE 0x0000f000
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#define NV50_DISP_DAC_MTHD_OR 0x00000003
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#define NV50_DISP_DAC_PWR 0x00020000
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#define NV50_DISP_DAC_PWR_HSYNC 0x00000001
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#define NV50_DISP_DAC_PWR_HSYNC_ON 0x00000000
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#define NV50_DISP_DAC_PWR_HSYNC_LO 0x00000001
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#define NV50_DISP_DAC_PWR_VSYNC 0x00000004
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#define NV50_DISP_DAC_PWR_VSYNC_ON 0x00000000
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#define NV50_DISP_DAC_PWR_VSYNC_LO 0x00000004
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#define NV50_DISP_DAC_PWR_DATA 0x00000010
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#define NV50_DISP_DAC_PWR_DATA_ON 0x00000000
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#define NV50_DISP_DAC_PWR_DATA_LO 0x00000010
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#define NV50_DISP_DAC_PWR_STATE 0x00000040
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#define NV50_DISP_DAC_PWR_STATE_ON 0x00000000
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#define NV50_DISP_DAC_PWR_STATE_OFF 0x00000040
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#define NV50_DISP_DAC_LOAD 0x0002000c
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#define NV50_DISP_DAC_LOAD_VALUE 0x00000007
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struct nv50_display_class {
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};
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/* 507a: NV50_DISP_CURS
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* 827a: NV84_DISP_CURS
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* 837a: NVA0_DISP_CURS
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* 887a: NV94_DISP_CURS
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* 857a: NVA3_DISP_CURS
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* 907a: NVD0_DISP_CURS
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* 917a: NVE0_DISP_CURS
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*/
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#define NV50_DISP_CURS_CLASS 0x0000507a
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#define NV84_DISP_CURS_CLASS 0x0000827a
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#define NVA0_DISP_CURS_CLASS 0x0000837a
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#define NV94_DISP_CURS_CLASS 0x0000887a
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#define NVA3_DISP_CURS_CLASS 0x0000857a
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#define NVD0_DISP_CURS_CLASS 0x0000907a
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#define NVE0_DISP_CURS_CLASS 0x0000917a
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struct nv50_display_curs_class {
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u32 head;
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};
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/* 507b: NV50_DISP_OIMM
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* 827b: NV84_DISP_OIMM
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* 837b: NVA0_DISP_OIMM
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* 887b: NV94_DISP_OIMM
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* 857b: NVA3_DISP_OIMM
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* 907b: NVD0_DISP_OIMM
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* 917b: NVE0_DISP_OIMM
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*/
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#define NV50_DISP_OIMM_CLASS 0x0000507b
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#define NV84_DISP_OIMM_CLASS 0x0000827b
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#define NVA0_DISP_OIMM_CLASS 0x0000837b
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#define NV94_DISP_OIMM_CLASS 0x0000887b
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#define NVA3_DISP_OIMM_CLASS 0x0000857b
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#define NVD0_DISP_OIMM_CLASS 0x0000907b
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#define NVE0_DISP_OIMM_CLASS 0x0000917b
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struct nv50_display_oimm_class {
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u32 head;
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};
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/* 507c: NV50_DISP_SYNC
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* 827c: NV84_DISP_SYNC
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* 837c: NVA0_DISP_SYNC
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* 887c: NV94_DISP_SYNC
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* 857c: NVA3_DISP_SYNC
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* 907c: NVD0_DISP_SYNC
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* 917c: NVE0_DISP_SYNC
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*/
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#define NV50_DISP_SYNC_CLASS 0x0000507c
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#define NV84_DISP_SYNC_CLASS 0x0000827c
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#define NVA0_DISP_SYNC_CLASS 0x0000837c
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#define NV94_DISP_SYNC_CLASS 0x0000887c
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#define NVA3_DISP_SYNC_CLASS 0x0000857c
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#define NVD0_DISP_SYNC_CLASS 0x0000907c
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#define NVE0_DISP_SYNC_CLASS 0x0000917c
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struct nv50_display_sync_class {
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u32 pushbuf;
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u32 head;
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};
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/* 507d: NV50_DISP_MAST
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* 827d: NV84_DISP_MAST
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* 837d: NVA0_DISP_MAST
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* 887d: NV94_DISP_MAST
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* 857d: NVA3_DISP_MAST
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* 907d: NVD0_DISP_MAST
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* 917d: NVE0_DISP_MAST
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*/
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#define NV50_DISP_MAST_CLASS 0x0000507d
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#define NV84_DISP_MAST_CLASS 0x0000827d
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#define NVA0_DISP_MAST_CLASS 0x0000837d
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#define NV94_DISP_MAST_CLASS 0x0000887d
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#define NVA3_DISP_MAST_CLASS 0x0000857d
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#define NVD0_DISP_MAST_CLASS 0x0000907d
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#define NVE0_DISP_MAST_CLASS 0x0000917d
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struct nv50_display_mast_class {
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u32 pushbuf;
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};
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/* 507e: NV50_DISP_OVLY
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* 827e: NV84_DISP_OVLY
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* 837e: NVA0_DISP_OVLY
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* 887e: NV94_DISP_OVLY
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* 857e: NVA3_DISP_OVLY
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* 907e: NVD0_DISP_OVLY
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* 917e: NVE0_DISP_OVLY
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*/
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#define NV50_DISP_OVLY_CLASS 0x0000507e
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#define NV84_DISP_OVLY_CLASS 0x0000827e
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#define NVA0_DISP_OVLY_CLASS 0x0000837e
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#define NV94_DISP_OVLY_CLASS 0x0000887e
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#define NVA3_DISP_OVLY_CLASS 0x0000857e
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#define NVD0_DISP_OVLY_CLASS 0x0000907e
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#define NVE0_DISP_OVLY_CLASS 0x0000917e
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struct nv50_display_ovly_class {
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u32 pushbuf;
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u32 head;
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};
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#endif
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