![Linus Torvalds](/assets/img/avatar_default.png)
* 'cpus4096-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (66 commits) x86: export vector_used_by_percpu_irq x86: use logical apicid in x2apic_cluster's x2apic_cpu_mask_to_apicid_and() sched: nominate preferred wakeup cpu, fix x86: fix lguest used_vectors breakage, -v2 x86: fix warning in arch/x86/kernel/io_apic.c sched: fix warning in kernel/sched.c sched: move test_sd_parent() to an SMP section of sched.h sched: add SD_BALANCE_NEWIDLE at MC and CPU level for sched_mc>0 sched: activate active load balancing in new idle cpus sched: bias task wakeups to preferred semi-idle packages sched: nominate preferred wakeup cpu sched: favour lower logical cpu number for sched_mc balance sched: framework for sched_mc/smt_power_savings=N sched: convert BALANCE_FOR_xx_POWER to inline functions x86: use possible_cpus=NUM to extend the possible cpus allowed x86: fix cpu_mask_to_apicid_and to include cpu_online_mask x86: update io_apic.c to the new cpumask code x86: Introduce topology_core_cpumask()/topology_thread_cpumask() x86: xen: use smp_call_function_many() x86: use work_on_cpu in x86/kernel/cpu/mcheck/mce_amd_64.c ... Fixed up trivial conflict in kernel/time/tick-sched.c manually
601 lines
15 KiB
C
601 lines
15 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* SGI UV APIC functions (note: not an Intel compatible APIC)
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*
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* Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
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*/
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#include <linux/kernel.h>
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#include <linux/threads.h>
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#include <linux/cpu.h>
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#include <linux/cpumask.h>
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#include <linux/string.h>
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#include <linux/ctype.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/module.h>
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#include <linux/hardirq.h>
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#include <linux/timer.h>
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#include <linux/proc_fs.h>
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#include <asm/current.h>
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#include <asm/smp.h>
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#include <asm/ipi.h>
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#include <asm/genapic.h>
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#include <asm/pgtable.h>
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#include <asm/uv/uv_mmrs.h>
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#include <asm/uv/uv_hub.h>
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#include <asm/uv/bios.h>
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DEFINE_PER_CPU(int, x2apic_extra_bits);
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static enum uv_system_type uv_system_type;
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static int uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
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{
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if (!strcmp(oem_id, "SGI")) {
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if (!strcmp(oem_table_id, "UVL"))
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uv_system_type = UV_LEGACY_APIC;
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else if (!strcmp(oem_table_id, "UVX"))
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uv_system_type = UV_X2APIC;
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else if (!strcmp(oem_table_id, "UVH")) {
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uv_system_type = UV_NON_UNIQUE_APIC;
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return 1;
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}
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}
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return 0;
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}
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enum uv_system_type get_uv_system_type(void)
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{
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return uv_system_type;
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}
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int is_uv_system(void)
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{
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return uv_system_type != UV_NONE;
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}
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EXPORT_SYMBOL_GPL(is_uv_system);
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DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
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EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
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struct uv_blade_info *uv_blade_info;
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EXPORT_SYMBOL_GPL(uv_blade_info);
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short *uv_node_to_blade;
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EXPORT_SYMBOL_GPL(uv_node_to_blade);
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short *uv_cpu_to_blade;
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EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
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short uv_possible_blades;
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EXPORT_SYMBOL_GPL(uv_possible_blades);
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unsigned long sn_rtc_cycles_per_second;
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EXPORT_SYMBOL(sn_rtc_cycles_per_second);
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/* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */
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static const struct cpumask *uv_target_cpus(void)
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{
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return cpumask_of(0);
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}
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static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
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{
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cpumask_clear(retmask);
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cpumask_set_cpu(cpu, retmask);
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}
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int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
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{
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unsigned long val;
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int pnode;
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pnode = uv_apicid_to_pnode(phys_apicid);
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val = (1UL << UVH_IPI_INT_SEND_SHFT) |
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(phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
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(((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
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APIC_DM_INIT;
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uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
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mdelay(10);
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val = (1UL << UVH_IPI_INT_SEND_SHFT) |
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(phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
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(((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
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APIC_DM_STARTUP;
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uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
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return 0;
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}
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static void uv_send_IPI_one(int cpu, int vector)
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{
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unsigned long val, apicid, lapicid;
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int pnode;
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apicid = per_cpu(x86_cpu_to_apicid, cpu);
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lapicid = apicid & 0x3f; /* ZZZ macro needed */
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pnode = uv_apicid_to_pnode(apicid);
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val =
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(1UL << UVH_IPI_INT_SEND_SHFT) | (lapicid <<
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UVH_IPI_INT_APIC_ID_SHFT) |
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(vector << UVH_IPI_INT_VECTOR_SHFT);
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uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
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}
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static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
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{
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unsigned int cpu;
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for_each_cpu(cpu, mask)
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uv_send_IPI_one(cpu, vector);
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}
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static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
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{
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unsigned int cpu;
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unsigned int this_cpu = smp_processor_id();
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for_each_cpu(cpu, mask)
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if (cpu != this_cpu)
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uv_send_IPI_one(cpu, vector);
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}
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static void uv_send_IPI_allbutself(int vector)
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{
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unsigned int cpu;
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unsigned int this_cpu = smp_processor_id();
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for_each_online_cpu(cpu)
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if (cpu != this_cpu)
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uv_send_IPI_one(cpu, vector);
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}
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static void uv_send_IPI_all(int vector)
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{
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uv_send_IPI_mask(cpu_online_mask, vector);
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}
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static int uv_apic_id_registered(void)
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{
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return 1;
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}
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static void uv_init_apic_ldr(void)
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{
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}
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static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
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{
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int cpu;
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/*
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* We're using fixed IRQ delivery, can only return one phys APIC ID.
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* May as well be the first.
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*/
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cpu = cpumask_first(cpumask);
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if ((unsigned)cpu < nr_cpu_ids)
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return per_cpu(x86_cpu_to_apicid, cpu);
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else
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return BAD_APICID;
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}
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static unsigned int uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
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const struct cpumask *andmask)
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{
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int cpu;
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/*
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* We're using fixed IRQ delivery, can only return one phys APIC ID.
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* May as well be the first.
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*/
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for_each_cpu_and(cpu, cpumask, andmask)
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if (cpumask_test_cpu(cpu, cpu_online_mask))
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break;
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if (cpu < nr_cpu_ids)
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return per_cpu(x86_cpu_to_apicid, cpu);
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return BAD_APICID;
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}
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static unsigned int get_apic_id(unsigned long x)
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{
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unsigned int id;
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WARN_ON(preemptible() && num_online_cpus() > 1);
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id = x | __get_cpu_var(x2apic_extra_bits);
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return id;
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}
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static unsigned long set_apic_id(unsigned int id)
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{
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unsigned long x;
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/* maskout x2apic_extra_bits ? */
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x = id;
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return x;
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}
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static unsigned int uv_read_apic_id(void)
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{
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return get_apic_id(apic_read(APIC_ID));
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}
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static unsigned int phys_pkg_id(int index_msb)
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{
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return uv_read_apic_id() >> index_msb;
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}
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static void uv_send_IPI_self(int vector)
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{
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apic_write(APIC_SELF_IPI, vector);
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}
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struct genapic apic_x2apic_uv_x = {
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.name = "UV large system",
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.acpi_madt_oem_check = uv_acpi_madt_oem_check,
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.int_delivery_mode = dest_Fixed,
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.int_dest_mode = (APIC_DEST_PHYSICAL != 0),
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.target_cpus = uv_target_cpus,
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.vector_allocation_domain = uv_vector_allocation_domain,
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.apic_id_registered = uv_apic_id_registered,
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.init_apic_ldr = uv_init_apic_ldr,
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.send_IPI_all = uv_send_IPI_all,
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.send_IPI_allbutself = uv_send_IPI_allbutself,
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.send_IPI_mask = uv_send_IPI_mask,
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.send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
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.send_IPI_self = uv_send_IPI_self,
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.cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
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.cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and,
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.phys_pkg_id = phys_pkg_id,
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.get_apic_id = get_apic_id,
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.set_apic_id = set_apic_id,
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.apic_id_mask = (0xFFFFFFFFu),
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};
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static __cpuinit void set_x2apic_extra_bits(int pnode)
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{
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__get_cpu_var(x2apic_extra_bits) = (pnode << 6);
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}
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/*
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* Called on boot cpu.
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*/
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static __init int boot_pnode_to_blade(int pnode)
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{
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int blade;
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for (blade = 0; blade < uv_num_possible_blades(); blade++)
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if (pnode == uv_blade_info[blade].pnode)
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return blade;
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BUG();
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}
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struct redir_addr {
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unsigned long redirect;
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unsigned long alias;
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};
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#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
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static __initdata struct redir_addr redir_addrs[] = {
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{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
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{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
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{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
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};
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static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
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{
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union uvh_si_alias0_overlay_config_u alias;
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union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
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int i;
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for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
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alias.v = uv_read_local_mmr(redir_addrs[i].alias);
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if (alias.s.base == 0) {
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*size = (1UL << alias.s.m_alias);
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redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
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*base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
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return;
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}
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}
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BUG();
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}
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static __init void map_low_mmrs(void)
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{
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init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
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init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
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}
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enum map_type {map_wb, map_uc};
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static __init void map_high(char *id, unsigned long base, int shift,
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int max_pnode, enum map_type map_type)
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{
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unsigned long bytes, paddr;
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paddr = base << shift;
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bytes = (1UL << shift) * (max_pnode + 1);
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printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
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paddr + bytes);
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if (map_type == map_uc)
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init_extra_mapping_uc(paddr, bytes);
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else
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init_extra_mapping_wb(paddr, bytes);
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}
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static __init void map_gru_high(int max_pnode)
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{
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union uvh_rh_gam_gru_overlay_config_mmr_u gru;
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int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
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gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
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if (gru.s.enable)
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map_high("GRU", gru.s.base, shift, max_pnode, map_wb);
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}
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static __init void map_config_high(int max_pnode)
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{
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union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
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int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;
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cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
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if (cfg.s.enable)
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map_high("CONFIG", cfg.s.base, shift, max_pnode, map_uc);
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}
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static __init void map_mmr_high(int max_pnode)
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{
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union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
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int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
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mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
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if (mmr.s.enable)
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map_high("MMR", mmr.s.base, shift, max_pnode, map_uc);
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}
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static __init void map_mmioh_high(int max_pnode)
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{
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union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
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int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
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mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
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if (mmioh.s.enable)
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map_high("MMIOH", mmioh.s.base, shift, max_pnode, map_uc);
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}
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static __init void uv_rtc_init(void)
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{
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long status;
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u64 ticks_per_sec;
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status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
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&ticks_per_sec);
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if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
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printk(KERN_WARNING
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"unable to determine platform RTC clock frequency, "
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"guessing.\n");
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/* BIOS gives wrong value for clock freq. so guess */
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sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
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} else
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sn_rtc_cycles_per_second = ticks_per_sec;
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}
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/*
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* percpu heartbeat timer
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*/
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static void uv_heartbeat(unsigned long ignored)
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{
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struct timer_list *timer = &uv_hub_info->scir.timer;
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unsigned char bits = uv_hub_info->scir.state;
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/* flip heartbeat bit */
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bits ^= SCIR_CPU_HEARTBEAT;
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/* is this cpu idle? */
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if (idle_cpu(raw_smp_processor_id()))
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bits &= ~SCIR_CPU_ACTIVITY;
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else
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bits |= SCIR_CPU_ACTIVITY;
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/* update system controller interface reg */
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uv_set_scir_bits(bits);
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/* enable next timer period */
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mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL);
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}
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static void __cpuinit uv_heartbeat_enable(int cpu)
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{
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if (!uv_cpu_hub_info(cpu)->scir.enabled) {
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struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
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uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
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setup_timer(timer, uv_heartbeat, cpu);
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timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
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add_timer_on(timer, cpu);
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uv_cpu_hub_info(cpu)->scir.enabled = 1;
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}
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/* check boot cpu */
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if (!uv_cpu_hub_info(0)->scir.enabled)
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uv_heartbeat_enable(0);
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}
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#ifdef CONFIG_HOTPLUG_CPU
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static void __cpuinit uv_heartbeat_disable(int cpu)
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{
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if (uv_cpu_hub_info(cpu)->scir.enabled) {
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uv_cpu_hub_info(cpu)->scir.enabled = 0;
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del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
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}
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uv_set_cpu_scir_bits(cpu, 0xff);
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}
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/*
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* cpu hotplug notifier
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*/
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static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
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unsigned long action, void *hcpu)
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{
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long cpu = (long)hcpu;
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switch (action) {
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case CPU_ONLINE:
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uv_heartbeat_enable(cpu);
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break;
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case CPU_DOWN_PREPARE:
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uv_heartbeat_disable(cpu);
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break;
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default:
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break;
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}
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return NOTIFY_OK;
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}
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static __init void uv_scir_register_cpu_notifier(void)
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{
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hotcpu_notifier(uv_scir_cpu_notify, 0);
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}
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|
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#else /* !CONFIG_HOTPLUG_CPU */
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|
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static __init void uv_scir_register_cpu_notifier(void)
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|
{
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}
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|
|
|
static __init int uv_init_heartbeat(void)
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|
{
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|
int cpu;
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|
|
|
if (is_uv_system())
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for_each_online_cpu(cpu)
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uv_heartbeat_enable(cpu);
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return 0;
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|
}
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|
|
|
late_initcall(uv_init_heartbeat);
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|
|
|
#endif /* !CONFIG_HOTPLUG_CPU */
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|
|
|
/*
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* Called on each cpu to initialize the per_cpu UV data area.
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* ZZZ hotplug not supported yet
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|
*/
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|
void __cpuinit uv_cpu_init(void)
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|
{
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|
/* CPU 0 initilization will be done via uv_system_init. */
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|
if (!uv_blade_info)
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|
return;
|
|
|
|
uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
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|
|
|
if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
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|
set_x2apic_extra_bits(uv_hub_info->pnode);
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|
}
|
|
|
|
|
|
void __init uv_system_init(void)
|
|
{
|
|
union uvh_si_addr_map_config_u m_n_config;
|
|
union uvh_node_id_u node_id;
|
|
unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
|
|
int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
|
|
int max_pnode = 0;
|
|
unsigned long mmr_base, present;
|
|
|
|
map_low_mmrs();
|
|
|
|
m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
|
|
m_val = m_n_config.s.m_skt;
|
|
n_val = m_n_config.s.n_skt;
|
|
mmr_base =
|
|
uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
|
|
~UV_MMR_ENABLE;
|
|
printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
|
|
|
|
for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
|
|
uv_possible_blades +=
|
|
hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
|
|
printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
|
|
|
|
bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
|
|
uv_blade_info = kmalloc(bytes, GFP_KERNEL);
|
|
|
|
get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
|
|
|
|
bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
|
|
uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
|
|
memset(uv_node_to_blade, 255, bytes);
|
|
|
|
bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
|
|
uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
|
|
memset(uv_cpu_to_blade, 255, bytes);
|
|
|
|
blade = 0;
|
|
for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
|
|
present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
|
|
for (j = 0; j < 64; j++) {
|
|
if (!test_bit(j, &present))
|
|
continue;
|
|
uv_blade_info[blade].pnode = (i * 64 + j);
|
|
uv_blade_info[blade].nr_possible_cpus = 0;
|
|
uv_blade_info[blade].nr_online_cpus = 0;
|
|
blade++;
|
|
}
|
|
}
|
|
|
|
node_id.v = uv_read_local_mmr(UVH_NODE_ID);
|
|
gnode_upper = (((unsigned long)node_id.s.node_id) &
|
|
~((1 << n_val) - 1)) << m_val;
|
|
|
|
uv_bios_init();
|
|
uv_bios_get_sn_info(0, &uv_type, &sn_partition_id,
|
|
&sn_coherency_id, &sn_region_size);
|
|
uv_rtc_init();
|
|
|
|
for_each_present_cpu(cpu) {
|
|
nid = cpu_to_node(cpu);
|
|
pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
|
|
blade = boot_pnode_to_blade(pnode);
|
|
lcpu = uv_blade_info[blade].nr_possible_cpus;
|
|
uv_blade_info[blade].nr_possible_cpus++;
|
|
|
|
uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
|
|
uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
|
|
uv_cpu_hub_info(cpu)->m_val = m_val;
|
|
uv_cpu_hub_info(cpu)->n_val = m_val;
|
|
uv_cpu_hub_info(cpu)->numa_blade_id = blade;
|
|
uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
|
|
uv_cpu_hub_info(cpu)->pnode = pnode;
|
|
uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
|
|
uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
|
|
uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
|
|
uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
|
|
uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
|
|
uv_cpu_hub_info(cpu)->scir.offset = SCIR_LOCAL_MMR_BASE + lcpu;
|
|
uv_node_to_blade[nid] = blade;
|
|
uv_cpu_to_blade[cpu] = blade;
|
|
max_pnode = max(pnode, max_pnode);
|
|
|
|
printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
|
|
"lcpu %d, blade %d\n",
|
|
cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
|
|
lcpu, blade);
|
|
}
|
|
|
|
map_gru_high(max_pnode);
|
|
map_mmr_high(max_pnode);
|
|
map_config_high(max_pnode);
|
|
map_mmioh_high(max_pnode);
|
|
|
|
uv_cpu_init();
|
|
uv_scir_register_cpu_notifier();
|
|
proc_mkdir("sgi_uv", NULL);
|
|
}
|