![Suresh Siddha](/assets/img/avatar_default.png)
These commits: commit95d313cf1c
Author: Mike Travis <travis@sgi.com> Date: Tue Dec 16 17:33:54 2008 -0800 x86: Add cpu_mask_to_apicid_and and commit6eeb7c5a99
Author: Mike Travis <travis@sgi.com> Date: Tue Dec 16 17:33:55 2008 -0800 x86: update add-cpu_mask_to_apicid_and to use struct cpumask* broke interrupt delivery on x2apic platforms. As x2apic cluster mode uses logical delivery mode, we need to use logical apicid instead of physical apicid in x2apic_cpu_mask_to_apicid_and() Impact: fixes the broken interrupt delivery issue on generic x2apic platforms. Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Acked-by: Mike Travis <travis@sgi.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
199 lines
4.5 KiB
C
199 lines
4.5 KiB
C
#include <linux/threads.h>
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#include <linux/cpumask.h>
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#include <linux/string.h>
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#include <linux/kernel.h>
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#include <linux/ctype.h>
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#include <linux/init.h>
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#include <linux/dmar.h>
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#include <asm/smp.h>
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#include <asm/ipi.h>
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#include <asm/genapic.h>
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DEFINE_PER_CPU(u32, x86_cpu_to_logical_apicid);
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static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
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{
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if (cpu_has_x2apic)
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return 1;
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return 0;
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}
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/* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */
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static const struct cpumask *x2apic_target_cpus(void)
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{
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return cpumask_of(0);
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}
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/*
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* for now each logical cpu is in its own vector allocation domain.
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*/
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static void x2apic_vector_allocation_domain(int cpu, struct cpumask *retmask)
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{
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cpumask_clear(retmask);
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cpumask_set_cpu(cpu, retmask);
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}
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static void __x2apic_send_IPI_dest(unsigned int apicid, int vector,
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unsigned int dest)
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{
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unsigned long cfg;
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cfg = __prepare_ICR(0, vector, dest);
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/*
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* send the IPI.
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*/
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x2apic_icr_write(cfg, apicid);
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}
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/*
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* for now, we send the IPI's one by one in the cpumask.
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* TBD: Based on the cpu mask, we can send the IPI's to the cluster group
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* at once. We have 16 cpu's in a cluster. This will minimize IPI register
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* writes.
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*/
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static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector)
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{
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unsigned long flags;
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unsigned long query_cpu;
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local_irq_save(flags);
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for_each_cpu(query_cpu, mask)
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__x2apic_send_IPI_dest(
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per_cpu(x86_cpu_to_logical_apicid, query_cpu),
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vector, APIC_DEST_LOGICAL);
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local_irq_restore(flags);
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}
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static void x2apic_send_IPI_mask_allbutself(const struct cpumask *mask,
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int vector)
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{
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unsigned long flags;
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unsigned long query_cpu;
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unsigned long this_cpu = smp_processor_id();
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local_irq_save(flags);
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for_each_cpu(query_cpu, mask)
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if (query_cpu != this_cpu)
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__x2apic_send_IPI_dest(
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per_cpu(x86_cpu_to_logical_apicid, query_cpu),
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vector, APIC_DEST_LOGICAL);
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local_irq_restore(flags);
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}
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static void x2apic_send_IPI_allbutself(int vector)
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{
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unsigned long flags;
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unsigned long query_cpu;
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unsigned long this_cpu = smp_processor_id();
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local_irq_save(flags);
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for_each_online_cpu(query_cpu)
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if (query_cpu != this_cpu)
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__x2apic_send_IPI_dest(
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per_cpu(x86_cpu_to_logical_apicid, query_cpu),
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vector, APIC_DEST_LOGICAL);
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local_irq_restore(flags);
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}
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static void x2apic_send_IPI_all(int vector)
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{
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x2apic_send_IPI_mask(cpu_online_mask, vector);
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}
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static int x2apic_apic_id_registered(void)
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{
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return 1;
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}
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static unsigned int x2apic_cpu_mask_to_apicid(const struct cpumask *cpumask)
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{
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int cpu;
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/*
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* We're using fixed IRQ delivery, can only return one logical APIC ID.
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* May as well be the first.
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*/
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cpu = cpumask_first(cpumask);
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if ((unsigned)cpu < nr_cpu_ids)
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return per_cpu(x86_cpu_to_logical_apicid, cpu);
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else
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return BAD_APICID;
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}
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static unsigned int x2apic_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
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const struct cpumask *andmask)
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{
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int cpu;
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/*
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* We're using fixed IRQ delivery, can only return one logical APIC ID.
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* May as well be the first.
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*/
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for_each_cpu_and(cpu, cpumask, andmask)
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if (cpumask_test_cpu(cpu, cpu_online_mask))
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break;
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if (cpu < nr_cpu_ids)
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return per_cpu(x86_cpu_to_logical_apicid, cpu);
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return BAD_APICID;
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}
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static unsigned int get_apic_id(unsigned long x)
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{
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unsigned int id;
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id = x;
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return id;
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}
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static unsigned long set_apic_id(unsigned int id)
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{
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unsigned long x;
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x = id;
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return x;
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}
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static unsigned int phys_pkg_id(int index_msb)
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{
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return current_cpu_data.initial_apicid >> index_msb;
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}
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static void x2apic_send_IPI_self(int vector)
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{
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apic_write(APIC_SELF_IPI, vector);
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}
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static void init_x2apic_ldr(void)
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{
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int cpu = smp_processor_id();
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per_cpu(x86_cpu_to_logical_apicid, cpu) = apic_read(APIC_LDR);
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return;
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}
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struct genapic apic_x2apic_cluster = {
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.name = "cluster x2apic",
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.acpi_madt_oem_check = x2apic_acpi_madt_oem_check,
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.int_delivery_mode = dest_LowestPrio,
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.int_dest_mode = (APIC_DEST_LOGICAL != 0),
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.target_cpus = x2apic_target_cpus,
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.vector_allocation_domain = x2apic_vector_allocation_domain,
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.apic_id_registered = x2apic_apic_id_registered,
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.init_apic_ldr = init_x2apic_ldr,
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.send_IPI_all = x2apic_send_IPI_all,
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.send_IPI_allbutself = x2apic_send_IPI_allbutself,
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.send_IPI_mask = x2apic_send_IPI_mask,
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.send_IPI_mask_allbutself = x2apic_send_IPI_mask_allbutself,
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.send_IPI_self = x2apic_send_IPI_self,
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.cpu_mask_to_apicid = x2apic_cpu_mask_to_apicid,
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.cpu_mask_to_apicid_and = x2apic_cpu_mask_to_apicid_and,
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.phys_pkg_id = phys_pkg_id,
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.get_apic_id = get_apic_id,
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.set_apic_id = set_apic_id,
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.apic_id_mask = (0xFFFFFFFFu),
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};
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