![Tim Abbott](/assets/img/avatar_default.png)
This has the consequence of changing the section name use for head code from ".text.head" to ".head.text". Since this commit changes all users in the architecture, this change should be harmless. Signed-off-by: Tim Abbott <tabbott@mit.edu> Cc: Paul Mundt <lethal@linux-sh.org> Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
360 lines
9.3 KiB
ArmAsm
360 lines
9.3 KiB
ArmAsm
/*
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* arch/sh/kernel/head_64.S
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*
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* Copyright (C) 2000, 2001 Paolo Alberelli
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* Copyright (C) 2003, 2004 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <asm/page.h>
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#include <asm/cache.h>
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#include <asm/tlb.h>
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#include <cpu/registers.h>
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#include <cpu/mmu_context.h>
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#include <asm/thread_info.h>
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/*
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* MMU defines: TLB boundaries.
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*/
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#define MMUIR_FIRST ITLB_FIXED
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#define MMUIR_END ITLB_LAST_VAR_UNRESTRICTED+TLB_STEP
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#define MMUIR_STEP TLB_STEP
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#define MMUDR_FIRST DTLB_FIXED
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#define MMUDR_END DTLB_LAST_VAR_UNRESTRICTED+TLB_STEP
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#define MMUDR_STEP TLB_STEP
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/* Safety check : CONFIG_PAGE_OFFSET has to be a multiple of 512Mb */
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#if (CONFIG_PAGE_OFFSET & ((1UL<<29)-1))
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#error "CONFIG_PAGE_OFFSET must be a multiple of 512Mb"
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#endif
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/*
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* MMU defines: Fixed TLBs.
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*/
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/* Deal safely with the case where the base of RAM is not 512Mb aligned */
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#define ALIGN_512M_MASK (0xffffffffe0000000)
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#define ALIGNED_EFFECTIVE ((CONFIG_PAGE_OFFSET + CONFIG_MEMORY_START) & ALIGN_512M_MASK)
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#define ALIGNED_PHYSICAL (CONFIG_MEMORY_START & ALIGN_512M_MASK)
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#define MMUIR_TEXT_H (0x0000000000000003 | ALIGNED_EFFECTIVE)
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/* Enabled, Shared, ASID 0, Eff. Add. 0xA0000000 */
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#define MMUIR_TEXT_L (0x000000000000009a | ALIGNED_PHYSICAL)
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/* 512 Mb, Cacheable, Write-back, execute, Not User, Ph. Add. */
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#define MMUDR_CACHED_H 0x0000000000000003 | ALIGNED_EFFECTIVE
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/* Enabled, Shared, ASID 0, Eff. Add. 0xA0000000 */
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#define MMUDR_CACHED_L 0x000000000000015a | ALIGNED_PHYSICAL
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/* 512 Mb, Cacheable, Write-back, read/write, Not User, Ph. Add. */
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#ifdef CONFIG_CACHE_OFF
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#define ICCR0_INIT_VAL ICCR0_OFF /* ICACHE off */
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#else
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#define ICCR0_INIT_VAL ICCR0_ON | ICCR0_ICI /* ICE + ICI */
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#endif
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#define ICCR1_INIT_VAL ICCR1_NOLOCK /* No locking */
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#if defined (CONFIG_CACHE_OFF)
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#define OCCR0_INIT_VAL OCCR0_OFF /* D-cache: off */
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#elif defined (CONFIG_CACHE_WRITETHROUGH)
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#define OCCR0_INIT_VAL OCCR0_ON | OCCR0_OCI | OCCR0_WT /* D-cache: on, */
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/* WT, invalidate */
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#elif defined (CONFIG_CACHE_WRITEBACK)
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#define OCCR0_INIT_VAL OCCR0_ON | OCCR0_OCI | OCCR0_WB /* D-cache: on, */
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/* WB, invalidate */
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#else
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#error preprocessor flag CONFIG_CACHE_... not recognized!
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#endif
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#define OCCR1_INIT_VAL OCCR1_NOLOCK /* No locking */
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.section .empty_zero_page, "aw"
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.global empty_zero_page
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empty_zero_page:
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.long 1 /* MOUNT_ROOT_RDONLY */
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.long 0 /* RAMDISK_FLAGS */
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.long 0x0200 /* ORIG_ROOT_DEV */
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.long 1 /* LOADER_TYPE */
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.long 0x00800000 /* INITRD_START */
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.long 0x00800000 /* INITRD_SIZE */
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.long 0
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.text
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.balign 4096,0,4096
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.section .data, "aw"
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.balign PAGE_SIZE
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.section .data, "aw"
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.balign PAGE_SIZE
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.global mmu_pdtp_cache
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mmu_pdtp_cache:
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.space PAGE_SIZE, 0
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.global empty_bad_page
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empty_bad_page:
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.space PAGE_SIZE, 0
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.global empty_bad_pte_table
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empty_bad_pte_table:
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.space PAGE_SIZE, 0
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.global fpu_in_use
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fpu_in_use: .quad 0
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__HEAD
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.balign L1_CACHE_BYTES
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/*
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* Condition at the entry of __stext:
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* . Reset state:
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* . SR.FD = 1 (FPU disabled)
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* . SR.BL = 1 (Exceptions disabled)
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* . SR.MD = 1 (Privileged Mode)
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* . SR.MMU = 0 (MMU Disabled)
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* . SR.CD = 0 (CTC User Visible)
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* . SR.IMASK = Undefined (Interrupt Mask)
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*
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* Operations supposed to be performed by __stext:
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* . prevent speculative fetch onto device memory while MMU is off
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* . reflect as much as possible SH5 ABI (r15, r26, r27, r18)
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* . first, save CPU state and set it to something harmless
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* . any CPU detection and/or endianness settings (?)
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* . initialize EMI/LMI (but not TMU/RTC/INTC/SCIF): TBD
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* . set initial TLB entries for cached and uncached regions
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* (no fine granularity paging)
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* . set initial cache state
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* . enable MMU and caches
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* . set CPU to a consistent state
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* . registers (including stack pointer and current/KCR0)
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* . NOT expecting to set Exception handling nor VBR/RESVEC/DCR
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* at this stage. This is all to later Linux initialization steps.
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* . initialize FPU
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* . clear BSS
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* . jump into start_kernel()
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* . be prepared to hopeless start_kernel() returns.
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*
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*/
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.global _stext
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_stext:
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/*
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* Prevent speculative fetch on device memory due to
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* uninitialized target registers.
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*/
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ptabs/u ZERO, tr0
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ptabs/u ZERO, tr1
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ptabs/u ZERO, tr2
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ptabs/u ZERO, tr3
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ptabs/u ZERO, tr4
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ptabs/u ZERO, tr5
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ptabs/u ZERO, tr6
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ptabs/u ZERO, tr7
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synci
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/*
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* Read/Set CPU state. After this block:
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* r29 = Initial SR
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*/
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getcon SR, r29
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movi SR_HARMLESS, r20
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putcon r20, SR
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/*
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* Initialize EMI/LMI. To Be Done.
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*/
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/*
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* CPU detection and/or endianness settings (?). To Be Done.
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* Pure PIC code here, please ! Just save state into r30.
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* After this block:
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* r30 = CPU type/Platform Endianness
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*/
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/*
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* Set initial TLB entries for cached and uncached regions.
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* Note: PTA/BLINK is PIC code, PTABS/BLINK isn't !
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*/
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/* Clear ITLBs */
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pta clear_ITLB, tr1
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movi MMUIR_FIRST, r21
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movi MMUIR_END, r22
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clear_ITLB:
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putcfg r21, 0, ZERO /* Clear MMUIR[n].PTEH.V */
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addi r21, MMUIR_STEP, r21
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bne r21, r22, tr1
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/* Clear DTLBs */
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pta clear_DTLB, tr1
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movi MMUDR_FIRST, r21
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movi MMUDR_END, r22
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clear_DTLB:
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putcfg r21, 0, ZERO /* Clear MMUDR[n].PTEH.V */
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addi r21, MMUDR_STEP, r21
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bne r21, r22, tr1
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/* Map one big (512Mb) page for ITLB */
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movi MMUIR_FIRST, r21
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movi MMUIR_TEXT_L, r22 /* PTEL first */
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add.l r22, r63, r22 /* Sign extend */
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putcfg r21, 1, r22 /* Set MMUIR[0].PTEL */
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movi MMUIR_TEXT_H, r22 /* PTEH last */
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add.l r22, r63, r22 /* Sign extend */
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putcfg r21, 0, r22 /* Set MMUIR[0].PTEH */
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/* Map one big CACHED (512Mb) page for DTLB */
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movi MMUDR_FIRST, r21
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movi MMUDR_CACHED_L, r22 /* PTEL first */
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add.l r22, r63, r22 /* Sign extend */
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putcfg r21, 1, r22 /* Set MMUDR[0].PTEL */
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movi MMUDR_CACHED_H, r22 /* PTEH last */
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add.l r22, r63, r22 /* Sign extend */
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putcfg r21, 0, r22 /* Set MMUDR[0].PTEH */
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#ifdef CONFIG_EARLY_PRINTK
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/*
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* Setup a DTLB translation for SCIF phys.
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*/
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addi r21, MMUDR_STEP, r21
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movi 0x0a03, r22 /* SCIF phys */
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shori 0x0148, r22
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putcfg r21, 1, r22 /* PTEL first */
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movi 0xfa03, r22 /* 0xfa030000, fixed SCIF virt */
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shori 0x0003, r22
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putcfg r21, 0, r22 /* PTEH last */
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#endif
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/*
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* Set cache behaviours.
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*/
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/* ICache */
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movi ICCR_BASE, r21
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movi ICCR0_INIT_VAL, r22
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movi ICCR1_INIT_VAL, r23
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putcfg r21, ICCR_REG0, r22
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putcfg r21, ICCR_REG1, r23
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/* OCache */
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movi OCCR_BASE, r21
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movi OCCR0_INIT_VAL, r22
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movi OCCR1_INIT_VAL, r23
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putcfg r21, OCCR_REG0, r22
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putcfg r21, OCCR_REG1, r23
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/*
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* Enable Caches and MMU. Do the first non-PIC jump.
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* Now head.S global variables, constants and externs
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* can be used.
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*/
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getcon SR, r21
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movi SR_ENABLE_MMU, r22
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or r21, r22, r21
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putcon r21, SSR
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movi hyperspace, r22
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ori r22, 1, r22 /* Make it SHmedia, not required but..*/
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putcon r22, SPC
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synco
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rte /* And now go into the hyperspace ... */
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hyperspace: /* ... that's the next instruction ! */
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/*
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* Set CPU to a consistent state.
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* r31 = FPU support flag
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* tr0/tr7 in use. Others give a chance to loop somewhere safe
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*/
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movi start_kernel, r32
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ori r32, 1, r32
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ptabs r32, tr0 /* r32 = _start_kernel address */
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pta/u hopeless, tr1
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pta/u hopeless, tr2
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pta/u hopeless, tr3
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pta/u hopeless, tr4
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pta/u hopeless, tr5
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pta/u hopeless, tr6
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pta/u hopeless, tr7
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gettr tr1, r28 /* r28 = hopeless address */
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/* Set initial stack pointer */
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movi init_thread_union, SP
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putcon SP, KCR0 /* Set current to init_task */
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movi THREAD_SIZE, r22 /* Point to the end */
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add SP, r22, SP
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/*
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* Initialize FPU.
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* Keep FPU flag in r31. After this block:
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* r31 = FPU flag
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*/
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movi fpu_in_use, r31 /* Temporary */
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#ifdef CONFIG_SH_FPU
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getcon SR, r21
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movi SR_ENABLE_FPU, r22
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and r21, r22, r22
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putcon r22, SR /* Try to enable */
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getcon SR, r22
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xor r21, r22, r21
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shlri r21, 15, r21 /* Supposedly 0/1 */
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st.q r31, 0 , r21 /* Set fpu_in_use */
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#else
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movi 0, r21
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st.q r31, 0 , r21 /* Set fpu_in_use */
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#endif
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or r21, ZERO, r31 /* Set FPU flag at last */
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#ifndef CONFIG_SH_NO_BSS_INIT
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/* Don't clear BSS if running on slow platforms such as an RTL simulation,
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remote memory via SHdebug link, etc. For these the memory can be guaranteed
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to be all zero on boot anyway. */
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/*
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* Clear bss
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*/
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pta clear_quad, tr1
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movi __bss_start, r22
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movi _end, r23
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clear_quad:
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st.q r22, 0, ZERO
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addi r22, 8, r22
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bne r22, r23, tr1 /* Both quad aligned, see vmlinux.lds.S */
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#endif
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pta/u hopeless, tr1
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/* Say bye to head.S but be prepared to wrongly get back ... */
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blink tr0, LINK
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/* If we ever get back here through LINK/tr1-tr7 */
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pta/u hopeless, tr7
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hopeless:
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/*
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* Something's badly wrong here. Loop endlessly,
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* there's nothing more we can do about it.
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*
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* Note on hopeless: it can be jumped into invariably
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* before or after jumping into hyperspace. The only
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* requirement is to be PIC called (PTA) before and
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* any way (PTA/PTABS) after. According to Virtual
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* to Physical mapping a simulator/emulator can easily
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* tell where we came here from just looking at hopeless
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* (PC) address.
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*
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* For debugging purposes:
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* (r28) hopeless/loop address
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* (r29) Original SR
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* (r30) CPU type/Platform endianness
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* (r31) FPU Support
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* (r32) _start_kernel address
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*/
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blink tr7, ZERO
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