![Dmitri Vorobiev](/assets/img/avatar_default.png)
The variable cpu_callin_map is needlessly defined global, so let's make it static now. Build-tested using malta_defconfig. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@movial.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
409 lines
9.5 KiB
C
409 lines
9.5 KiB
C
/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) 2000, 2001 Kanoj Sarcar
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* Copyright (C) 2000, 2001 Ralf Baechle
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* Copyright (C) 2000, 2001 Silicon Graphics, Inc.
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* Copyright (C) 2000, 2001, 2003 Broadcom Corporation
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*/
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#include <linux/cache.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/threads.h>
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#include <linux/module.h>
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#include <linux/time.h>
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#include <linux/timex.h>
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#include <linux/sched.h>
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#include <linux/cpumask.h>
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#include <linux/cpu.h>
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#include <linux/err.h>
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#include <asm/atomic.h>
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#include <asm/cpu.h>
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#include <asm/processor.h>
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#include <asm/r4k-timer.h>
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#include <asm/system.h>
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#include <asm/mmu_context.h>
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#include <asm/time.h>
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#ifdef CONFIG_MIPS_MT_SMTC
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#include <asm/mipsmtregs.h>
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#endif /* CONFIG_MIPS_MT_SMTC */
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static volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */
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int __cpu_number_map[NR_CPUS]; /* Map physical to logical */
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int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */
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extern void cpu_idle(void);
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/* Number of TCs (or siblings in Intel speak) per CPU core */
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int smp_num_siblings = 1;
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EXPORT_SYMBOL(smp_num_siblings);
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/* representing the TCs (or siblings in Intel speak) of each logical CPU */
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cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
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EXPORT_SYMBOL(cpu_sibling_map);
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/* representing cpus for which sibling maps can be computed */
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static cpumask_t cpu_sibling_setup_map;
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static inline void set_cpu_sibling_map(int cpu)
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{
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int i;
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cpu_set(cpu, cpu_sibling_setup_map);
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if (smp_num_siblings > 1) {
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for_each_cpu_mask(i, cpu_sibling_setup_map) {
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if (cpu_data[cpu].core == cpu_data[i].core) {
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cpu_set(i, cpu_sibling_map[cpu]);
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cpu_set(cpu, cpu_sibling_map[i]);
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}
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}
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} else
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cpu_set(cpu, cpu_sibling_map[cpu]);
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}
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struct plat_smp_ops *mp_ops;
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__cpuinit void register_smp_ops(struct plat_smp_ops *ops)
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{
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if (mp_ops)
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printk(KERN_WARNING "Overriding previously set SMP ops\n");
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mp_ops = ops;
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}
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/*
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* First C code run on the secondary CPUs after being started up by
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* the master.
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*/
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asmlinkage __cpuinit void start_secondary(void)
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{
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unsigned int cpu;
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#ifdef CONFIG_MIPS_MT_SMTC
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/* Only do cpu_probe for first TC of CPU */
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if ((read_c0_tcbind() & TCBIND_CURTC) == 0)
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#endif /* CONFIG_MIPS_MT_SMTC */
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cpu_probe();
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cpu_report();
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per_cpu_trap_init();
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mips_clockevent_init();
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mp_ops->init_secondary();
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/*
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* XXX parity protection should be folded in here when it's converted
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* to an option instead of something based on .cputype
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*/
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calibrate_delay();
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preempt_disable();
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cpu = smp_processor_id();
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cpu_data[cpu].udelay_val = loops_per_jiffy;
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notify_cpu_starting(cpu);
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mp_ops->smp_finish();
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set_cpu_sibling_map(cpu);
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cpu_set(cpu, cpu_callin_map);
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synchronise_count_slave();
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cpu_idle();
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}
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void arch_send_call_function_ipi(cpumask_t mask)
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{
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mp_ops->send_ipi_mask(mask, SMP_CALL_FUNCTION);
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}
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/*
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* We reuse the same vector for the single IPI
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*/
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void arch_send_call_function_single_ipi(int cpu)
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{
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mp_ops->send_ipi_mask(cpumask_of_cpu(cpu), SMP_CALL_FUNCTION);
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}
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/*
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* Call into both interrupt handlers, as we share the IPI for them
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*/
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void smp_call_function_interrupt(void)
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{
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irq_enter();
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generic_smp_call_function_single_interrupt();
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generic_smp_call_function_interrupt();
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irq_exit();
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}
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static void stop_this_cpu(void *dummy)
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{
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/*
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* Remove this CPU:
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*/
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cpu_clear(smp_processor_id(), cpu_online_map);
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for (;;) {
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if (cpu_wait)
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(*cpu_wait)(); /* Wait if available. */
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}
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}
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void smp_send_stop(void)
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{
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smp_call_function(stop_this_cpu, NULL, 0);
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}
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void __init smp_cpus_done(unsigned int max_cpus)
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{
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mp_ops->cpus_done();
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synchronise_count_master();
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}
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/* called from main before smp_init() */
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void __init smp_prepare_cpus(unsigned int max_cpus)
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{
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init_new_context(current, &init_mm);
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current_thread_info()->cpu = 0;
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mp_ops->prepare_cpus(max_cpus);
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set_cpu_sibling_map(0);
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#ifndef CONFIG_HOTPLUG_CPU
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cpu_present_map = cpu_possible_map;
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#endif
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}
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/* preload SMP state for boot cpu */
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void __devinit smp_prepare_boot_cpu(void)
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{
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cpu_set(0, cpu_possible_map);
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cpu_set(0, cpu_online_map);
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cpu_set(0, cpu_callin_map);
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}
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/*
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* Called once for each "cpu_possible(cpu)". Needs to spin up the cpu
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* and keep control until "cpu_online(cpu)" is set. Note: cpu is
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* physical, not logical.
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*/
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int __cpuinit __cpu_up(unsigned int cpu)
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{
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struct task_struct *idle;
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/*
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* Processor goes to start_secondary(), sets online flag
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* The following code is purely to make sure
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* Linux can schedule processes on this slave.
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*/
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idle = fork_idle(cpu);
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if (IS_ERR(idle))
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panic(KERN_ERR "Fork failed for CPU %d", cpu);
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mp_ops->boot_secondary(cpu, idle);
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/*
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* Trust is futile. We should really have timeouts ...
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*/
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while (!cpu_isset(cpu, cpu_callin_map))
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udelay(100);
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cpu_set(cpu, cpu_online_map);
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return 0;
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}
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/* Not really SMP stuff ... */
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int setup_profiling_timer(unsigned int multiplier)
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{
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return 0;
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}
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static void flush_tlb_all_ipi(void *info)
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{
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local_flush_tlb_all();
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}
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void flush_tlb_all(void)
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{
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on_each_cpu(flush_tlb_all_ipi, NULL, 1);
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}
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static void flush_tlb_mm_ipi(void *mm)
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{
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local_flush_tlb_mm((struct mm_struct *)mm);
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}
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/*
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* Special Variant of smp_call_function for use by TLB functions:
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*
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* o No return value
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* o collapses to normal function call on UP kernels
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* o collapses to normal function call on systems with a single shared
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* primary cache.
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* o CONFIG_MIPS_MT_SMTC currently implies there is only one physical core.
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*/
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static inline void smp_on_other_tlbs(void (*func) (void *info), void *info)
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{
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#ifndef CONFIG_MIPS_MT_SMTC
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smp_call_function(func, info, 1);
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#endif
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}
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static inline void smp_on_each_tlb(void (*func) (void *info), void *info)
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{
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preempt_disable();
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smp_on_other_tlbs(func, info);
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func(info);
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preempt_enable();
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}
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/*
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* The following tlb flush calls are invoked when old translations are
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* being torn down, or pte attributes are changing. For single threaded
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* address spaces, a new context is obtained on the current cpu, and tlb
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* context on other cpus are invalidated to force a new context allocation
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* at switch_mm time, should the mm ever be used on other cpus. For
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* multithreaded address spaces, intercpu interrupts have to be sent.
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* Another case where intercpu interrupts are required is when the target
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* mm might be active on another cpu (eg debuggers doing the flushes on
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* behalf of debugees, kswapd stealing pages from another process etc).
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* Kanoj 07/00.
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*/
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void flush_tlb_mm(struct mm_struct *mm)
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{
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preempt_disable();
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if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
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smp_on_other_tlbs(flush_tlb_mm_ipi, mm);
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} else {
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cpumask_t mask = cpu_online_map;
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unsigned int cpu;
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cpu_clear(smp_processor_id(), mask);
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for_each_cpu_mask(cpu, mask)
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if (cpu_context(cpu, mm))
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cpu_context(cpu, mm) = 0;
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}
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local_flush_tlb_mm(mm);
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preempt_enable();
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}
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struct flush_tlb_data {
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struct vm_area_struct *vma;
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unsigned long addr1;
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unsigned long addr2;
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};
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static void flush_tlb_range_ipi(void *info)
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{
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struct flush_tlb_data *fd = info;
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local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2);
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}
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void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
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{
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struct mm_struct *mm = vma->vm_mm;
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preempt_disable();
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if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
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struct flush_tlb_data fd = {
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.vma = vma,
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.addr1 = start,
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.addr2 = end,
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};
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smp_on_other_tlbs(flush_tlb_range_ipi, &fd);
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} else {
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cpumask_t mask = cpu_online_map;
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unsigned int cpu;
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cpu_clear(smp_processor_id(), mask);
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for_each_cpu_mask(cpu, mask)
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if (cpu_context(cpu, mm))
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cpu_context(cpu, mm) = 0;
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}
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local_flush_tlb_range(vma, start, end);
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preempt_enable();
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}
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static void flush_tlb_kernel_range_ipi(void *info)
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{
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struct flush_tlb_data *fd = info;
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local_flush_tlb_kernel_range(fd->addr1, fd->addr2);
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}
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void flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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struct flush_tlb_data fd = {
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.addr1 = start,
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.addr2 = end,
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};
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on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1);
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}
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static void flush_tlb_page_ipi(void *info)
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{
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struct flush_tlb_data *fd = info;
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local_flush_tlb_page(fd->vma, fd->addr1);
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}
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void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
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{
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preempt_disable();
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if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) {
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struct flush_tlb_data fd = {
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.vma = vma,
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.addr1 = page,
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};
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smp_on_other_tlbs(flush_tlb_page_ipi, &fd);
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} else {
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cpumask_t mask = cpu_online_map;
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unsigned int cpu;
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cpu_clear(smp_processor_id(), mask);
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for_each_cpu_mask(cpu, mask)
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if (cpu_context(cpu, vma->vm_mm))
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cpu_context(cpu, vma->vm_mm) = 0;
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}
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local_flush_tlb_page(vma, page);
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preempt_enable();
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}
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static void flush_tlb_one_ipi(void *info)
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{
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unsigned long vaddr = (unsigned long) info;
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local_flush_tlb_one(vaddr);
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}
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void flush_tlb_one(unsigned long vaddr)
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{
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smp_on_each_tlb(flush_tlb_one_ipi, (void *) vaddr);
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}
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EXPORT_SYMBOL(flush_tlb_page);
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EXPORT_SYMBOL(flush_tlb_one);
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