![David Daney](/assets/img/avatar_default.png)
This is the final part of the watch register patch. Here we hook up ptrace so that the user space debugger (gdb), can set and read the registers. Signed-off-by: David Daney <ddaney@avtrex.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
602 lines
14 KiB
C
602 lines
14 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1992 Ross Biro
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* Copyright (C) Linus Torvalds
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* Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle
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* Copyright (C) 1996 David S. Miller
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* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 1999 MIPS Technologies, Inc.
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* Copyright (C) 2000 Ulf Carlsson
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*
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* At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit
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* binaries.
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*/
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#include <linux/compiler.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <linux/errno.h>
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#include <linux/ptrace.h>
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#include <linux/smp.h>
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#include <linux/user.h>
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#include <linux/security.h>
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#include <linux/audit.h>
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#include <linux/seccomp.h>
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#include <asm/byteorder.h>
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#include <asm/cpu.h>
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#include <asm/dsp.h>
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#include <asm/fpu.h>
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#include <asm/mipsregs.h>
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#include <asm/mipsmtregs.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/system.h>
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#include <asm/uaccess.h>
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#include <asm/bootinfo.h>
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#include <asm/reg.h>
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/*
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* Called by kernel/ptrace.c when detaching..
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*
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* Make sure single step bits etc are not set.
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*/
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void ptrace_disable(struct task_struct *child)
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{
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/* Don't load the watchpoint registers for the ex-child. */
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clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
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}
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/*
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* Read a general register set. We always use the 64-bit format, even
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* for 32-bit kernels and for 32-bit processes on a 64-bit kernel.
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* Registers are sign extended to fill the available space.
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*/
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int ptrace_getregs(struct task_struct *child, __s64 __user *data)
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{
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struct pt_regs *regs;
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int i;
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if (!access_ok(VERIFY_WRITE, data, 38 * 8))
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return -EIO;
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regs = task_pt_regs(child);
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for (i = 0; i < 32; i++)
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__put_user((long)regs->regs[i], data + i);
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__put_user((long)regs->lo, data + EF_LO - EF_R0);
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__put_user((long)regs->hi, data + EF_HI - EF_R0);
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__put_user((long)regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
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__put_user((long)regs->cp0_badvaddr, data + EF_CP0_BADVADDR - EF_R0);
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__put_user((long)regs->cp0_status, data + EF_CP0_STATUS - EF_R0);
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__put_user((long)regs->cp0_cause, data + EF_CP0_CAUSE - EF_R0);
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return 0;
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}
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/*
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* Write a general register set. As for PTRACE_GETREGS, we always use
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* the 64-bit format. On a 32-bit kernel only the lower order half
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* (according to endianness) will be used.
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*/
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int ptrace_setregs(struct task_struct *child, __s64 __user *data)
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{
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struct pt_regs *regs;
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int i;
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if (!access_ok(VERIFY_READ, data, 38 * 8))
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return -EIO;
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regs = task_pt_regs(child);
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for (i = 0; i < 32; i++)
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__get_user(regs->regs[i], data + i);
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__get_user(regs->lo, data + EF_LO - EF_R0);
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__get_user(regs->hi, data + EF_HI - EF_R0);
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__get_user(regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
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/* badvaddr, status, and cause may not be written. */
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return 0;
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}
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int ptrace_getfpregs(struct task_struct *child, __u32 __user *data)
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{
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int i;
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unsigned int tmp;
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if (!access_ok(VERIFY_WRITE, data, 33 * 8))
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return -EIO;
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if (tsk_used_math(child)) {
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fpureg_t *fregs = get_fpu_regs(child);
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for (i = 0; i < 32; i++)
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__put_user(fregs[i], i + (__u64 __user *) data);
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} else {
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for (i = 0; i < 32; i++)
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__put_user((__u64) -1, i + (__u64 __user *) data);
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}
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__put_user(child->thread.fpu.fcr31, data + 64);
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preempt_disable();
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if (cpu_has_fpu) {
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unsigned int flags;
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if (cpu_has_mipsmt) {
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unsigned int vpflags = dvpe();
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flags = read_c0_status();
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__enable_fpu();
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__asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
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write_c0_status(flags);
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evpe(vpflags);
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} else {
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flags = read_c0_status();
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__enable_fpu();
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__asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
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write_c0_status(flags);
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}
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} else {
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tmp = 0;
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}
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preempt_enable();
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__put_user(tmp, data + 65);
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return 0;
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}
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int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
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{
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fpureg_t *fregs;
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int i;
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if (!access_ok(VERIFY_READ, data, 33 * 8))
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return -EIO;
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fregs = get_fpu_regs(child);
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for (i = 0; i < 32; i++)
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__get_user(fregs[i], i + (__u64 __user *) data);
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__get_user(child->thread.fpu.fcr31, data + 64);
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/* FIR may not be written. */
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return 0;
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}
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int ptrace_get_watch_regs(struct task_struct *child,
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struct pt_watch_regs __user *addr)
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{
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enum pt_watch_style style;
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int i;
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if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt == 0)
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return -EIO;
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if (!access_ok(VERIFY_WRITE, addr, sizeof(struct pt_watch_regs)))
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return -EIO;
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#ifdef CONFIG_32BIT
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style = pt_watch_style_mips32;
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#define WATCH_STYLE mips32
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#else
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style = pt_watch_style_mips64;
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#define WATCH_STYLE mips64
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#endif
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__put_user(style, &addr->style);
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__put_user(current_cpu_data.watch_reg_use_cnt,
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&addr->WATCH_STYLE.num_valid);
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for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
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__put_user(child->thread.watch.mips3264.watchlo[i],
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&addr->WATCH_STYLE.watchlo[i]);
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__put_user(child->thread.watch.mips3264.watchhi[i] & 0xfff,
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&addr->WATCH_STYLE.watchhi[i]);
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__put_user(current_cpu_data.watch_reg_masks[i],
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&addr->WATCH_STYLE.watch_masks[i]);
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}
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for (; i < 8; i++) {
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__put_user(0, &addr->WATCH_STYLE.watchlo[i]);
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__put_user(0, &addr->WATCH_STYLE.watchhi[i]);
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__put_user(0, &addr->WATCH_STYLE.watch_masks[i]);
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}
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return 0;
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}
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int ptrace_set_watch_regs(struct task_struct *child,
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struct pt_watch_regs __user *addr)
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{
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int i;
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int watch_active = 0;
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unsigned long lt[NUM_WATCH_REGS];
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u16 ht[NUM_WATCH_REGS];
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if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt == 0)
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return -EIO;
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if (!access_ok(VERIFY_READ, addr, sizeof(struct pt_watch_regs)))
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return -EIO;
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/* Check the values. */
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for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
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__get_user(lt[i], &addr->WATCH_STYLE.watchlo[i]);
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#ifdef CONFIG_32BIT
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if (lt[i] & __UA_LIMIT)
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return -EINVAL;
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#else
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if (test_tsk_thread_flag(child, TIF_32BIT_ADDR)) {
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if (lt[i] & 0xffffffff80000000UL)
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return -EINVAL;
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} else {
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if (lt[i] & __UA_LIMIT)
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return -EINVAL;
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}
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#endif
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__get_user(ht[i], &addr->WATCH_STYLE.watchhi[i]);
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if (ht[i] & ~0xff8)
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return -EINVAL;
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}
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/* Install them. */
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for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
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if (lt[i] & 7)
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watch_active = 1;
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child->thread.watch.mips3264.watchlo[i] = lt[i];
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/* Set the G bit. */
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child->thread.watch.mips3264.watchhi[i] = ht[i];
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}
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if (watch_active)
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set_tsk_thread_flag(child, TIF_LOAD_WATCH);
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else
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clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
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return 0;
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}
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long arch_ptrace(struct task_struct *child, long request, long addr, long data)
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{
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int ret;
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switch (request) {
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/* when I and D space are separate, these will need to be fixed. */
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case PTRACE_PEEKTEXT: /* read word at location addr. */
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case PTRACE_PEEKDATA:
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ret = generic_ptrace_peekdata(child, addr, data);
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break;
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/* Read the word at location addr in the USER area. */
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case PTRACE_PEEKUSR: {
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struct pt_regs *regs;
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unsigned long tmp = 0;
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regs = task_pt_regs(child);
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ret = 0; /* Default return value. */
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switch (addr) {
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case 0 ... 31:
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tmp = regs->regs[addr];
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break;
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case FPR_BASE ... FPR_BASE + 31:
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if (tsk_used_math(child)) {
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fpureg_t *fregs = get_fpu_regs(child);
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#ifdef CONFIG_32BIT
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/*
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* The odd registers are actually the high
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* order bits of the values stored in the even
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* registers - unless we're using r2k_switch.S.
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*/
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if (addr & 1)
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tmp = (unsigned long) (fregs[((addr & ~1) - 32)] >> 32);
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else
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tmp = (unsigned long) (fregs[(addr - 32)] & 0xffffffff);
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#endif
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#ifdef CONFIG_64BIT
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tmp = fregs[addr - FPR_BASE];
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#endif
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} else {
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tmp = -1; /* FP not yet used */
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}
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break;
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case PC:
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tmp = regs->cp0_epc;
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break;
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case CAUSE:
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tmp = regs->cp0_cause;
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break;
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case BADVADDR:
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tmp = regs->cp0_badvaddr;
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break;
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case MMHI:
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tmp = regs->hi;
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break;
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case MMLO:
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tmp = regs->lo;
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break;
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#ifdef CONFIG_CPU_HAS_SMARTMIPS
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case ACX:
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tmp = regs->acx;
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break;
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#endif
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case FPC_CSR:
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tmp = child->thread.fpu.fcr31;
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break;
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case FPC_EIR: { /* implementation / version register */
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unsigned int flags;
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#ifdef CONFIG_MIPS_MT_SMTC
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unsigned long irqflags;
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unsigned int mtflags;
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#endif /* CONFIG_MIPS_MT_SMTC */
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preempt_disable();
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if (!cpu_has_fpu) {
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preempt_enable();
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break;
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}
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#ifdef CONFIG_MIPS_MT_SMTC
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/* Read-modify-write of Status must be atomic */
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local_irq_save(irqflags);
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mtflags = dmt();
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#endif /* CONFIG_MIPS_MT_SMTC */
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if (cpu_has_mipsmt) {
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unsigned int vpflags = dvpe();
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flags = read_c0_status();
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__enable_fpu();
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__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
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write_c0_status(flags);
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evpe(vpflags);
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} else {
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flags = read_c0_status();
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__enable_fpu();
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__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
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write_c0_status(flags);
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}
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#ifdef CONFIG_MIPS_MT_SMTC
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emt(mtflags);
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local_irq_restore(irqflags);
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#endif /* CONFIG_MIPS_MT_SMTC */
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preempt_enable();
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break;
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}
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case DSP_BASE ... DSP_BASE + 5: {
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dspreg_t *dregs;
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if (!cpu_has_dsp) {
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tmp = 0;
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ret = -EIO;
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goto out;
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}
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dregs = __get_dsp_regs(child);
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tmp = (unsigned long) (dregs[addr - DSP_BASE]);
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break;
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}
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case DSP_CONTROL:
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if (!cpu_has_dsp) {
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tmp = 0;
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ret = -EIO;
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goto out;
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}
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tmp = child->thread.dsp.dspcontrol;
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break;
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default:
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tmp = 0;
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ret = -EIO;
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goto out;
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}
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ret = put_user(tmp, (unsigned long __user *) data);
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break;
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}
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/* when I and D space are separate, this will have to be fixed. */
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case PTRACE_POKETEXT: /* write the word at location addr. */
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case PTRACE_POKEDATA:
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ret = generic_ptrace_pokedata(child, addr, data);
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break;
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case PTRACE_POKEUSR: {
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struct pt_regs *regs;
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ret = 0;
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regs = task_pt_regs(child);
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switch (addr) {
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case 0 ... 31:
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regs->regs[addr] = data;
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break;
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case FPR_BASE ... FPR_BASE + 31: {
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fpureg_t *fregs = get_fpu_regs(child);
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if (!tsk_used_math(child)) {
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/* FP not yet used */
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memset(&child->thread.fpu, ~0,
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sizeof(child->thread.fpu));
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child->thread.fpu.fcr31 = 0;
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}
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#ifdef CONFIG_32BIT
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/*
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* The odd registers are actually the high order bits
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* of the values stored in the even registers - unless
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* we're using r2k_switch.S.
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*/
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if (addr & 1) {
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fregs[(addr & ~1) - FPR_BASE] &= 0xffffffff;
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fregs[(addr & ~1) - FPR_BASE] |= ((unsigned long long) data) << 32;
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} else {
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fregs[addr - FPR_BASE] &= ~0xffffffffLL;
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fregs[addr - FPR_BASE] |= data;
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}
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#endif
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#ifdef CONFIG_64BIT
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fregs[addr - FPR_BASE] = data;
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#endif
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break;
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}
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case PC:
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regs->cp0_epc = data;
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break;
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case MMHI:
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regs->hi = data;
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break;
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case MMLO:
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regs->lo = data;
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break;
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#ifdef CONFIG_CPU_HAS_SMARTMIPS
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case ACX:
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regs->acx = data;
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break;
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#endif
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case FPC_CSR:
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child->thread.fpu.fcr31 = data;
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break;
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case DSP_BASE ... DSP_BASE + 5: {
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dspreg_t *dregs;
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if (!cpu_has_dsp) {
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ret = -EIO;
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break;
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}
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dregs = __get_dsp_regs(child);
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dregs[addr - DSP_BASE] = data;
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break;
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}
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case DSP_CONTROL:
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if (!cpu_has_dsp) {
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ret = -EIO;
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break;
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}
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child->thread.dsp.dspcontrol = data;
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break;
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default:
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/* The rest are not allowed. */
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ret = -EIO;
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break;
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}
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break;
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}
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case PTRACE_GETREGS:
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ret = ptrace_getregs(child, (__s64 __user *) data);
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break;
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case PTRACE_SETREGS:
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ret = ptrace_setregs(child, (__s64 __user *) data);
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break;
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case PTRACE_GETFPREGS:
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ret = ptrace_getfpregs(child, (__u32 __user *) data);
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break;
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case PTRACE_SETFPREGS:
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ret = ptrace_setfpregs(child, (__u32 __user *) data);
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break;
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case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */
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case PTRACE_CONT: { /* restart after signal. */
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ret = -EIO;
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if (!valid_signal(data))
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break;
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if (request == PTRACE_SYSCALL) {
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set_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
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}
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else {
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clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
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}
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child->exit_code = data;
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wake_up_process(child);
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ret = 0;
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break;
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}
|
|
|
|
/*
|
|
* make the child exit. Best I can do is send it a sigkill.
|
|
* perhaps it should be put in the status that it wants to
|
|
* exit.
|
|
*/
|
|
case PTRACE_KILL:
|
|
ret = 0;
|
|
if (child->exit_state == EXIT_ZOMBIE) /* already dead */
|
|
break;
|
|
child->exit_code = SIGKILL;
|
|
wake_up_process(child);
|
|
break;
|
|
|
|
case PTRACE_GET_THREAD_AREA:
|
|
ret = put_user(task_thread_info(child)->tp_value,
|
|
(unsigned long __user *) data);
|
|
break;
|
|
|
|
case PTRACE_GET_WATCH_REGS:
|
|
ret = ptrace_get_watch_regs(child,
|
|
(struct pt_watch_regs __user *) addr);
|
|
break;
|
|
|
|
case PTRACE_SET_WATCH_REGS:
|
|
ret = ptrace_set_watch_regs(child,
|
|
(struct pt_watch_regs __user *) addr);
|
|
break;
|
|
|
|
default:
|
|
ret = ptrace_request(child, request, addr, data);
|
|
break;
|
|
}
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static inline int audit_arch(void)
|
|
{
|
|
int arch = EM_MIPS;
|
|
#ifdef CONFIG_64BIT
|
|
arch |= __AUDIT_ARCH_64BIT;
|
|
#endif
|
|
#if defined(__LITTLE_ENDIAN)
|
|
arch |= __AUDIT_ARCH_LE;
|
|
#endif
|
|
return arch;
|
|
}
|
|
|
|
/*
|
|
* Notification of system call entry/exit
|
|
* - triggered by current->work.syscall_trace
|
|
*/
|
|
asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit)
|
|
{
|
|
/* do the secure computing check first */
|
|
if (!entryexit)
|
|
secure_computing(regs->regs[0]);
|
|
|
|
if (unlikely(current->audit_context) && entryexit)
|
|
audit_syscall_exit(AUDITSC_RESULT(regs->regs[2]),
|
|
regs->regs[2]);
|
|
|
|
if (!(current->ptrace & PT_PTRACED))
|
|
goto out;
|
|
|
|
if (!test_thread_flag(TIF_SYSCALL_TRACE))
|
|
goto out;
|
|
|
|
/* The 0x80 provides a way for the tracing parent to distinguish
|
|
between a syscall stop and SIGTRAP delivery */
|
|
ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ?
|
|
0x80 : 0));
|
|
|
|
/*
|
|
* this isn't the same as continuing with a signal, but it will do
|
|
* for normal use. strace only continues with a signal if the
|
|
* stopping signal is not SIGTRAP. -brl
|
|
*/
|
|
if (current->exit_code) {
|
|
send_sig(current->exit_code, current, 1);
|
|
current->exit_code = 0;
|
|
}
|
|
|
|
out:
|
|
if (unlikely(current->audit_context) && !entryexit)
|
|
audit_syscall_entry(audit_arch(), regs->regs[0],
|
|
regs->regs[4], regs->regs[5],
|
|
regs->regs[6], regs->regs[7]);
|
|
}
|