![Bartlomiej Zolnierkiewicz](/assets/img/avatar_default.png)
v2: * sparc build fix. (From Stephen Rothwell) Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
575 lines
15 KiB
C
575 lines
15 KiB
C
/*
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* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
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* Copyright (C) 1995-1998 Mark Lord
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* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
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*
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* May be copied or modified under the terms of the GNU General Public License
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/ide.h>
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#include <linux/dma-mapping.h>
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#include <asm/io.h>
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/**
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* ide_setup_pci_baseregs - place a PCI IDE controller native
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* @dev: PCI device of interface to switch native
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* @name: Name of interface
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*
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* We attempt to place the PCI interface into PCI native mode. If
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* we succeed the BARs are ok and the controller is in PCI mode.
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* Returns 0 on success or an errno code.
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*
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* FIXME: if we program the interface and then fail to set the BARS
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* we don't switch it back to legacy mode. Do we actually care ??
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*/
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static int ide_setup_pci_baseregs(struct pci_dev *dev, const char *name)
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{
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u8 progif = 0;
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/*
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* Place both IDE interfaces into PCI "native" mode:
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*/
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if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) ||
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(progif & 5) != 5) {
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if ((progif & 0xa) != 0xa) {
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printk(KERN_INFO "%s: device not capable of full "
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"native PCI mode\n", name);
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return -EOPNOTSUPP;
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}
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printk("%s: placing both ports into native PCI mode\n", name);
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(void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5);
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if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) ||
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(progif & 5) != 5) {
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printk(KERN_ERR "%s: rewrite of PROGIF failed, wanted "
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"0x%04x, got 0x%04x\n",
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name, progif|5, progif);
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return -EOPNOTSUPP;
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}
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}
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return 0;
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}
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#ifdef CONFIG_BLK_DEV_IDEDMA_PCI
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static void ide_pci_clear_simplex(unsigned long dma_base, const char *name)
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{
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u8 dma_stat = inb(dma_base + 2);
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outb(dma_stat & 0x60, dma_base + 2);
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dma_stat = inb(dma_base + 2);
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if (dma_stat & 0x80)
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printk(KERN_INFO "%s: simplex device: DMA forced\n", name);
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}
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/**
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* ide_pci_dma_base - setup BMIBA
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* @hwif: IDE interface
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* @d: IDE port info
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*
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* Fetch the DMA Bus-Master-I/O-Base-Address (BMIBA) from PCI space.
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* Where a device has a partner that is already in DMA mode we check
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* and enforce IDE simplex rules.
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*/
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unsigned long ide_pci_dma_base(ide_hwif_t *hwif, const struct ide_port_info *d)
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{
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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unsigned long dma_base = 0;
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u8 dma_stat = 0;
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if (hwif->host_flags & IDE_HFLAG_MMIO)
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return hwif->dma_base;
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if (hwif->mate && hwif->mate->dma_base) {
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dma_base = hwif->mate->dma_base - (hwif->channel ? 0 : 8);
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} else {
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u8 baridx = (d->host_flags & IDE_HFLAG_CS5520) ? 2 : 4;
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dma_base = pci_resource_start(dev, baridx);
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if (dma_base == 0) {
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printk(KERN_ERR "%s: DMA base is invalid\n", d->name);
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return 0;
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}
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}
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if (hwif->channel)
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dma_base += 8;
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if (d->host_flags & IDE_HFLAG_CS5520)
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goto out;
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if (d->host_flags & IDE_HFLAG_CLEAR_SIMPLEX) {
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ide_pci_clear_simplex(dma_base, d->name);
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goto out;
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}
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/*
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* If the device claims "simplex" DMA, this means that only one of
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* the two interfaces can be trusted with DMA at any point in time
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* (so we should enable DMA only on one of the two interfaces).
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*
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* FIXME: At this point we haven't probed the drives so we can't make
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* the appropriate decision. Really we should defer this problem until
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* we tune the drive then try to grab DMA ownership if we want to be
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* the DMA end. This has to be become dynamic to handle hot-plug.
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*/
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dma_stat = hwif->INB(dma_base + 2);
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if ((dma_stat & 0x80) && hwif->mate && hwif->mate->dma_base) {
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printk(KERN_INFO "%s: simplex device: DMA disabled\n", d->name);
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dma_base = 0;
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}
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out:
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return dma_base;
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}
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EXPORT_SYMBOL_GPL(ide_pci_dma_base);
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/*
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* Set up BM-DMA capability (PnP BIOS should have done this)
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*/
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int ide_pci_set_master(struct pci_dev *dev, const char *name)
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{
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u16 pcicmd;
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pci_read_config_word(dev, PCI_COMMAND, &pcicmd);
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if ((pcicmd & PCI_COMMAND_MASTER) == 0) {
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pci_set_master(dev);
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if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd) ||
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(pcicmd & PCI_COMMAND_MASTER) == 0) {
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printk(KERN_ERR "%s: error updating PCICMD on %s\n",
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name, pci_name(dev));
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return -EIO;
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}
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(ide_pci_set_master);
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#endif /* CONFIG_BLK_DEV_IDEDMA_PCI */
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void ide_setup_pci_noise(struct pci_dev *dev, const struct ide_port_info *d)
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{
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printk(KERN_INFO "%s: IDE controller (0x%04x:0x%04x rev 0x%02x) at "
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" PCI slot %s\n", d->name, dev->vendor, dev->device,
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dev->revision, pci_name(dev));
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}
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EXPORT_SYMBOL_GPL(ide_setup_pci_noise);
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/**
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* ide_pci_enable - do PCI enables
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* @dev: PCI device
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* @d: IDE port info
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*
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* Enable the IDE PCI device. We attempt to enable the device in full
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* but if that fails then we only need IO space. The PCI code should
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* have setup the proper resources for us already for controllers in
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* legacy mode.
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*
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* Returns zero on success or an error code
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*/
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static int ide_pci_enable(struct pci_dev *dev, const struct ide_port_info *d)
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{
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int ret, bars;
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if (pci_enable_device(dev)) {
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ret = pci_enable_device_io(dev);
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if (ret < 0) {
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printk(KERN_WARNING "%s: (ide_setup_pci_device:) "
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"Could not enable device.\n", d->name);
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goto out;
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}
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printk(KERN_WARNING "%s: BIOS configuration fixed.\n", d->name);
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}
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/*
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* assume all devices can do 32-bit DMA for now, we can add
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* a DMA mask field to the struct ide_port_info if we need it
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* (or let lower level driver set the DMA mask)
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*/
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ret = pci_set_dma_mask(dev, DMA_32BIT_MASK);
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if (ret < 0) {
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printk(KERN_ERR "%s: can't set dma mask\n", d->name);
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goto out;
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}
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if (d->host_flags & IDE_HFLAG_SINGLE)
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bars = (1 << 2) - 1;
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else
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bars = (1 << 4) - 1;
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if ((d->host_flags & IDE_HFLAG_NO_DMA) == 0) {
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if (d->host_flags & IDE_HFLAG_CS5520)
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bars |= (1 << 2);
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else
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bars |= (1 << 4);
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}
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ret = pci_request_selected_regions(dev, bars, d->name);
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if (ret < 0)
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printk(KERN_ERR "%s: can't reserve resources\n", d->name);
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out:
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return ret;
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}
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/**
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* ide_pci_configure - configure an unconfigured device
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* @dev: PCI device
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* @d: IDE port info
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*
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* Enable and configure the PCI device we have been passed.
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* Returns zero on success or an error code.
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*/
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static int ide_pci_configure(struct pci_dev *dev, const struct ide_port_info *d)
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{
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u16 pcicmd = 0;
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/*
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* PnP BIOS was *supposed* to have setup this device, but we
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* can do it ourselves, so long as the BIOS has assigned an IRQ
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* (or possibly the device is using a "legacy header" for IRQs).
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* Maybe the user deliberately *disabled* the device,
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* but we'll eventually ignore it again if no drives respond.
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*/
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if (ide_setup_pci_baseregs(dev, d->name) ||
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pci_write_config_word(dev, PCI_COMMAND, pcicmd | PCI_COMMAND_IO)) {
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printk(KERN_INFO "%s: device disabled (BIOS)\n", d->name);
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return -ENODEV;
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}
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if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd)) {
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printk(KERN_ERR "%s: error accessing PCI regs\n", d->name);
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return -EIO;
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}
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if (!(pcicmd & PCI_COMMAND_IO)) {
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printk(KERN_ERR "%s: unable to enable IDE controller\n", d->name);
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return -ENXIO;
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}
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return 0;
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}
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/**
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* ide_pci_check_iomem - check a register is I/O
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* @dev: PCI device
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* @d: IDE port info
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* @bar: BAR number
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*
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* Checks if a BAR is configured and points to MMIO space. If so,
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* return an error code. Otherwise return 0
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*/
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static int ide_pci_check_iomem(struct pci_dev *dev, const struct ide_port_info *d,
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int bar)
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{
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ulong flags = pci_resource_flags(dev, bar);
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/* Unconfigured ? */
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if (!flags || pci_resource_len(dev, bar) == 0)
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return 0;
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/* I/O space */
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if (flags & IORESOURCE_IO)
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return 0;
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/* Bad */
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return -EINVAL;
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}
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/**
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* ide_hwif_configure - configure an IDE interface
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* @dev: PCI device holding interface
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* @d: IDE port info
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* @port: port number
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* @irq: PCI IRQ
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*
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* Perform the initial set up for the hardware interface structure. This
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* is done per interface port rather than per PCI device. There may be
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* more than one port per device.
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*
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* Returns the new hardware interface structure, or NULL on a failure
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*/
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static ide_hwif_t *ide_hwif_configure(struct pci_dev *dev,
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const struct ide_port_info *d,
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unsigned int port, int irq)
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{
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unsigned long ctl = 0, base = 0;
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ide_hwif_t *hwif;
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struct hw_regs_s hw;
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if ((d->host_flags & IDE_HFLAG_ISA_PORTS) == 0) {
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if (ide_pci_check_iomem(dev, d, 2 * port) ||
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ide_pci_check_iomem(dev, d, 2 * port + 1)) {
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printk(KERN_ERR "%s: I/O baseregs (BIOS) are reported "
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"as MEM for port %d!\n", d->name, port);
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return NULL;
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}
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ctl = pci_resource_start(dev, 2*port+1);
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base = pci_resource_start(dev, 2*port);
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} else {
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/* Use default values */
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ctl = port ? 0x374 : 0x3f4;
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base = port ? 0x170 : 0x1f0;
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}
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if (!base || !ctl) {
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printk(KERN_ERR "%s: bad PCI BARs for port %d, skipping\n",
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d->name, port);
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return NULL;
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}
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hwif = ide_find_port_slot(d);
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if (hwif == NULL)
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return NULL;
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memset(&hw, 0, sizeof(hw));
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hw.irq = irq;
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hw.dev = &dev->dev;
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hw.chipset = d->chipset ? d->chipset : ide_pci;
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ide_std_init_ports(&hw, base, ctl | 2);
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ide_init_port_hw(hwif, &hw);
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return hwif;
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}
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#ifdef CONFIG_BLK_DEV_IDEDMA_PCI
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/**
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* ide_hwif_setup_dma - configure DMA interface
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* @hwif: IDE interface
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* @d: IDE port info
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*
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* Set up the DMA base for the interface. Enable the master bits as
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* necessary and attempt to bring the device DMA into a ready to use
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* state
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*/
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int ide_hwif_setup_dma(ide_hwif_t *hwif, const struct ide_port_info *d)
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{
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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if ((d->host_flags & IDE_HFLAG_NO_AUTODMA) == 0 ||
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((dev->class >> 8) == PCI_CLASS_STORAGE_IDE &&
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(dev->class & 0x80))) {
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unsigned long base = ide_pci_dma_base(hwif, d);
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if (base == 0 || ide_pci_set_master(dev, d->name) < 0)
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return -1;
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if (hwif->host_flags & IDE_HFLAG_MMIO)
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printk(KERN_INFO " %s: MMIO-DMA\n", hwif->name);
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else
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printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n",
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hwif->name, base, base + 7);
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hwif->extra_base = base + (hwif->channel ? 8 : 16);
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if (ide_allocate_dma_engine(hwif))
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return -1;
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ide_setup_dma(hwif, base);
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}
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return 0;
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}
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#endif /* CONFIG_BLK_DEV_IDEDMA_PCI */
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/**
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* ide_setup_pci_controller - set up IDE PCI
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* @dev: PCI device
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* @d: IDE port info
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* @noisy: verbose flag
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* @config: returned as 1 if we configured the hardware
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*
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* Set up the PCI and controller side of the IDE interface. This brings
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* up the PCI side of the device, checks that the device is enabled
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* and enables it if need be
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*/
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static int ide_setup_pci_controller(struct pci_dev *dev, const struct ide_port_info *d, int noisy, int *config)
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{
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int ret;
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u16 pcicmd;
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if (noisy)
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ide_setup_pci_noise(dev, d);
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ret = ide_pci_enable(dev, d);
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if (ret < 0)
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goto out;
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ret = pci_read_config_word(dev, PCI_COMMAND, &pcicmd);
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if (ret < 0) {
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printk(KERN_ERR "%s: error accessing PCI regs\n", d->name);
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goto out;
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}
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if (!(pcicmd & PCI_COMMAND_IO)) { /* is device disabled? */
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ret = ide_pci_configure(dev, d);
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if (ret < 0)
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goto out;
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*config = 1;
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printk(KERN_INFO "%s: device enabled (Linux)\n", d->name);
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}
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out:
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return ret;
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}
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/**
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* ide_pci_setup_ports - configure ports/devices on PCI IDE
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* @dev: PCI device
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* @d: IDE port info
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* @pciirq: IRQ line
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* @idx: ATA index table to update
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*
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* Scan the interfaces attached to this device and do any
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* necessary per port setup. Attach the devices and ask the
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* generic DMA layer to do its work for us.
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*
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* Normally called automaticall from do_ide_pci_setup_device,
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* but is also used directly as a helper function by some controllers
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* where the chipset setup is not the default PCI IDE one.
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*/
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void ide_pci_setup_ports(struct pci_dev *dev, const struct ide_port_info *d, int pciirq, u8 *idx)
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{
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int channels = (d->host_flags & IDE_HFLAG_SINGLE) ? 1 : 2, port;
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ide_hwif_t *hwif;
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u8 tmp;
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/*
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* Set up the IDE ports
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*/
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for (port = 0; port < channels; ++port) {
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const ide_pci_enablebit_t *e = &(d->enablebits[port]);
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if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) ||
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(tmp & e->mask) != e->val)) {
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printk(KERN_INFO "%s: IDE port disabled\n", d->name);
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continue; /* port not enabled */
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}
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hwif = ide_hwif_configure(dev, d, port, pciirq);
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if (hwif == NULL)
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continue;
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*(idx + port) = hwif->index;
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}
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}
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EXPORT_SYMBOL_GPL(ide_pci_setup_ports);
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/*
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* ide_setup_pci_device() looks at the primary/secondary interfaces
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* on a PCI IDE device and, if they are enabled, prepares the IDE driver
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* for use with them. This generic code works for most PCI chipsets.
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*
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* One thing that is not standardized is the location of the
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* primary/secondary interface "enable/disable" bits. For chipsets that
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* we "know" about, this information is in the struct ide_port_info;
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* for all other chipsets, we just assume both interfaces are enabled.
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*/
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static int do_ide_setup_pci_device(struct pci_dev *dev,
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const struct ide_port_info *d,
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u8 *idx, u8 noisy)
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{
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int tried_config = 0;
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int pciirq, ret;
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ret = ide_setup_pci_controller(dev, d, noisy, &tried_config);
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if (ret < 0)
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goto out;
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/*
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* Can we trust the reported IRQ?
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*/
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pciirq = dev->irq;
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/* Is it an "IDE storage" device in non-PCI mode? */
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if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && (dev->class & 5) != 5) {
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if (noisy)
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printk(KERN_INFO "%s: not 100%% native mode: "
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"will probe irqs later\n", d->name);
|
|
/*
|
|
* This allows offboard ide-pci cards the enable a BIOS,
|
|
* verify interrupt settings of split-mirror pci-config
|
|
* space, place chipset into init-mode, and/or preserve
|
|
* an interrupt if the card is not native ide support.
|
|
*/
|
|
ret = d->init_chipset ? d->init_chipset(dev, d->name) : 0;
|
|
if (ret < 0)
|
|
goto out;
|
|
pciirq = ret;
|
|
} else if (tried_config) {
|
|
if (noisy)
|
|
printk(KERN_INFO "%s: will probe irqs later\n", d->name);
|
|
pciirq = 0;
|
|
} else if (!pciirq) {
|
|
if (noisy)
|
|
printk(KERN_WARNING "%s: bad irq (%d): will probe later\n",
|
|
d->name, pciirq);
|
|
pciirq = 0;
|
|
} else {
|
|
if (d->init_chipset) {
|
|
ret = d->init_chipset(dev, d->name);
|
|
if (ret < 0)
|
|
goto out;
|
|
}
|
|
if (noisy)
|
|
printk(KERN_INFO "%s: 100%% native mode on irq %d\n",
|
|
d->name, pciirq);
|
|
}
|
|
|
|
/* FIXME: silent failure can happen */
|
|
|
|
ide_pci_setup_ports(dev, d, pciirq, idx);
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
int ide_setup_pci_device(struct pci_dev *dev, const struct ide_port_info *d)
|
|
{
|
|
u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
|
|
int ret;
|
|
|
|
ret = do_ide_setup_pci_device(dev, d, &idx[0], 1);
|
|
|
|
if (ret >= 0)
|
|
ide_device_add(idx, d);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(ide_setup_pci_device);
|
|
|
|
int ide_setup_pci_devices(struct pci_dev *dev1, struct pci_dev *dev2,
|
|
const struct ide_port_info *d)
|
|
{
|
|
struct pci_dev *pdev[] = { dev1, dev2 };
|
|
int ret, i;
|
|
u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
ret = do_ide_setup_pci_device(pdev[i], d, &idx[i*2], !i);
|
|
/*
|
|
* FIXME: Mom, mom, they stole me the helper function to undo
|
|
* do_ide_setup_pci_device() on the first device!
|
|
*/
|
|
if (ret < 0)
|
|
goto out;
|
|
}
|
|
|
|
ide_device_add(idx, d);
|
|
out:
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(ide_setup_pci_devices);
|