156 lines
3.8 KiB
C
156 lines
3.8 KiB
C
/*
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* Copyright (C) 2009 Cisco Systems, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __ASM_MACH_POWERTV_ASIC_H_
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#define __ASM_MACH_POWERTV_ASIC_H_
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#include <linux/io.h>
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/* ASIC types */
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enum asic_type {
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ASIC_UNKNOWN,
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ASIC_ZEUS,
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ASIC_CALLIOPE,
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ASIC_CRONUS,
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ASIC_CRONUSLITE,
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ASICS
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};
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/* hardcoded values read from Chip Version registers */
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#define CRONUS_10 0x0B4C1C20
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#define CRONUS_11 0x0B4C1C21
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#define CRONUSLITE_10 0x0B4C1C40
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#define NAND_FLASH_BASE 0x03000000
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#define ZEUS_IO_BASE 0x09000000
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#define CALLIOPE_IO_BASE 0x08000000
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#define CRONUS_IO_BASE 0x09000000
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#define ASIC_IO_SIZE 0x01000000
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/* Definitions for backward compatibility */
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#define UART1_INTSTAT uart1_intstat
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#define UART1_INTEN uart1_inten
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#define UART1_CONFIG1 uart1_config1
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#define UART1_CONFIG2 uart1_config2
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#define UART1_DIVISORHI uart1_divisorhi
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#define UART1_DIVISORLO uart1_divisorlo
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#define UART1_DATA uart1_data
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#define UART1_STATUS uart1_status
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/* ASIC register enumeration */
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struct register_map {
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u32 eic_slow0_strt_add;
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u32 eic_cfg_bits;
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u32 eic_ready_status;
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u32 chipver3;
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u32 chipver2;
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u32 chipver1;
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u32 chipver0;
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u32 uart1_intstat;
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u32 uart1_inten;
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u32 uart1_config1;
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u32 uart1_config2;
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u32 uart1_divisorhi;
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u32 uart1_divisorlo;
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u32 uart1_data;
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u32 uart1_status;
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u32 int_stat_3;
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u32 int_stat_2;
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u32 int_stat_1;
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u32 int_stat_0;
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u32 int_config;
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u32 int_int_scan;
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u32 ien_int_3;
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u32 ien_int_2;
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u32 ien_int_1;
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u32 ien_int_0;
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u32 int_level_3_3;
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u32 int_level_3_2;
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u32 int_level_3_1;
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u32 int_level_3_0;
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u32 int_level_2_3;
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u32 int_level_2_2;
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u32 int_level_2_1;
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u32 int_level_2_0;
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u32 int_level_1_3;
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u32 int_level_1_2;
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u32 int_level_1_1;
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u32 int_level_1_0;
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u32 int_level_0_3;
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u32 int_level_0_2;
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u32 int_level_0_1;
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u32 int_level_0_0;
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u32 int_docsis_en;
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u32 mips_pll_setup;
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u32 usb_fs;
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u32 test_bus;
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u32 crt_spare;
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u32 usb2_ohci_int_mask;
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u32 usb2_strap;
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u32 ehci_hcapbase;
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u32 ohci_hc_revision;
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u32 bcm1_bs_lmi_steer;
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u32 usb2_control;
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u32 usb2_stbus_obc;
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u32 usb2_stbus_mess_size;
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u32 usb2_stbus_chunk_size;
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u32 pcie_regs;
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u32 tim_ch;
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u32 tim_cl;
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u32 gpio_dout;
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u32 gpio_din;
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u32 gpio_dir;
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u32 watchdog;
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u32 front_panel;
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u32 register_maps;
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};
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extern enum asic_type asic;
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extern const struct register_map *register_map;
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extern unsigned long asic_phy_base; /* Physical address of ASIC */
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extern unsigned long asic_base; /* Virtual address of ASIC */
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/*
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* Macros to interface to registers through their ioremapped address
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* asic_reg_offset Returns the offset of a given register from the start
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* of the ASIC address space
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* asic_reg_phys_addr Returns the physical address of the given register
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* asic_reg_addr Returns the iomapped virtual address of the given
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* register.
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*/
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#define asic_reg_offset(x) (register_map->x)
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#define asic_reg_phys_addr(x) (asic_phy_base + asic_reg_offset(x))
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#define asic_reg_addr(x) \
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((unsigned int *) (asic_base + asic_reg_offset(x)))
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/*
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* The asic_reg macro is gone. It should be replaced by either asic_read or
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* asic_write, as appropriate.
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*/
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#define asic_read(x) readl(asic_reg_addr(x))
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#define asic_write(v, x) writel(v, asic_reg_addr(x))
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extern void asic_irq_init(void);
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#endif
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