148 lines
3.5 KiB
C
148 lines
3.5 KiB
C
#ifndef _ASM_X86_MACH_DEFAULT_MACH_APIC_H
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#define _ASM_X86_MACH_DEFAULT_MACH_APIC_H
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#ifdef CONFIG_X86_LOCAL_APIC
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#include <mach_apicdef.h>
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#include <asm/smp.h>
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#define APIC_DFR_VALUE (APIC_DFR_FLAT)
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static inline const struct cpumask *default_target_cpus(void)
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{
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#ifdef CONFIG_SMP
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return cpu_online_mask;
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#else
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return cpumask_of(0);
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#endif
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}
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#ifdef CONFIG_X86_64
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#include <asm/genapic.h>
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#define read_apic_id() (apic->get_apic_id(apic_read(APIC_ID)))
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#define wakeup_secondary_cpu (apic->wakeup_cpu)
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extern void default_setup_apic_routing(void);
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#else
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#define wakeup_secondary_cpu wakeup_secondary_cpu_via_init
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/*
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* Set up the logical destination ID.
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*
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* Intel recommends to set DFR, LDR and TPR before enabling
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* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
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* document number 292116). So here it goes...
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*/
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static inline void default_init_apic_ldr(void)
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{
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unsigned long val;
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apic_write(APIC_DFR, APIC_DFR_VALUE);
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val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
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val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
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apic_write(APIC_LDR, val);
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}
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static inline int default_apic_id_registered(void)
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{
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return physid_isset(read_apic_id(), phys_cpu_present_map);
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}
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static inline unsigned int
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default_cpu_mask_to_apicid(const struct cpumask *cpumask)
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{
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return cpumask_bits(cpumask)[0];
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}
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static inline unsigned int
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default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
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const struct cpumask *andmask)
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{
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unsigned long mask1 = cpumask_bits(cpumask)[0];
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unsigned long mask2 = cpumask_bits(andmask)[0];
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unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
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return (unsigned int)(mask1 & mask2 & mask3);
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}
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static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
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{
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return cpuid_apic >> index_msb;
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}
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static inline void default_setup_apic_routing(void)
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{
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#ifdef CONFIG_X86_IO_APIC
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printk("Enabling APIC mode: %s. Using %d I/O APICs\n",
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"Flat", nr_ioapics);
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#endif
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}
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static inline int default_apicid_to_node(int logical_apicid)
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{
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#ifdef CONFIG_SMP
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return apicid_2_node[hard_smp_processor_id()];
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#else
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return 0;
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#endif
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}
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#endif
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static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid)
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{
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return physid_isset(apicid, bitmap);
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}
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static inline unsigned long default_check_apicid_present(int bit)
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{
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return physid_isset(bit, phys_cpu_present_map);
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}
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static inline physid_mask_t default_ioapic_phys_id_map(physid_mask_t phys_map)
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{
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return phys_map;
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}
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/* Mapping from cpu number to logical apicid */
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static inline int default_cpu_to_logical_apicid(int cpu)
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{
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return 1 << cpu;
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}
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static inline int __default_cpu_present_to_apicid(int mps_cpu)
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{
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if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
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return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
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else
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return BAD_APICID;
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}
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static inline int
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__default_check_phys_apicid_present(int boot_cpu_physical_apicid)
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{
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return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
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}
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#ifdef CONFIG_X86_32
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static inline int default_cpu_present_to_apicid(int mps_cpu)
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{
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return __default_cpu_present_to_apicid(mps_cpu);
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}
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static inline int
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default_check_phys_apicid_present(int boot_cpu_physical_apicid)
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{
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return __default_check_phys_apicid_present(boot_cpu_physical_apicid);
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}
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#else
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extern int default_cpu_present_to_apicid(int mps_cpu);
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extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid);
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#endif
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static inline physid_mask_t default_apicid_to_cpu_present(int phys_apicid)
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{
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return physid_mask_of_physid(phys_apicid);
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}
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#endif /* CONFIG_X86_LOCAL_APIC */
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#endif /* _ASM_X86_MACH_DEFAULT_MACH_APIC_H */
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