![Jeff Garzik](/assets/img/avatar_default.png)
eliminate a bunch of if (mmio) writel() else outl() code with the pci_iomap() and io{read,write}{8,16,32}() interface.
563 lines
16 KiB
C
563 lines
16 KiB
C
/*
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* sata_nv.c - NVIDIA nForce SATA
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*
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* Copyright 2004 NVIDIA Corp. All rights reserved.
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* Copyright 2004 Andrew Chew
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*
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* libata documentation is available via 'make {ps|pdf}docs',
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* as Documentation/DocBook/libata.*
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*
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* No hardware documentation available outside of NVIDIA.
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* This driver programs the NVIDIA SATA controller in a similar
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* fashion as with other PCI IDE BMDMA controllers, with a few
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* NV-specific details such as register offsets, SATA phy location,
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* hotplug info, etc.
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*
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/device.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "sata_nv"
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#define DRV_VERSION "0.8"
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enum {
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NV_PORTS = 2,
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NV_PIO_MASK = 0x1f,
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NV_MWDMA_MASK = 0x07,
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NV_UDMA_MASK = 0x7f,
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NV_PORT0_SCR_REG_OFFSET = 0x00,
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NV_PORT1_SCR_REG_OFFSET = 0x40,
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NV_INT_STATUS = 0x10,
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NV_INT_STATUS_CK804 = 0x440,
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NV_INT_STATUS_PDEV_INT = 0x01,
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NV_INT_STATUS_PDEV_PM = 0x02,
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NV_INT_STATUS_PDEV_ADDED = 0x04,
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NV_INT_STATUS_PDEV_REMOVED = 0x08,
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NV_INT_STATUS_SDEV_INT = 0x10,
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NV_INT_STATUS_SDEV_PM = 0x20,
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NV_INT_STATUS_SDEV_ADDED = 0x40,
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NV_INT_STATUS_SDEV_REMOVED = 0x80,
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NV_INT_STATUS_PDEV_HOTPLUG = (NV_INT_STATUS_PDEV_ADDED |
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NV_INT_STATUS_PDEV_REMOVED),
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NV_INT_STATUS_SDEV_HOTPLUG = (NV_INT_STATUS_SDEV_ADDED |
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NV_INT_STATUS_SDEV_REMOVED),
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NV_INT_STATUS_HOTPLUG = (NV_INT_STATUS_PDEV_HOTPLUG |
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NV_INT_STATUS_SDEV_HOTPLUG),
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NV_INT_ENABLE = 0x11,
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NV_INT_ENABLE_CK804 = 0x441,
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NV_INT_ENABLE_PDEV_MASK = 0x01,
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NV_INT_ENABLE_PDEV_PM = 0x02,
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NV_INT_ENABLE_PDEV_ADDED = 0x04,
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NV_INT_ENABLE_PDEV_REMOVED = 0x08,
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NV_INT_ENABLE_SDEV_MASK = 0x10,
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NV_INT_ENABLE_SDEV_PM = 0x20,
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NV_INT_ENABLE_SDEV_ADDED = 0x40,
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NV_INT_ENABLE_SDEV_REMOVED = 0x80,
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NV_INT_ENABLE_PDEV_HOTPLUG = (NV_INT_ENABLE_PDEV_ADDED |
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NV_INT_ENABLE_PDEV_REMOVED),
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NV_INT_ENABLE_SDEV_HOTPLUG = (NV_INT_ENABLE_SDEV_ADDED |
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NV_INT_ENABLE_SDEV_REMOVED),
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NV_INT_ENABLE_HOTPLUG = (NV_INT_ENABLE_PDEV_HOTPLUG |
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NV_INT_ENABLE_SDEV_HOTPLUG),
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NV_INT_CONFIG = 0x12,
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NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI
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// For PCI config register 20
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NV_MCP_SATA_CFG_20 = 0x50,
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NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
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};
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static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
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static irqreturn_t nv_interrupt (int irq, void *dev_instance,
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struct pt_regs *regs);
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static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
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static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
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static void nv_host_stop (struct ata_host_set *host_set);
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static void nv_enable_hotplug(struct ata_probe_ent *probe_ent);
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static void nv_disable_hotplug(struct ata_host_set *host_set);
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static int nv_check_hotplug(struct ata_host_set *host_set);
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static void nv_enable_hotplug_ck804(struct ata_probe_ent *probe_ent);
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static void nv_disable_hotplug_ck804(struct ata_host_set *host_set);
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static int nv_check_hotplug_ck804(struct ata_host_set *host_set);
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enum nv_host_type
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{
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GENERIC,
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NFORCE2,
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NFORCE3,
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CK804
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};
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static const struct pci_device_id nv_pci_tbl[] = {
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{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE2 },
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{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
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{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
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{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
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{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
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{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
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{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
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{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
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{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
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{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
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{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
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{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
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PCI_ANY_ID, PCI_ANY_ID,
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PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC },
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{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
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PCI_ANY_ID, PCI_ANY_ID,
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PCI_CLASS_STORAGE_RAID<<8, 0xffff00, GENERIC },
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{ 0, } /* terminate list */
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};
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struct nv_host_desc
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{
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enum nv_host_type host_type;
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void (*enable_hotplug)(struct ata_probe_ent *probe_ent);
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void (*disable_hotplug)(struct ata_host_set *host_set);
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int (*check_hotplug)(struct ata_host_set *host_set);
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};
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static struct nv_host_desc nv_device_tbl[] = {
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{
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.host_type = GENERIC,
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.enable_hotplug = NULL,
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.disable_hotplug= NULL,
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.check_hotplug = NULL,
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},
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{
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.host_type = NFORCE2,
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.enable_hotplug = nv_enable_hotplug,
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.disable_hotplug= nv_disable_hotplug,
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.check_hotplug = nv_check_hotplug,
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},
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{
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.host_type = NFORCE3,
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.enable_hotplug = nv_enable_hotplug,
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.disable_hotplug= nv_disable_hotplug,
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.check_hotplug = nv_check_hotplug,
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},
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{ .host_type = CK804,
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.enable_hotplug = nv_enable_hotplug_ck804,
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.disable_hotplug= nv_disable_hotplug_ck804,
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.check_hotplug = nv_check_hotplug_ck804,
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},
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};
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struct nv_host
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{
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struct nv_host_desc *host_desc;
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unsigned long host_flags;
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};
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static struct pci_driver nv_pci_driver = {
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.name = DRV_NAME,
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.id_table = nv_pci_tbl,
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.probe = nv_init_one,
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.remove = ata_pci_remove_one,
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};
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static struct scsi_host_template nv_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.eh_strategy_handler = ata_scsi_error,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_MAX_PRD,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.bios_param = ata_std_bios_param,
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};
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static const struct ata_port_operations nv_ops = {
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.port_disable = ata_port_disable,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.exec_command = ata_exec_command,
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.check_status = ata_check_status,
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.dev_select = ata_std_dev_select,
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.phy_reset = sata_phy_reset,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.eng_timeout = ata_eng_timeout,
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.irq_handler = nv_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.scr_read = nv_scr_read,
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.scr_write = nv_scr_write,
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.port_start = ata_port_start,
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.port_stop = ata_port_stop,
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.host_stop = nv_host_stop,
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};
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/* FIXME: The hardware provides the necessary SATA PHY controls
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* to support ATA_FLAG_SATA_RESET. However, it is currently
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* necessary to disable that flag, to solve misdetection problems.
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* See http://bugme.osdl.org/show_bug.cgi?id=3352 for more info.
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*
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* This problem really needs to be investigated further. But in the
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* meantime, we avoid ATA_FLAG_SATA_RESET to get people working.
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*/
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static struct ata_port_info nv_port_info = {
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.sht = &nv_sht,
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.host_flags = ATA_FLAG_SATA |
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/* ATA_FLAG_SATA_RESET | */
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ATA_FLAG_SRST |
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ATA_FLAG_NO_LEGACY,
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.pio_mask = NV_PIO_MASK,
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.mwdma_mask = NV_MWDMA_MASK,
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.udma_mask = NV_UDMA_MASK,
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.port_ops = &nv_ops,
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};
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MODULE_AUTHOR("NVIDIA");
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MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
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MODULE_VERSION(DRV_VERSION);
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static irqreturn_t nv_interrupt (int irq, void *dev_instance,
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struct pt_regs *regs)
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{
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struct ata_host_set *host_set = dev_instance;
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struct nv_host *host = host_set->private_data;
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unsigned int i;
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unsigned int handled = 0;
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unsigned long flags;
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spin_lock_irqsave(&host_set->lock, flags);
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for (i = 0; i < host_set->n_ports; i++) {
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struct ata_port *ap;
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ap = host_set->ports[i];
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if (ap &&
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!(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
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struct ata_queued_cmd *qc;
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qc = ata_qc_from_tag(ap, ap->active_tag);
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if (qc && (!(qc->tf.ctl & ATA_NIEN)))
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handled += ata_host_intr(ap, qc);
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else
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// No request pending? Clear interrupt status
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// anyway, in case there's one pending.
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ap->ops->check_status(ap);
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}
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}
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if (host->host_desc->check_hotplug)
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handled += host->host_desc->check_hotplug(host_set);
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spin_unlock_irqrestore(&host_set->lock, flags);
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return IRQ_RETVAL(handled);
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}
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static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
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{
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if (sc_reg > SCR_CONTROL)
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return 0xffffffffU;
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return ioread32((void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
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}
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static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
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{
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if (sc_reg > SCR_CONTROL)
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return;
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iowrite32(val, (void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
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}
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static void nv_host_stop (struct ata_host_set *host_set)
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{
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struct nv_host *host = host_set->private_data;
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// Disable hotplug event interrupts.
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if (host->host_desc->disable_hotplug)
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host->host_desc->disable_hotplug(host_set);
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kfree(host);
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ata_pci_host_stop(host_set);
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}
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static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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static int printed_version = 0;
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struct nv_host *host;
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struct ata_port_info *ppi;
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struct ata_probe_ent *probe_ent;
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int pci_dev_busy = 0;
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int rc;
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u32 bar;
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unsigned long base;
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// Make sure this is a SATA controller by counting the number of bars
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// (NVIDIA SATA controllers will always have six bars). Otherwise,
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// it's an IDE controller and we ignore it.
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for (bar=0; bar<6; bar++)
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if (pci_resource_start(pdev, bar) == 0)
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return -ENODEV;
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if (!printed_version++)
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dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
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rc = pci_enable_device(pdev);
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if (rc)
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goto err_out;
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rc = pci_request_regions(pdev, DRV_NAME);
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if (rc) {
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pci_dev_busy = 1;
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goto err_out_disable;
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}
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rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
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if (rc)
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goto err_out_regions;
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rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
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if (rc)
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goto err_out_regions;
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rc = -ENOMEM;
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ppi = &nv_port_info;
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probe_ent = ata_pci_init_native_mode(pdev, &ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
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if (!probe_ent)
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goto err_out_regions;
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host = kmalloc(sizeof(struct nv_host), GFP_KERNEL);
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if (!host)
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goto err_out_free_ent;
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memset(host, 0, sizeof(struct nv_host));
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host->host_desc = &nv_device_tbl[ent->driver_data];
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probe_ent->private_data = host;
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probe_ent->mmio_base = pci_iomap(pdev, 5, 0);
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if (!probe_ent->mmio_base) {
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rc = -EIO;
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goto err_out_free_host;
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}
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base = (unsigned long)probe_ent->mmio_base;
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probe_ent->port[0].scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
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probe_ent->port[1].scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
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pci_set_master(pdev);
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rc = ata_device_add(probe_ent);
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if (rc != NV_PORTS)
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goto err_out_iounmap;
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// Enable hotplug event interrupts.
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if (host->host_desc->enable_hotplug)
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host->host_desc->enable_hotplug(probe_ent);
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kfree(probe_ent);
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return 0;
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err_out_iounmap:
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pci_iounmap(pdev, probe_ent->mmio_base);
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err_out_free_host:
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kfree(host);
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err_out_free_ent:
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kfree(probe_ent);
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err_out_regions:
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pci_release_regions(pdev);
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err_out_disable:
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if (!pci_dev_busy)
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pci_disable_device(pdev);
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err_out:
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return rc;
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}
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static void nv_enable_hotplug(struct ata_probe_ent *probe_ent)
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{
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u8 intr_mask;
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outb(NV_INT_STATUS_HOTPLUG,
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probe_ent->port[0].scr_addr + NV_INT_STATUS);
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intr_mask = inb(probe_ent->port[0].scr_addr + NV_INT_ENABLE);
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intr_mask |= NV_INT_ENABLE_HOTPLUG;
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outb(intr_mask, probe_ent->port[0].scr_addr + NV_INT_ENABLE);
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}
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static void nv_disable_hotplug(struct ata_host_set *host_set)
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{
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u8 intr_mask;
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|
intr_mask = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_ENABLE);
|
|
|
|
intr_mask &= ~(NV_INT_ENABLE_HOTPLUG);
|
|
|
|
outb(intr_mask, host_set->ports[0]->ioaddr.scr_addr + NV_INT_ENABLE);
|
|
}
|
|
|
|
static int nv_check_hotplug(struct ata_host_set *host_set)
|
|
{
|
|
u8 intr_status;
|
|
|
|
intr_status = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
|
|
|
|
// Clear interrupt status.
|
|
outb(0xff, host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
|
|
|
|
if (intr_status & NV_INT_STATUS_HOTPLUG) {
|
|
if (intr_status & NV_INT_STATUS_PDEV_ADDED)
|
|
printk(KERN_WARNING "nv_sata: "
|
|
"Primary device added\n");
|
|
|
|
if (intr_status & NV_INT_STATUS_PDEV_REMOVED)
|
|
printk(KERN_WARNING "nv_sata: "
|
|
"Primary device removed\n");
|
|
|
|
if (intr_status & NV_INT_STATUS_SDEV_ADDED)
|
|
printk(KERN_WARNING "nv_sata: "
|
|
"Secondary device added\n");
|
|
|
|
if (intr_status & NV_INT_STATUS_SDEV_REMOVED)
|
|
printk(KERN_WARNING "nv_sata: "
|
|
"Secondary device removed\n");
|
|
|
|
return 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void nv_enable_hotplug_ck804(struct ata_probe_ent *probe_ent)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
|
|
u8 intr_mask;
|
|
u8 regval;
|
|
|
|
pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val);
|
|
regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
|
|
pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
|
|
|
|
writeb(NV_INT_STATUS_HOTPLUG, probe_ent->mmio_base + NV_INT_STATUS_CK804);
|
|
|
|
intr_mask = readb(probe_ent->mmio_base + NV_INT_ENABLE_CK804);
|
|
intr_mask |= NV_INT_ENABLE_HOTPLUG;
|
|
|
|
writeb(intr_mask, probe_ent->mmio_base + NV_INT_ENABLE_CK804);
|
|
}
|
|
|
|
static void nv_disable_hotplug_ck804(struct ata_host_set *host_set)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(host_set->dev);
|
|
u8 intr_mask;
|
|
u8 regval;
|
|
|
|
intr_mask = readb(host_set->mmio_base + NV_INT_ENABLE_CK804);
|
|
|
|
intr_mask &= ~(NV_INT_ENABLE_HOTPLUG);
|
|
|
|
writeb(intr_mask, host_set->mmio_base + NV_INT_ENABLE_CK804);
|
|
|
|
pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val);
|
|
regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
|
|
pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
|
|
}
|
|
|
|
static int nv_check_hotplug_ck804(struct ata_host_set *host_set)
|
|
{
|
|
u8 intr_status;
|
|
|
|
intr_status = readb(host_set->mmio_base + NV_INT_STATUS_CK804);
|
|
|
|
// Clear interrupt status.
|
|
writeb(0xff, host_set->mmio_base + NV_INT_STATUS_CK804);
|
|
|
|
if (intr_status & NV_INT_STATUS_HOTPLUG) {
|
|
if (intr_status & NV_INT_STATUS_PDEV_ADDED)
|
|
printk(KERN_WARNING "nv_sata: "
|
|
"Primary device added\n");
|
|
|
|
if (intr_status & NV_INT_STATUS_PDEV_REMOVED)
|
|
printk(KERN_WARNING "nv_sata: "
|
|
"Primary device removed\n");
|
|
|
|
if (intr_status & NV_INT_STATUS_SDEV_ADDED)
|
|
printk(KERN_WARNING "nv_sata: "
|
|
"Secondary device added\n");
|
|
|
|
if (intr_status & NV_INT_STATUS_SDEV_REMOVED)
|
|
printk(KERN_WARNING "nv_sata: "
|
|
"Secondary device removed\n");
|
|
|
|
return 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __init nv_init(void)
|
|
{
|
|
return pci_module_init(&nv_pci_driver);
|
|
}
|
|
|
|
static void __exit nv_exit(void)
|
|
{
|
|
pci_unregister_driver(&nv_pci_driver);
|
|
}
|
|
|
|
module_init(nv_init);
|
|
module_exit(nv_exit);
|