81 lines
1.5 KiB
Plaintext
81 lines
1.5 KiB
Plaintext
/*
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* Copyright 2012 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/include/ "skeleton.dtsi"
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/ {
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interrupt-parent = <&intc>;
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cpus {
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cpu@0 {
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compatible = "arm,cortex-a8";
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};
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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osc: oscillator {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x01c20000 0x300000>;
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ranges;
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timer@01c20c00 {
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compatible = "allwinner,sunxi-timer";
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reg = <0x01c20c00 0x90>;
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interrupts = <22>;
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clocks = <&osc>;
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};
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wdt: watchdog@01c20c90 {
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compatible = "allwinner,sunxi-wdt";
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reg = <0x01c20c90 0x10>;
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};
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intc: interrupt-controller@01c20400 {
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compatible = "allwinner,sunxi-ic";
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reg = <0x01c20400 0x400>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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uart0: uart@01c28000 {
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compatible = "ns8250";
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reg = <0x01c28000 0x400>;
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interrupts = <1>;
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reg-shift = <2>;
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clock-frequency = <24000000>;
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status = "disabled";
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};
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uart1: uart@01c28400 {
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compatible = "ns8250";
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reg = <0x01c28400 0x400>;
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interrupts = <2>;
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reg-shift = <2>;
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clock-frequency = <24000000>;
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status = "disabled";
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};
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};
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};
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