96c5590058
The 'latency timer' of PCI devices, both Type 0 and Type 1, is setup in architecture-specific code [see: 'pcibios_set_master()']. There are two approaches being taken by all the architectures - check if the 'latency timer' is currently set between 16 and 255 and if not bring it within bounds, or, do nothing (and then there is the gratuitously different PA-RISC implementation). There is nothing architecture-specific about PCI's 'latency timer' so this patch pulls its setup functionality up into the PCI core by creating a generic 'pcibios_set_master()' function using the '__weak' attribute which can be used by all architectures as a default which, if necessary, can then be over-ridden by architecture-specific code. No functional change. Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
20 lines
382 B
C
20 lines
382 B
C
#ifndef _ASM_H8300_PCI_H
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#define _ASM_H8300_PCI_H
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/*
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* asm-h8300/pci.h - H8/300 specific PCI declarations.
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*
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* Yoshinori Sato <ysato@users.sourceforge.jp>
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*/
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#define pcibios_assign_all_busses() 0
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static inline void pcibios_penalize_isa_irq(int irq, int active)
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{
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/* We don't do dynamic PCI IRQ allocation */
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}
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#define PCI_DMA_BUS_IS_PHYS (1)
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#endif /* _ASM_H8300_PCI_H */
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