![Stephen Rothwell](/assets/img/avatar_default.png)
so remove a firmware feature test. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
983 lines
26 KiB
C
983 lines
26 KiB
C
/*
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* Port for PPC64 David Engebretsen, IBM Corp.
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* Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
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*
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* Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
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* Rework, based on alpha PCI code.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <linux/mm.h>
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#include <linux/list.h>
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#include <linux/syscalls.h>
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#include <linux/irq.h>
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#include <linux/vmalloc.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#include <asm/byteorder.h>
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#include <asm/machdep.h>
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#include <asm/ppc-pci.h>
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#include <asm/firmware.h>
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#ifdef DEBUG
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#include <asm/udbg.h>
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#define DBG(fmt...) printk(fmt)
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#else
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#define DBG(fmt...)
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#endif
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unsigned long pci_probe_only = 1;
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int pci_assign_all_buses = 0;
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static void fixup_resource(struct resource *res, struct pci_dev *dev);
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static void do_bus_setup(struct pci_bus *bus);
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/* pci_io_base -- the base address from which io bars are offsets.
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* This is the lowest I/O base address (so bar values are always positive),
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* and it *must* be the start of ISA space if an ISA bus exists because
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* ISA drivers use hard coded offsets. If no ISA bus exists nothing
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* is mapped on the first 64K of IO space
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*/
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unsigned long pci_io_base = ISA_IO_BASE;
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EXPORT_SYMBOL(pci_io_base);
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LIST_HEAD(hose_list);
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static struct dma_mapping_ops *pci_dma_ops;
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void set_pci_dma_ops(struct dma_mapping_ops *dma_ops)
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{
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pci_dma_ops = dma_ops;
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}
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struct dma_mapping_ops *get_pci_dma_ops(void)
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{
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return pci_dma_ops;
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}
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EXPORT_SYMBOL(get_pci_dma_ops);
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static void fixup_broken_pcnet32(struct pci_dev* dev)
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{
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if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
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dev->vendor = PCI_VENDOR_ID_AMD;
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pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
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void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
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struct resource *res)
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{
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unsigned long offset = 0;
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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if (!hose)
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return;
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if (res->flags & IORESOURCE_IO)
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offset = (unsigned long)hose->io_base_virt - _IO_BASE;
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if (res->flags & IORESOURCE_MEM)
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offset = hose->pci_mem_offset;
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region->start = res->start - offset;
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region->end = res->end - offset;
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}
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void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
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struct pci_bus_region *region)
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{
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unsigned long offset = 0;
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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if (!hose)
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return;
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if (res->flags & IORESOURCE_IO)
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offset = (unsigned long)hose->io_base_virt - _IO_BASE;
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if (res->flags & IORESOURCE_MEM)
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offset = hose->pci_mem_offset;
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res->start = region->start + offset;
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res->end = region->end + offset;
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}
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#ifdef CONFIG_HOTPLUG
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EXPORT_SYMBOL(pcibios_resource_to_bus);
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EXPORT_SYMBOL(pcibios_bus_to_resource);
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#endif
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/*
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* We need to avoid collisions with `mirrored' VGA ports
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* and other strange ISA hardware, so we always want the
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* addresses to be allocated in the 0x000-0x0ff region
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* modulo 0x400.
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*
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* Why? Because some silly external IO cards only decode
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* the low 10 bits of the IO address. The 0x00-0xff region
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* is reserved for motherboard devices that decode all 16
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* bits, so it's ok to allocate at, say, 0x2800-0x28ff,
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* but we want to try to avoid allocating at 0x2900-0x2bff
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* which might have be mirrored at 0x0100-0x03ff..
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*/
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void pcibios_align_resource(void *data, struct resource *res,
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resource_size_t size, resource_size_t align)
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{
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struct pci_dev *dev = data;
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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resource_size_t start = res->start;
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unsigned long alignto;
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if (res->flags & IORESOURCE_IO) {
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unsigned long offset = (unsigned long)hose->io_base_virt -
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_IO_BASE;
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/* Make sure we start at our min on all hoses */
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if (start - offset < PCIBIOS_MIN_IO)
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start = PCIBIOS_MIN_IO + offset;
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/*
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* Put everything into 0x00-0xff region modulo 0x400
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*/
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if (start & 0x300)
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start = (start + 0x3ff) & ~0x3ff;
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} else if (res->flags & IORESOURCE_MEM) {
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/* Make sure we start at our min on all hoses */
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if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM)
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start = PCIBIOS_MIN_MEM + hose->pci_mem_offset;
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/* Align to multiple of size of minimum base. */
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alignto = max(0x1000UL, align);
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start = ALIGN(start, alignto);
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}
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res->start = start;
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}
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void __devinit pcibios_claim_one_bus(struct pci_bus *b)
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{
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struct pci_dev *dev;
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struct pci_bus *child_bus;
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list_for_each_entry(dev, &b->devices, bus_list) {
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int i;
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for (i = 0; i < PCI_NUM_RESOURCES; i++) {
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struct resource *r = &dev->resource[i];
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if (r->parent || !r->start || !r->flags)
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continue;
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pci_claim_resource(dev, i);
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}
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}
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list_for_each_entry(child_bus, &b->children, node)
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pcibios_claim_one_bus(child_bus);
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}
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#ifdef CONFIG_HOTPLUG
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EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
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#endif
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static void __init pcibios_claim_of_setup(void)
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{
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struct pci_bus *b;
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if (firmware_has_feature(FW_FEATURE_ISERIES))
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return;
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list_for_each_entry(b, &pci_root_buses, node)
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pcibios_claim_one_bus(b);
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}
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static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
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{
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const u32 *prop;
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int len;
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prop = of_get_property(np, name, &len);
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if (prop && len >= 4)
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return *prop;
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return def;
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}
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static unsigned int pci_parse_of_flags(u32 addr0)
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{
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unsigned int flags = 0;
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if (addr0 & 0x02000000) {
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flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
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flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
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flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
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if (addr0 & 0x40000000)
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flags |= IORESOURCE_PREFETCH
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| PCI_BASE_ADDRESS_MEM_PREFETCH;
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} else if (addr0 & 0x01000000)
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flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
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return flags;
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}
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static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
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{
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u64 base, size;
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unsigned int flags;
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struct resource *res;
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const u32 *addrs;
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u32 i;
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int proplen;
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addrs = of_get_property(node, "assigned-addresses", &proplen);
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if (!addrs)
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return;
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DBG(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
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for (; proplen >= 20; proplen -= 20, addrs += 5) {
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flags = pci_parse_of_flags(addrs[0]);
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if (!flags)
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continue;
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base = of_read_number(&addrs[1], 2);
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size = of_read_number(&addrs[3], 2);
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if (!size)
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continue;
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i = addrs[0] & 0xff;
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DBG(" base: %llx, size: %llx, i: %x\n",
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(unsigned long long)base, (unsigned long long)size, i);
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if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
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res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
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} else if (i == dev->rom_base_reg) {
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res = &dev->resource[PCI_ROM_RESOURCE];
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flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
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} else {
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printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
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continue;
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}
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res->start = base;
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res->end = base + size - 1;
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res->flags = flags;
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res->name = pci_name(dev);
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fixup_resource(res, dev);
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}
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}
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struct pci_dev *of_create_pci_dev(struct device_node *node,
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struct pci_bus *bus, int devfn)
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{
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struct pci_dev *dev;
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const char *type;
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dev = alloc_pci_dev();
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if (!dev)
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return NULL;
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type = of_get_property(node, "device_type", NULL);
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if (type == NULL)
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type = "";
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DBG(" create device, devfn: %x, type: %s\n", devfn, type);
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dev->bus = bus;
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dev->sysdata = node;
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dev->dev.parent = bus->bridge;
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dev->dev.bus = &pci_bus_type;
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dev->devfn = devfn;
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dev->multifunction = 0; /* maybe a lie? */
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dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
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dev->device = get_int_prop(node, "device-id", 0xffff);
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dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
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dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
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dev->cfg_size = pci_cfg_space_size(dev);
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sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
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dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
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dev->class = get_int_prop(node, "class-code", 0);
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dev->revision = get_int_prop(node, "revision-id", 0);
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DBG(" class: 0x%x\n", dev->class);
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DBG(" revision: 0x%x\n", dev->revision);
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dev->current_state = 4; /* unknown power state */
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dev->error_state = pci_channel_io_normal;
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dev->dma_mask = 0xffffffff;
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if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
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/* a PCI-PCI bridge */
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dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
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dev->rom_base_reg = PCI_ROM_ADDRESS1;
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} else if (!strcmp(type, "cardbus")) {
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dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
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} else {
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dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
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dev->rom_base_reg = PCI_ROM_ADDRESS;
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/* Maybe do a default OF mapping here */
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dev->irq = NO_IRQ;
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}
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pci_parse_of_addrs(node, dev);
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DBG(" adding to system ...\n");
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pci_device_add(dev, bus);
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return dev;
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}
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EXPORT_SYMBOL(of_create_pci_dev);
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void __devinit of_scan_bus(struct device_node *node,
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struct pci_bus *bus)
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{
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struct device_node *child = NULL;
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const u32 *reg;
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int reglen, devfn;
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struct pci_dev *dev;
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DBG("of_scan_bus(%s) bus no %d... \n", node->full_name, bus->number);
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while ((child = of_get_next_child(node, child)) != NULL) {
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DBG(" * %s\n", child->full_name);
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reg = of_get_property(child, "reg", ®len);
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if (reg == NULL || reglen < 20)
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continue;
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devfn = (reg[0] >> 8) & 0xff;
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/* create a new pci_dev for this device */
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dev = of_create_pci_dev(child, bus, devfn);
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if (!dev)
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continue;
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DBG("dev header type: %x\n", dev->hdr_type);
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if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
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dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
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of_scan_pci_bridge(child, dev);
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}
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do_bus_setup(bus);
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}
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EXPORT_SYMBOL(of_scan_bus);
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void __devinit of_scan_pci_bridge(struct device_node *node,
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struct pci_dev *dev)
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{
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struct pci_bus *bus;
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const u32 *busrange, *ranges;
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int len, i, mode;
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struct resource *res;
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unsigned int flags;
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u64 size;
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DBG("of_scan_pci_bridge(%s)\n", node->full_name);
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/* parse bus-range property */
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busrange = of_get_property(node, "bus-range", &len);
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if (busrange == NULL || len != 8) {
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printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
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node->full_name);
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return;
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}
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ranges = of_get_property(node, "ranges", &len);
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if (ranges == NULL) {
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printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
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node->full_name);
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return;
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}
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bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
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if (!bus) {
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printk(KERN_ERR "Failed to create pci bus for %s\n",
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node->full_name);
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return;
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}
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bus->primary = dev->bus->number;
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bus->subordinate = busrange[1];
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bus->bridge_ctl = 0;
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bus->sysdata = node;
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/* parse ranges property */
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/* PCI #address-cells == 3 and #size-cells == 2 always */
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res = &dev->resource[PCI_BRIDGE_RESOURCES];
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for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
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res->flags = 0;
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bus->resource[i] = res;
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++res;
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}
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i = 1;
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for (; len >= 32; len -= 32, ranges += 8) {
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flags = pci_parse_of_flags(ranges[0]);
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size = of_read_number(&ranges[6], 2);
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if (flags == 0 || size == 0)
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continue;
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if (flags & IORESOURCE_IO) {
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res = bus->resource[0];
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if (res->flags) {
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printk(KERN_ERR "PCI: ignoring extra I/O range"
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" for bridge %s\n", node->full_name);
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continue;
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}
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} else {
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if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
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printk(KERN_ERR "PCI: too many memory ranges"
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" for bridge %s\n", node->full_name);
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continue;
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}
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res = bus->resource[i];
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++i;
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}
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res->start = of_read_number(&ranges[1], 2);
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res->end = res->start + size - 1;
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res->flags = flags;
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fixup_resource(res, dev);
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}
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sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
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bus->number);
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DBG(" bus name: %s\n", bus->name);
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mode = PCI_PROBE_NORMAL;
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if (ppc_md.pci_probe_mode)
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mode = ppc_md.pci_probe_mode(bus);
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DBG(" probe mode: %d\n", mode);
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if (mode == PCI_PROBE_DEVTREE)
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of_scan_bus(node, bus);
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else if (mode == PCI_PROBE_NORMAL)
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pci_scan_child_bus(bus);
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}
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EXPORT_SYMBOL(of_scan_pci_bridge);
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void __devinit scan_phb(struct pci_controller *hose)
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{
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struct pci_bus *bus;
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struct device_node *node = hose->arch_data;
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int i, mode;
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struct resource *res;
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DBG("Scanning PHB %s\n", node ? node->full_name : "<NO NAME>");
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bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, node);
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if (bus == NULL) {
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printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
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hose->global_number);
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return;
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}
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bus->secondary = hose->first_busno;
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hose->bus = bus;
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if (!firmware_has_feature(FW_FEATURE_ISERIES))
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pcibios_map_io_space(bus);
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bus->resource[0] = res = &hose->io_resource;
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if (res->flags && request_resource(&ioport_resource, res)) {
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printk(KERN_ERR "Failed to request PCI IO region "
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"on PCI domain %04x\n", hose->global_number);
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|
DBG("res->start = 0x%016lx, res->end = 0x%016lx\n",
|
|
res->start, res->end);
|
|
}
|
|
|
|
for (i = 0; i < 3; ++i) {
|
|
res = &hose->mem_resources[i];
|
|
bus->resource[i+1] = res;
|
|
if (res->flags && request_resource(&iomem_resource, res))
|
|
printk(KERN_ERR "Failed to request PCI memory region "
|
|
"on PCI domain %04x\n", hose->global_number);
|
|
}
|
|
|
|
mode = PCI_PROBE_NORMAL;
|
|
|
|
if (node && ppc_md.pci_probe_mode)
|
|
mode = ppc_md.pci_probe_mode(bus);
|
|
DBG(" probe mode: %d\n", mode);
|
|
if (mode == PCI_PROBE_DEVTREE) {
|
|
bus->subordinate = hose->last_busno;
|
|
of_scan_bus(node, bus);
|
|
}
|
|
|
|
if (mode == PCI_PROBE_NORMAL)
|
|
hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
|
|
}
|
|
|
|
static int __init pcibios_init(void)
|
|
{
|
|
struct pci_controller *hose, *tmp;
|
|
|
|
/* For now, override phys_mem_access_prot. If we need it,
|
|
* later, we may move that initialization to each ppc_md
|
|
*/
|
|
ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
|
|
|
|
printk(KERN_DEBUG "PCI: Probing PCI hardware\n");
|
|
|
|
/* Scan all of the recorded PCI controllers. */
|
|
list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
|
|
scan_phb(hose);
|
|
pci_bus_add_devices(hose->bus);
|
|
}
|
|
|
|
if (!firmware_has_feature(FW_FEATURE_ISERIES)) {
|
|
if (pci_probe_only)
|
|
pcibios_claim_of_setup();
|
|
else
|
|
/* FIXME: `else' will be removed when
|
|
pci_assign_unassigned_resources() is able to work
|
|
correctly with [partially] allocated PCI tree. */
|
|
pci_assign_unassigned_resources();
|
|
}
|
|
|
|
/* Call machine dependent final fixup */
|
|
if (ppc_md.pcibios_fixup)
|
|
ppc_md.pcibios_fixup();
|
|
|
|
printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
subsys_initcall(pcibios_init);
|
|
|
|
int pcibios_enable_device(struct pci_dev *dev, int mask)
|
|
{
|
|
u16 cmd, oldcmd;
|
|
int i;
|
|
|
|
pci_read_config_word(dev, PCI_COMMAND, &cmd);
|
|
oldcmd = cmd;
|
|
|
|
for (i = 0; i < PCI_NUM_RESOURCES; i++) {
|
|
struct resource *res = &dev->resource[i];
|
|
|
|
/* Only set up the requested stuff */
|
|
if (!(mask & (1<<i)))
|
|
continue;
|
|
|
|
if (res->flags & IORESOURCE_IO)
|
|
cmd |= PCI_COMMAND_IO;
|
|
if (res->flags & IORESOURCE_MEM)
|
|
cmd |= PCI_COMMAND_MEMORY;
|
|
}
|
|
|
|
if (cmd != oldcmd) {
|
|
printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
|
|
pci_name(dev), cmd);
|
|
/* Enable the appropriate bits in the PCI command register. */
|
|
pci_write_config_word(dev, PCI_COMMAND, cmd);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* Decide whether to display the domain number in /proc */
|
|
int pci_proc_domain(struct pci_bus *bus)
|
|
{
|
|
struct pci_controller *hose = pci_bus_to_host(bus);
|
|
return hose->buid != 0;
|
|
}
|
|
|
|
void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
|
|
struct device_node *dev, int prim)
|
|
{
|
|
const unsigned int *ranges;
|
|
unsigned int pci_space;
|
|
unsigned long size;
|
|
int rlen = 0;
|
|
int memno = 0;
|
|
struct resource *res;
|
|
int np, na = of_n_addr_cells(dev);
|
|
unsigned long pci_addr, cpu_phys_addr;
|
|
|
|
np = na + 5;
|
|
|
|
/* From "PCI Binding to 1275"
|
|
* The ranges property is laid out as an array of elements,
|
|
* each of which comprises:
|
|
* cells 0 - 2: a PCI address
|
|
* cells 3 or 3+4: a CPU physical address
|
|
* (size depending on dev->n_addr_cells)
|
|
* cells 4+5 or 5+6: the size of the range
|
|
*/
|
|
ranges = of_get_property(dev, "ranges", &rlen);
|
|
if (ranges == NULL)
|
|
return;
|
|
hose->io_base_phys = 0;
|
|
while ((rlen -= np * sizeof(unsigned int)) >= 0) {
|
|
res = NULL;
|
|
pci_space = ranges[0];
|
|
pci_addr = ((unsigned long)ranges[1] << 32) | ranges[2];
|
|
cpu_phys_addr = of_translate_address(dev, &ranges[3]);
|
|
size = ((unsigned long)ranges[na+3] << 32) | ranges[na+4];
|
|
ranges += np;
|
|
if (size == 0)
|
|
continue;
|
|
|
|
/* Now consume following elements while they are contiguous */
|
|
while (rlen >= np * sizeof(unsigned int)) {
|
|
unsigned long addr, phys;
|
|
|
|
if (ranges[0] != pci_space)
|
|
break;
|
|
addr = ((unsigned long)ranges[1] << 32) | ranges[2];
|
|
phys = ranges[3];
|
|
if (na >= 2)
|
|
phys = (phys << 32) | ranges[4];
|
|
if (addr != pci_addr + size ||
|
|
phys != cpu_phys_addr + size)
|
|
break;
|
|
|
|
size += ((unsigned long)ranges[na+3] << 32)
|
|
| ranges[na+4];
|
|
ranges += np;
|
|
rlen -= np * sizeof(unsigned int);
|
|
}
|
|
|
|
switch ((pci_space >> 24) & 0x3) {
|
|
case 1: /* I/O space */
|
|
hose->io_base_phys = cpu_phys_addr - pci_addr;
|
|
/* handle from 0 to top of I/O window */
|
|
hose->pci_io_size = pci_addr + size;
|
|
|
|
res = &hose->io_resource;
|
|
res->flags = IORESOURCE_IO;
|
|
res->start = pci_addr;
|
|
DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose->global_number,
|
|
res->start, res->start + size - 1);
|
|
break;
|
|
case 2: /* memory space */
|
|
memno = 0;
|
|
while (memno < 3 && hose->mem_resources[memno].flags)
|
|
++memno;
|
|
|
|
if (memno == 0)
|
|
hose->pci_mem_offset = cpu_phys_addr - pci_addr;
|
|
if (memno < 3) {
|
|
res = &hose->mem_resources[memno];
|
|
res->flags = IORESOURCE_MEM;
|
|
res->start = cpu_phys_addr;
|
|
DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose->global_number,
|
|
res->start, res->start + size - 1);
|
|
}
|
|
break;
|
|
}
|
|
if (res != NULL) {
|
|
res->name = dev->full_name;
|
|
res->end = res->start + size - 1;
|
|
res->parent = NULL;
|
|
res->sibling = NULL;
|
|
res->child = NULL;
|
|
}
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_HOTPLUG
|
|
|
|
int pcibios_unmap_io_space(struct pci_bus *bus)
|
|
{
|
|
struct pci_controller *hose;
|
|
|
|
WARN_ON(bus == NULL);
|
|
|
|
/* If this is not a PHB, we only flush the hash table over
|
|
* the area mapped by this bridge. We don't play with the PTE
|
|
* mappings since we might have to deal with sub-page alignemnts
|
|
* so flushing the hash table is the only sane way to make sure
|
|
* that no hash entries are covering that removed bridge area
|
|
* while still allowing other busses overlapping those pages
|
|
*/
|
|
if (bus->self) {
|
|
struct resource *res = bus->resource[0];
|
|
|
|
DBG("IO unmapping for PCI-PCI bridge %s\n",
|
|
pci_name(bus->self));
|
|
|
|
__flush_hash_table_range(&init_mm, res->start + _IO_BASE,
|
|
res->end - res->start + 1);
|
|
return 0;
|
|
}
|
|
|
|
/* Get the host bridge */
|
|
hose = pci_bus_to_host(bus);
|
|
|
|
/* Check if we have IOs allocated */
|
|
if (hose->io_base_alloc == 0)
|
|
return 0;
|
|
|
|
DBG("IO unmapping for PHB %s\n",
|
|
((struct device_node *)hose->arch_data)->full_name);
|
|
DBG(" alloc=0x%p\n", hose->io_base_alloc);
|
|
|
|
/* This is a PHB, we fully unmap the IO area */
|
|
vunmap(hose->io_base_alloc);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pcibios_unmap_io_space);
|
|
|
|
#endif /* CONFIG_HOTPLUG */
|
|
|
|
int __devinit pcibios_map_io_space(struct pci_bus *bus)
|
|
{
|
|
struct vm_struct *area;
|
|
unsigned long phys_page;
|
|
unsigned long size_page;
|
|
unsigned long io_virt_offset;
|
|
struct pci_controller *hose;
|
|
|
|
WARN_ON(bus == NULL);
|
|
|
|
/* If this not a PHB, nothing to do, page tables still exist and
|
|
* thus HPTEs will be faulted in when needed
|
|
*/
|
|
if (bus->self) {
|
|
DBG("IO mapping for PCI-PCI bridge %s\n",
|
|
pci_name(bus->self));
|
|
DBG(" virt=0x%016lx...0x%016lx\n",
|
|
bus->resource[0]->start + _IO_BASE,
|
|
bus->resource[0]->end + _IO_BASE);
|
|
return 0;
|
|
}
|
|
|
|
/* Get the host bridge */
|
|
hose = pci_bus_to_host(bus);
|
|
phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE);
|
|
size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE);
|
|
|
|
/* Make sure IO area address is clear */
|
|
hose->io_base_alloc = NULL;
|
|
|
|
/* If there's no IO to map on that bus, get away too */
|
|
if (hose->pci_io_size == 0 || hose->io_base_phys == 0)
|
|
return 0;
|
|
|
|
/* Let's allocate some IO space for that guy. We don't pass
|
|
* VM_IOREMAP because we don't care about alignment tricks that
|
|
* the core does in that case. Maybe we should due to stupid card
|
|
* with incomplete address decoding but I'd rather not deal with
|
|
* those outside of the reserved 64K legacy region.
|
|
*/
|
|
area = __get_vm_area(size_page, 0, PHB_IO_BASE, PHB_IO_END);
|
|
if (area == NULL)
|
|
return -ENOMEM;
|
|
hose->io_base_alloc = area->addr;
|
|
hose->io_base_virt = (void __iomem *)(area->addr +
|
|
hose->io_base_phys - phys_page);
|
|
|
|
DBG("IO mapping for PHB %s\n",
|
|
((struct device_node *)hose->arch_data)->full_name);
|
|
DBG(" phys=0x%016lx, virt=0x%p (alloc=0x%p)\n",
|
|
hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc);
|
|
DBG(" size=0x%016lx (alloc=0x%016lx)\n",
|
|
hose->pci_io_size, size_page);
|
|
|
|
/* Establish the mapping */
|
|
if (__ioremap_at(phys_page, area->addr, size_page,
|
|
_PAGE_NO_CACHE | _PAGE_GUARDED) == NULL)
|
|
return -ENOMEM;
|
|
|
|
/* Fixup hose IO resource */
|
|
io_virt_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
|
|
hose->io_resource.start += io_virt_offset;
|
|
hose->io_resource.end += io_virt_offset;
|
|
|
|
DBG(" hose->io_resource=0x%016lx...0x%016lx\n",
|
|
hose->io_resource.start, hose->io_resource.end);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pcibios_map_io_space);
|
|
|
|
static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
|
|
{
|
|
struct pci_controller *hose = pci_bus_to_host(dev->bus);
|
|
unsigned long offset;
|
|
|
|
if (res->flags & IORESOURCE_IO) {
|
|
offset = (unsigned long)hose->io_base_virt - _IO_BASE;
|
|
res->start += offset;
|
|
res->end += offset;
|
|
} else if (res->flags & IORESOURCE_MEM) {
|
|
res->start += hose->pci_mem_offset;
|
|
res->end += hose->pci_mem_offset;
|
|
}
|
|
}
|
|
|
|
void __devinit pcibios_fixup_device_resources(struct pci_dev *dev,
|
|
struct pci_bus *bus)
|
|
{
|
|
/* Update device resources. */
|
|
int i;
|
|
|
|
DBG("%s: Fixup resources:\n", pci_name(dev));
|
|
for (i = 0; i < PCI_NUM_RESOURCES; i++) {
|
|
struct resource *res = &dev->resource[i];
|
|
if (!res->flags)
|
|
continue;
|
|
|
|
DBG(" 0x%02x < %08lx:0x%016lx...0x%016lx\n",
|
|
i, res->flags, res->start, res->end);
|
|
|
|
fixup_resource(res, dev);
|
|
|
|
DBG(" > %08lx:0x%016lx...0x%016lx\n",
|
|
res->flags, res->start, res->end);
|
|
}
|
|
}
|
|
EXPORT_SYMBOL(pcibios_fixup_device_resources);
|
|
|
|
void __devinit pcibios_setup_new_device(struct pci_dev *dev)
|
|
{
|
|
struct dev_archdata *sd = &dev->dev.archdata;
|
|
|
|
sd->of_node = pci_device_to_OF_node(dev);
|
|
|
|
DBG("PCI device %s OF node: %s\n", pci_name(dev),
|
|
sd->of_node ? sd->of_node->full_name : "<none>");
|
|
|
|
sd->dma_ops = pci_dma_ops;
|
|
#ifdef CONFIG_NUMA
|
|
sd->numa_node = pcibus_to_node(dev->bus);
|
|
#else
|
|
sd->numa_node = -1;
|
|
#endif
|
|
if (ppc_md.pci_dma_dev_setup)
|
|
ppc_md.pci_dma_dev_setup(dev);
|
|
}
|
|
EXPORT_SYMBOL(pcibios_setup_new_device);
|
|
|
|
static void __devinit do_bus_setup(struct pci_bus *bus)
|
|
{
|
|
struct pci_dev *dev;
|
|
|
|
if (ppc_md.pci_dma_bus_setup)
|
|
ppc_md.pci_dma_bus_setup(bus);
|
|
|
|
list_for_each_entry(dev, &bus->devices, bus_list)
|
|
pcibios_setup_new_device(dev);
|
|
|
|
/* Read default IRQs and fixup if necessary */
|
|
list_for_each_entry(dev, &bus->devices, bus_list) {
|
|
pci_read_irq_line(dev);
|
|
if (ppc_md.pci_irq_fixup)
|
|
ppc_md.pci_irq_fixup(dev);
|
|
}
|
|
}
|
|
|
|
void __devinit pcibios_fixup_bus(struct pci_bus *bus)
|
|
{
|
|
struct pci_dev *dev = bus->self;
|
|
struct device_node *np;
|
|
|
|
np = pci_bus_to_OF_node(bus);
|
|
|
|
DBG("pcibios_fixup_bus(%s)\n", np ? np->full_name : "<???>");
|
|
|
|
if (dev && pci_probe_only &&
|
|
(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
|
|
/* This is a subordinate bridge */
|
|
|
|
pci_read_bridge_bases(bus);
|
|
pcibios_fixup_device_resources(dev, bus);
|
|
}
|
|
|
|
do_bus_setup(bus);
|
|
|
|
if (!pci_probe_only)
|
|
return;
|
|
|
|
list_for_each_entry(dev, &bus->devices, bus_list)
|
|
if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
|
|
pcibios_fixup_device_resources(dev, bus);
|
|
}
|
|
EXPORT_SYMBOL(pcibios_fixup_bus);
|
|
|
|
unsigned long pci_address_to_pio(phys_addr_t address)
|
|
{
|
|
struct pci_controller *hose, *tmp;
|
|
|
|
list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
|
|
if (address >= hose->io_base_phys &&
|
|
address < (hose->io_base_phys + hose->pci_io_size)) {
|
|
unsigned long base =
|
|
(unsigned long)hose->io_base_virt - _IO_BASE;
|
|
return base + (address - hose->io_base_phys);
|
|
}
|
|
}
|
|
return (unsigned int)-1;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pci_address_to_pio);
|
|
|
|
|
|
#define IOBASE_BRIDGE_NUMBER 0
|
|
#define IOBASE_MEMORY 1
|
|
#define IOBASE_IO 2
|
|
#define IOBASE_ISA_IO 3
|
|
#define IOBASE_ISA_MEM 4
|
|
|
|
long sys_pciconfig_iobase(long which, unsigned long in_bus,
|
|
unsigned long in_devfn)
|
|
{
|
|
struct pci_controller* hose;
|
|
struct list_head *ln;
|
|
struct pci_bus *bus = NULL;
|
|
struct device_node *hose_node;
|
|
|
|
/* Argh ! Please forgive me for that hack, but that's the
|
|
* simplest way to get existing XFree to not lockup on some
|
|
* G5 machines... So when something asks for bus 0 io base
|
|
* (bus 0 is HT root), we return the AGP one instead.
|
|
*/
|
|
if (machine_is_compatible("MacRISC4"))
|
|
if (in_bus == 0)
|
|
in_bus = 0xf0;
|
|
|
|
/* That syscall isn't quite compatible with PCI domains, but it's
|
|
* used on pre-domains setup. We return the first match
|
|
*/
|
|
|
|
for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
|
|
bus = pci_bus_b(ln);
|
|
if (in_bus >= bus->number && in_bus <= bus->subordinate)
|
|
break;
|
|
bus = NULL;
|
|
}
|
|
if (bus == NULL || bus->sysdata == NULL)
|
|
return -ENODEV;
|
|
|
|
hose_node = (struct device_node *)bus->sysdata;
|
|
hose = PCI_DN(hose_node)->phb;
|
|
|
|
switch (which) {
|
|
case IOBASE_BRIDGE_NUMBER:
|
|
return (long)hose->first_busno;
|
|
case IOBASE_MEMORY:
|
|
return (long)hose->pci_mem_offset;
|
|
case IOBASE_IO:
|
|
return (long)hose->io_base_phys;
|
|
case IOBASE_ISA_IO:
|
|
return (long)isa_io_base;
|
|
case IOBASE_ISA_MEM:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
#ifdef CONFIG_NUMA
|
|
int pcibus_to_node(struct pci_bus *bus)
|
|
{
|
|
struct pci_controller *phb = pci_bus_to_host(bus);
|
|
return phb->node;
|
|
}
|
|
EXPORT_SYMBOL(pcibus_to_node);
|
|
#endif
|