![Ben Skeggs](/assets/img/avatar_default.png)
Nouveau will no longer load at all if card initialisation fails, so all these checks are unnecessary. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
822 lines
21 KiB
C
822 lines
21 KiB
C
/*
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* Copyright 2007 Dave Airlied
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/*
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* Authors: Dave Airlied <airlied@linux.ie>
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* Ben Skeggs <darktama@iinet.net.au>
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* Jeremy Kolb <jkolb@brandeis.edu>
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*/
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#include "drmP.h"
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#include "nouveau_drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_dma.h"
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#include <linux/log2.h>
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#include <linux/slab.h>
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static void
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nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
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{
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struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
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struct drm_device *dev = dev_priv->dev;
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struct nouveau_bo *nvbo = nouveau_bo(bo);
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ttm_bo_kunmap(&nvbo->kmap);
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if (unlikely(nvbo->gem))
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DRM_ERROR("bo %p still attached to GEM object\n", bo);
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if (nvbo->tile)
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nv10_mem_expire_tiling(dev, nvbo->tile, NULL);
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spin_lock(&dev_priv->ttm.bo_list_lock);
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list_del(&nvbo->head);
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spin_unlock(&dev_priv->ttm.bo_list_lock);
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kfree(nvbo);
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}
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static void
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nouveau_bo_fixup_align(struct drm_device *dev,
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uint32_t tile_mode, uint32_t tile_flags,
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int *align, int *size)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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/*
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* Some of the tile_flags have a periodic structure of N*4096 bytes,
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* align to to that as well as the page size. Align the size to the
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* appropriate boundaries. This does imply that sizes are rounded up
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* 3-7 pages, so be aware of this and do not waste memory by allocating
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* many small buffers.
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*/
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if (dev_priv->card_type == NV_50) {
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uint32_t block_size = dev_priv->vram_size >> 15;
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int i;
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switch (tile_flags) {
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case 0x1800:
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case 0x2800:
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case 0x4800:
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case 0x7a00:
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if (is_power_of_2(block_size)) {
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for (i = 1; i < 10; i++) {
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*align = 12 * i * block_size;
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if (!(*align % 65536))
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break;
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}
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} else {
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for (i = 1; i < 10; i++) {
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*align = 8 * i * block_size;
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if (!(*align % 65536))
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break;
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}
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}
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*size = roundup(*size, *align);
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break;
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default:
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break;
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}
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} else {
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if (tile_mode) {
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if (dev_priv->chipset >= 0x40) {
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*align = 65536;
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*size = roundup(*size, 64 * tile_mode);
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} else if (dev_priv->chipset >= 0x30) {
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*align = 32768;
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*size = roundup(*size, 64 * tile_mode);
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} else if (dev_priv->chipset >= 0x20) {
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*align = 16384;
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*size = roundup(*size, 64 * tile_mode);
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} else if (dev_priv->chipset >= 0x10) {
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*align = 16384;
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*size = roundup(*size, 32 * tile_mode);
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}
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}
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}
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/* ALIGN works only on powers of two. */
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*size = roundup(*size, PAGE_SIZE);
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if (dev_priv->card_type == NV_50) {
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*size = roundup(*size, 65536);
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*align = max(65536, *align);
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}
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}
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int
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nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
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int size, int align, uint32_t flags, uint32_t tile_mode,
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uint32_t tile_flags, bool no_vm, bool mappable,
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struct nouveau_bo **pnvbo)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_bo *nvbo;
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int ret = 0;
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nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
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if (!nvbo)
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return -ENOMEM;
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INIT_LIST_HEAD(&nvbo->head);
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INIT_LIST_HEAD(&nvbo->entry);
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nvbo->mappable = mappable;
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nvbo->no_vm = no_vm;
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nvbo->tile_mode = tile_mode;
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nvbo->tile_flags = tile_flags;
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nouveau_bo_fixup_align(dev, tile_mode, tile_flags, &align, &size);
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align >>= PAGE_SHIFT;
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nvbo->placement.fpfn = 0;
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nvbo->placement.lpfn = mappable ? dev_priv->fb_mappable_pages : 0;
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nouveau_bo_placement_set(nvbo, flags, 0);
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nvbo->channel = chan;
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ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
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ttm_bo_type_device, &nvbo->placement, align, 0,
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false, NULL, size, nouveau_bo_del_ttm);
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if (ret) {
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/* ttm will call nouveau_bo_del_ttm if it fails.. */
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return ret;
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}
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nvbo->channel = NULL;
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spin_lock(&dev_priv->ttm.bo_list_lock);
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list_add_tail(&nvbo->head, &dev_priv->ttm.bo_list);
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spin_unlock(&dev_priv->ttm.bo_list_lock);
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*pnvbo = nvbo;
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return 0;
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}
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static void
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set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
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{
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*n = 0;
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if (type & TTM_PL_FLAG_VRAM)
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pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
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if (type & TTM_PL_FLAG_TT)
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pl[(*n)++] = TTM_PL_FLAG_TT | flags;
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if (type & TTM_PL_FLAG_SYSTEM)
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pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
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}
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void
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nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
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{
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struct ttm_placement *pl = &nvbo->placement;
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uint32_t flags = TTM_PL_MASK_CACHING |
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(nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
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pl->placement = nvbo->placements;
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set_placement_list(nvbo->placements, &pl->num_placement,
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type, flags);
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pl->busy_placement = nvbo->busy_placements;
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set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
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type | busy, flags);
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}
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int
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nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
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{
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struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
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struct ttm_buffer_object *bo = &nvbo->bo;
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int ret;
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if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
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NV_ERROR(nouveau_bdev(bo->bdev)->dev,
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"bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
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1 << bo->mem.mem_type, memtype);
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return -EINVAL;
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}
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if (nvbo->pin_refcnt++)
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return 0;
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ret = ttm_bo_reserve(bo, false, false, false, 0);
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if (ret)
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goto out;
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nouveau_bo_placement_set(nvbo, memtype, 0);
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ret = ttm_bo_validate(bo, &nvbo->placement, false, false, false);
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if (ret == 0) {
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switch (bo->mem.mem_type) {
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case TTM_PL_VRAM:
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dev_priv->fb_aper_free -= bo->mem.size;
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break;
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case TTM_PL_TT:
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dev_priv->gart_info.aper_free -= bo->mem.size;
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break;
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default:
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break;
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}
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}
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ttm_bo_unreserve(bo);
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out:
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if (unlikely(ret))
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nvbo->pin_refcnt--;
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return ret;
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}
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int
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nouveau_bo_unpin(struct nouveau_bo *nvbo)
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{
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struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
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struct ttm_buffer_object *bo = &nvbo->bo;
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int ret;
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if (--nvbo->pin_refcnt)
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return 0;
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ret = ttm_bo_reserve(bo, false, false, false, 0);
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if (ret)
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return ret;
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nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
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ret = ttm_bo_validate(bo, &nvbo->placement, false, false, false);
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if (ret == 0) {
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switch (bo->mem.mem_type) {
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case TTM_PL_VRAM:
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dev_priv->fb_aper_free += bo->mem.size;
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break;
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case TTM_PL_TT:
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dev_priv->gart_info.aper_free += bo->mem.size;
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break;
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default:
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break;
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}
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}
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ttm_bo_unreserve(bo);
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return ret;
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}
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int
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nouveau_bo_map(struct nouveau_bo *nvbo)
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{
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int ret;
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ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
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if (ret)
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return ret;
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ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
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ttm_bo_unreserve(&nvbo->bo);
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return ret;
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}
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void
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nouveau_bo_unmap(struct nouveau_bo *nvbo)
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{
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ttm_bo_kunmap(&nvbo->kmap);
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}
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u16
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nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
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{
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bool is_iomem;
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u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
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mem = &mem[index];
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if (is_iomem)
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return ioread16_native((void __force __iomem *)mem);
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else
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return *mem;
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}
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void
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nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
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{
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bool is_iomem;
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u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
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mem = &mem[index];
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if (is_iomem)
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iowrite16_native(val, (void __force __iomem *)mem);
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else
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*mem = val;
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}
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u32
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nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
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{
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bool is_iomem;
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u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
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mem = &mem[index];
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if (is_iomem)
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return ioread32_native((void __force __iomem *)mem);
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else
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return *mem;
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}
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void
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nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
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{
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bool is_iomem;
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u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
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mem = &mem[index];
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if (is_iomem)
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iowrite32_native(val, (void __force __iomem *)mem);
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else
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*mem = val;
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}
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static struct ttm_backend *
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nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev)
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{
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struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
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struct drm_device *dev = dev_priv->dev;
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switch (dev_priv->gart_info.type) {
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#if __OS_HAS_AGP
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case NOUVEAU_GART_AGP:
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return ttm_agp_backend_init(bdev, dev->agp->bridge);
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#endif
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case NOUVEAU_GART_SGDMA:
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return nouveau_sgdma_init_ttm(dev);
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default:
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NV_ERROR(dev, "Unknown GART type %d\n",
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dev_priv->gart_info.type);
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break;
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}
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return NULL;
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}
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static int
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nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
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{
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/* We'll do this from user space. */
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return 0;
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}
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static int
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nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
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struct ttm_mem_type_manager *man)
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{
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struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
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struct drm_device *dev = dev_priv->dev;
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switch (type) {
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case TTM_PL_SYSTEM:
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man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
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man->available_caching = TTM_PL_MASK_CACHING;
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man->default_caching = TTM_PL_FLAG_CACHED;
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break;
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case TTM_PL_VRAM:
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man->flags = TTM_MEMTYPE_FLAG_FIXED |
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TTM_MEMTYPE_FLAG_MAPPABLE;
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man->available_caching = TTM_PL_FLAG_UNCACHED |
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TTM_PL_FLAG_WC;
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man->default_caching = TTM_PL_FLAG_WC;
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man->gpu_offset = dev_priv->vm_vram_base;
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break;
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case TTM_PL_TT:
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switch (dev_priv->gart_info.type) {
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case NOUVEAU_GART_AGP:
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man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
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man->available_caching = TTM_PL_FLAG_UNCACHED;
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man->default_caching = TTM_PL_FLAG_UNCACHED;
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break;
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case NOUVEAU_GART_SGDMA:
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man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
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TTM_MEMTYPE_FLAG_CMA;
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man->available_caching = TTM_PL_MASK_CACHING;
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man->default_caching = TTM_PL_FLAG_CACHED;
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break;
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default:
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NV_ERROR(dev, "Unknown GART type: %d\n",
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dev_priv->gart_info.type);
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return -EINVAL;
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}
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man->gpu_offset = dev_priv->vm_gart_base;
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break;
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default:
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NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type);
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return -EINVAL;
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}
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return 0;
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}
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static void
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nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
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{
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struct nouveau_bo *nvbo = nouveau_bo(bo);
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switch (bo->mem.mem_type) {
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case TTM_PL_VRAM:
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nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
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TTM_PL_FLAG_SYSTEM);
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break;
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default:
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nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
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break;
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}
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*pl = nvbo->placement;
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}
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/* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
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* TTM_PL_{VRAM,TT} directly.
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*/
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static int
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nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
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struct nouveau_bo *nvbo, bool evict,
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bool no_wait_reserve, bool no_wait_gpu,
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struct ttm_mem_reg *new_mem)
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{
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struct nouveau_fence *fence = NULL;
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int ret;
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ret = nouveau_fence_new(chan, &fence, true);
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if (ret)
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return ret;
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ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL,
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evict || (nvbo->channel &&
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nvbo->channel != chan),
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no_wait_reserve, no_wait_gpu, new_mem);
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nouveau_fence_unref((void *)&fence);
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return ret;
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}
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static inline uint32_t
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nouveau_bo_mem_ctxdma(struct nouveau_bo *nvbo, struct nouveau_channel *chan,
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struct ttm_mem_reg *mem)
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{
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if (chan == nouveau_bdev(nvbo->bo.bdev)->channel) {
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if (mem->mem_type == TTM_PL_TT)
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return NvDmaGART;
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return NvDmaVRAM;
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}
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if (mem->mem_type == TTM_PL_TT)
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return chan->gart_handle;
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return chan->vram_handle;
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}
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static int
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nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
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bool no_wait_reserve, bool no_wait_gpu,
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struct ttm_mem_reg *new_mem)
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{
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struct nouveau_bo *nvbo = nouveau_bo(bo);
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struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
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struct ttm_mem_reg *old_mem = &bo->mem;
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struct nouveau_channel *chan;
|
|
uint64_t src_offset, dst_offset;
|
|
uint32_t page_count;
|
|
int ret;
|
|
|
|
chan = nvbo->channel;
|
|
if (!chan || nvbo->tile_flags || nvbo->no_vm)
|
|
chan = dev_priv->channel;
|
|
|
|
src_offset = old_mem->mm_node->start << PAGE_SHIFT;
|
|
dst_offset = new_mem->mm_node->start << PAGE_SHIFT;
|
|
if (chan != dev_priv->channel) {
|
|
if (old_mem->mem_type == TTM_PL_TT)
|
|
src_offset += dev_priv->vm_gart_base;
|
|
else
|
|
src_offset += dev_priv->vm_vram_base;
|
|
|
|
if (new_mem->mem_type == TTM_PL_TT)
|
|
dst_offset += dev_priv->vm_gart_base;
|
|
else
|
|
dst_offset += dev_priv->vm_vram_base;
|
|
}
|
|
|
|
ret = RING_SPACE(chan, 3);
|
|
if (ret)
|
|
return ret;
|
|
BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
|
|
OUT_RING(chan, nouveau_bo_mem_ctxdma(nvbo, chan, old_mem));
|
|
OUT_RING(chan, nouveau_bo_mem_ctxdma(nvbo, chan, new_mem));
|
|
|
|
if (dev_priv->card_type >= NV_50) {
|
|
ret = RING_SPACE(chan, 4);
|
|
if (ret)
|
|
return ret;
|
|
BEGIN_RING(chan, NvSubM2MF, 0x0200, 1);
|
|
OUT_RING(chan, 1);
|
|
BEGIN_RING(chan, NvSubM2MF, 0x021c, 1);
|
|
OUT_RING(chan, 1);
|
|
}
|
|
|
|
page_count = new_mem->num_pages;
|
|
while (page_count) {
|
|
int line_count = (page_count > 2047) ? 2047 : page_count;
|
|
|
|
if (dev_priv->card_type >= NV_50) {
|
|
ret = RING_SPACE(chan, 3);
|
|
if (ret)
|
|
return ret;
|
|
BEGIN_RING(chan, NvSubM2MF, 0x0238, 2);
|
|
OUT_RING(chan, upper_32_bits(src_offset));
|
|
OUT_RING(chan, upper_32_bits(dst_offset));
|
|
}
|
|
ret = RING_SPACE(chan, 11);
|
|
if (ret)
|
|
return ret;
|
|
BEGIN_RING(chan, NvSubM2MF,
|
|
NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
|
|
OUT_RING(chan, lower_32_bits(src_offset));
|
|
OUT_RING(chan, lower_32_bits(dst_offset));
|
|
OUT_RING(chan, PAGE_SIZE); /* src_pitch */
|
|
OUT_RING(chan, PAGE_SIZE); /* dst_pitch */
|
|
OUT_RING(chan, PAGE_SIZE); /* line_length */
|
|
OUT_RING(chan, line_count);
|
|
OUT_RING(chan, (1<<8)|(1<<0));
|
|
OUT_RING(chan, 0);
|
|
BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
|
|
OUT_RING(chan, 0);
|
|
|
|
page_count -= line_count;
|
|
src_offset += (PAGE_SIZE * line_count);
|
|
dst_offset += (PAGE_SIZE * line_count);
|
|
}
|
|
|
|
return nouveau_bo_move_accel_cleanup(chan, nvbo, evict, no_wait_reserve, no_wait_gpu, new_mem);
|
|
}
|
|
|
|
static int
|
|
nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
|
|
bool no_wait_reserve, bool no_wait_gpu,
|
|
struct ttm_mem_reg *new_mem)
|
|
{
|
|
u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
|
|
struct ttm_placement placement;
|
|
struct ttm_mem_reg tmp_mem;
|
|
int ret;
|
|
|
|
placement.fpfn = placement.lpfn = 0;
|
|
placement.num_placement = placement.num_busy_placement = 1;
|
|
placement.placement = placement.busy_placement = &placement_memtype;
|
|
|
|
tmp_mem = *new_mem;
|
|
tmp_mem.mm_node = NULL;
|
|
ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = ttm_tt_bind(bo->ttm, &tmp_mem);
|
|
if (ret)
|
|
goto out;
|
|
|
|
ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, &tmp_mem);
|
|
if (ret)
|
|
goto out;
|
|
|
|
ret = ttm_bo_move_ttm(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
|
|
out:
|
|
if (tmp_mem.mm_node) {
|
|
spin_lock(&bo->bdev->glob->lru_lock);
|
|
drm_mm_put_block(tmp_mem.mm_node);
|
|
spin_unlock(&bo->bdev->glob->lru_lock);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
|
|
bool no_wait_reserve, bool no_wait_gpu,
|
|
struct ttm_mem_reg *new_mem)
|
|
{
|
|
u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
|
|
struct ttm_placement placement;
|
|
struct ttm_mem_reg tmp_mem;
|
|
int ret;
|
|
|
|
placement.fpfn = placement.lpfn = 0;
|
|
placement.num_placement = placement.num_busy_placement = 1;
|
|
placement.placement = placement.busy_placement = &placement_memtype;
|
|
|
|
tmp_mem = *new_mem;
|
|
tmp_mem.mm_node = NULL;
|
|
ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = ttm_bo_move_ttm(bo, evict, no_wait_reserve, no_wait_gpu, &tmp_mem);
|
|
if (ret)
|
|
goto out;
|
|
|
|
ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
|
|
if (ret)
|
|
goto out;
|
|
|
|
out:
|
|
if (tmp_mem.mm_node) {
|
|
spin_lock(&bo->bdev->glob->lru_lock);
|
|
drm_mm_put_block(tmp_mem.mm_node);
|
|
spin_unlock(&bo->bdev->glob->lru_lock);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
|
|
struct nouveau_tile_reg **new_tile)
|
|
{
|
|
struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
|
|
struct drm_device *dev = dev_priv->dev;
|
|
struct nouveau_bo *nvbo = nouveau_bo(bo);
|
|
uint64_t offset;
|
|
int ret;
|
|
|
|
if (nvbo->no_vm || new_mem->mem_type != TTM_PL_VRAM) {
|
|
/* Nothing to do. */
|
|
*new_tile = NULL;
|
|
return 0;
|
|
}
|
|
|
|
offset = new_mem->mm_node->start << PAGE_SHIFT;
|
|
|
|
if (dev_priv->card_type == NV_50) {
|
|
ret = nv50_mem_vm_bind_linear(dev,
|
|
offset + dev_priv->vm_vram_base,
|
|
new_mem->size, nvbo->tile_flags,
|
|
offset);
|
|
if (ret)
|
|
return ret;
|
|
|
|
} else if (dev_priv->card_type >= NV_10) {
|
|
*new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size,
|
|
nvbo->tile_mode);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
|
|
struct nouveau_tile_reg *new_tile,
|
|
struct nouveau_tile_reg **old_tile)
|
|
{
|
|
struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
|
|
struct drm_device *dev = dev_priv->dev;
|
|
|
|
if (dev_priv->card_type >= NV_10 &&
|
|
dev_priv->card_type < NV_50) {
|
|
if (*old_tile)
|
|
nv10_mem_expire_tiling(dev, *old_tile, bo->sync_obj);
|
|
|
|
*old_tile = new_tile;
|
|
}
|
|
}
|
|
|
|
static int
|
|
nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
|
|
bool no_wait_reserve, bool no_wait_gpu,
|
|
struct ttm_mem_reg *new_mem)
|
|
{
|
|
struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
|
|
struct nouveau_bo *nvbo = nouveau_bo(bo);
|
|
struct ttm_mem_reg *old_mem = &bo->mem;
|
|
struct nouveau_tile_reg *new_tile = NULL;
|
|
int ret = 0;
|
|
|
|
ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Software copy if the card isn't up and running yet. */
|
|
if (!dev_priv->channel) {
|
|
ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
|
|
goto out;
|
|
}
|
|
|
|
/* Fake bo copy. */
|
|
if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
|
|
BUG_ON(bo->mem.mm_node != NULL);
|
|
bo->mem = *new_mem;
|
|
new_mem->mm_node = NULL;
|
|
goto out;
|
|
}
|
|
|
|
/* Hardware assisted copy. */
|
|
if (new_mem->mem_type == TTM_PL_SYSTEM)
|
|
ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
|
|
else if (old_mem->mem_type == TTM_PL_SYSTEM)
|
|
ret = nouveau_bo_move_flips(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
|
|
else
|
|
ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
|
|
|
|
if (!ret)
|
|
goto out;
|
|
|
|
/* Fallback to software copy. */
|
|
ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
|
|
|
|
out:
|
|
if (ret)
|
|
nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
|
|
else
|
|
nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
|
|
{
|
|
struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
|
|
struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
|
|
struct drm_device *dev = dev_priv->dev;
|
|
|
|
mem->bus.addr = NULL;
|
|
mem->bus.offset = 0;
|
|
mem->bus.size = mem->num_pages << PAGE_SHIFT;
|
|
mem->bus.base = 0;
|
|
mem->bus.is_iomem = false;
|
|
if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
|
|
return -EINVAL;
|
|
switch (mem->mem_type) {
|
|
case TTM_PL_SYSTEM:
|
|
/* System memory */
|
|
return 0;
|
|
case TTM_PL_TT:
|
|
#if __OS_HAS_AGP
|
|
if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
|
|
mem->bus.offset = mem->mm_node->start << PAGE_SHIFT;
|
|
mem->bus.base = dev_priv->gart_info.aper_base;
|
|
mem->bus.is_iomem = true;
|
|
}
|
|
#endif
|
|
break;
|
|
case TTM_PL_VRAM:
|
|
mem->bus.offset = mem->mm_node->start << PAGE_SHIFT;
|
|
mem->bus.base = pci_resource_start(dev->pdev, 1);
|
|
mem->bus.is_iomem = true;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
|
|
{
|
|
}
|
|
|
|
static int
|
|
nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
struct ttm_bo_driver nouveau_bo_driver = {
|
|
.create_ttm_backend_entry = nouveau_bo_create_ttm_backend_entry,
|
|
.invalidate_caches = nouveau_bo_invalidate_caches,
|
|
.init_mem_type = nouveau_bo_init_mem_type,
|
|
.evict_flags = nouveau_bo_evict_flags,
|
|
.move = nouveau_bo_move,
|
|
.verify_access = nouveau_bo_verify_access,
|
|
.sync_obj_signaled = nouveau_fence_signalled,
|
|
.sync_obj_wait = nouveau_fence_wait,
|
|
.sync_obj_flush = nouveau_fence_flush,
|
|
.sync_obj_unref = nouveau_fence_unref,
|
|
.sync_obj_ref = nouveau_fence_ref,
|
|
.fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
|
|
.io_mem_reserve = &nouveau_ttm_io_mem_reserve,
|
|
.io_mem_free = &nouveau_ttm_io_mem_free,
|
|
};
|
|
|