959 lines
30 KiB
C
959 lines
30 KiB
C
/*
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* Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/pci.h>
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#include <linux/netdevice.h>
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#include <linux/vmalloc.h>
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#include "ipath_kernel.h"
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#include "ips_common.h"
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/*
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* min buffers we want to have per port, after driver
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*/
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#define IPATH_MIN_USER_PORT_BUFCNT 8
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/*
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* Number of ports we are configured to use (to allow for more pio
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* buffers per port, etc.) Zero means use chip value.
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*/
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static ushort ipath_cfgports;
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module_param_named(cfgports, ipath_cfgports, ushort, S_IRUGO);
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MODULE_PARM_DESC(cfgports, "Set max number of ports to use");
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/*
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* Number of buffers reserved for driver (layered drivers and SMA
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* send). Reserved at end of buffer list. Initialized based on
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* number of PIO buffers if not set via module interface.
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* The problem with this is that it's global, but we'll use different
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* numbers for different chip types. So the default value is not
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* very useful. I've redefined it for the 1.3 release so that it's
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* zero unless set by the user to something else, in which case we
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* try to respect it.
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*/
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static ushort ipath_kpiobufs;
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static int ipath_set_kpiobufs(const char *val, struct kernel_param *kp);
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module_param_call(kpiobufs, ipath_set_kpiobufs, param_get_ushort,
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&ipath_kpiobufs, S_IWUSR | S_IRUGO);
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MODULE_PARM_DESC(kpiobufs, "Set number of PIO buffers for driver");
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/**
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* create_port0_egr - allocate the eager TID buffers
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* @dd: the infinipath device
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*
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* This code is now quite different for user and kernel, because
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* the kernel uses skb's, for the accelerated network performance.
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* This is the kernel (port0) version.
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*
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* Allocate the eager TID buffers and program them into infinipath.
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* We use the network layer alloc_skb() allocator to allocate the
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* memory, and either use the buffers as is for things like SMA
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* packets, or pass the buffers up to the ipath layered driver and
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* thence the network layer, replacing them as we do so (see
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* ipath_rcv_layer()).
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*/
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static int create_port0_egr(struct ipath_devdata *dd)
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{
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unsigned e, egrcnt;
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struct sk_buff **skbs;
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int ret;
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egrcnt = dd->ipath_rcvegrcnt;
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skbs = vmalloc(sizeof(*dd->ipath_port0_skbs) * egrcnt);
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if (skbs == NULL) {
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ipath_dev_err(dd, "allocation error for eager TID "
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"skb array\n");
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ret = -ENOMEM;
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goto bail;
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}
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for (e = 0; e < egrcnt; e++) {
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/*
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* This is a bit tricky in that we allocate extra
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* space for 2 bytes of the 14 byte ethernet header.
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* These two bytes are passed in the ipath header so
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* the rest of the data is word aligned. We allocate
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* 4 bytes so that the data buffer stays word aligned.
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* See ipath_kreceive() for more details.
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*/
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skbs[e] = ipath_alloc_skb(dd, GFP_KERNEL);
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if (!skbs[e]) {
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ipath_dev_err(dd, "SKB allocation error for "
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"eager TID %u\n", e);
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while (e != 0)
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dev_kfree_skb(skbs[--e]);
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ret = -ENOMEM;
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goto bail;
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}
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}
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/*
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* After loop above, so we can test non-NULL to see if ready
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* to use at receive, etc.
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*/
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dd->ipath_port0_skbs = skbs;
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for (e = 0; e < egrcnt; e++) {
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unsigned long phys =
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virt_to_phys(dd->ipath_port0_skbs[e]->data);
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dd->ipath_f_put_tid(dd, e + (u64 __iomem *)
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((char __iomem *) dd->ipath_kregbase +
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dd->ipath_rcvegrbase), 0, phys);
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}
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ret = 0;
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bail:
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return ret;
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}
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static int bringup_link(struct ipath_devdata *dd)
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{
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u64 val, ibc;
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int ret = 0;
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/* hold IBC in reset */
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dd->ipath_control &= ~INFINIPATH_C_LINKENABLE;
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ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
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dd->ipath_control);
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/*
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* Note that prior to try 14 or 15 of IB, the credit scaling
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* wasn't working, because it was swapped for writes with the
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* 1 bit default linkstate field
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*/
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/* ignore pbc and align word */
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val = dd->ipath_piosize2k - 2 * sizeof(u32);
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/*
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* for ICRC, which we only send in diag test pkt mode, and we
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* don't need to worry about that for mtu
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*/
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val += 1;
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/*
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* Set the IBC maxpktlength to the size of our pio buffers the
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* maxpktlength is in words. This is *not* the IB data MTU.
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*/
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ibc = (val / sizeof(u32)) << INFINIPATH_IBCC_MAXPKTLEN_SHIFT;
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/* in KB */
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ibc |= 0x5ULL << INFINIPATH_IBCC_FLOWCTRLWATERMARK_SHIFT;
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/*
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* How often flowctrl sent. More or less in usecs; balance against
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* watermark value, so that in theory senders always get a flow
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* control update in time to not let the IB link go idle.
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*/
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ibc |= 0x3ULL << INFINIPATH_IBCC_FLOWCTRLPERIOD_SHIFT;
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/* max error tolerance */
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ibc |= 0xfULL << INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT;
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/* use "real" buffer space for */
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ibc |= 4ULL << INFINIPATH_IBCC_CREDITSCALE_SHIFT;
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/* IB credit flow control. */
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ibc |= 0xfULL << INFINIPATH_IBCC_OVERRUNTHRESHOLD_SHIFT;
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/* initially come up waiting for TS1, without sending anything. */
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dd->ipath_ibcctrl = ibc;
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/*
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* Want to start out with both LINKCMD and LINKINITCMD in NOP
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* (0 and 0). Don't put linkinitcmd in ipath_ibcctrl, want that
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* to stay a NOP
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*/
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ibc |= INFINIPATH_IBCC_LINKINITCMD_DISABLE <<
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INFINIPATH_IBCC_LINKINITCMD_SHIFT;
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ipath_cdbg(VERBOSE, "Writing 0x%llx to ibcctrl\n",
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(unsigned long long) ibc);
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ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl, ibc);
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// be sure chip saw it
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val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
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ret = dd->ipath_f_bringup_serdes(dd);
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if (ret)
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dev_info(&dd->pcidev->dev, "Could not initialize SerDes, "
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"not usable\n");
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else {
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/* enable IBC */
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dd->ipath_control |= INFINIPATH_C_LINKENABLE;
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ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
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dd->ipath_control);
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}
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return ret;
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}
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static int init_chip_first(struct ipath_devdata *dd,
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struct ipath_portdata **pdp)
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{
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struct ipath_portdata *pd = NULL;
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int ret = 0;
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u64 val;
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/*
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* skip cfgports stuff because we are not allocating memory,
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* and we don't want problems if the portcnt changed due to
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* cfgports. We do still check and report a difference, if
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* not same (should be impossible).
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*/
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dd->ipath_portcnt =
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ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
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if (!ipath_cfgports)
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dd->ipath_cfgports = dd->ipath_portcnt;
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else if (ipath_cfgports <= dd->ipath_portcnt) {
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dd->ipath_cfgports = ipath_cfgports;
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ipath_dbg("Configured to use %u ports out of %u in chip\n",
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dd->ipath_cfgports, dd->ipath_portcnt);
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} else {
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dd->ipath_cfgports = dd->ipath_portcnt;
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ipath_dbg("Tried to configured to use %u ports; chip "
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"only supports %u\n", ipath_cfgports,
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dd->ipath_portcnt);
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}
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dd->ipath_pd = kzalloc(sizeof(*dd->ipath_pd) * dd->ipath_cfgports,
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GFP_KERNEL);
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if (!dd->ipath_pd) {
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ipath_dev_err(dd, "Unable to allocate portdata array, "
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"failing\n");
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ret = -ENOMEM;
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goto done;
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}
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dd->ipath_lastegrheads = kzalloc(sizeof(*dd->ipath_lastegrheads)
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* dd->ipath_cfgports,
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GFP_KERNEL);
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dd->ipath_lastrcvhdrqtails =
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kzalloc(sizeof(*dd->ipath_lastrcvhdrqtails)
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* dd->ipath_cfgports, GFP_KERNEL);
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if (!dd->ipath_lastegrheads || !dd->ipath_lastrcvhdrqtails) {
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ipath_dev_err(dd, "Unable to allocate head arrays, "
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"failing\n");
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ret = -ENOMEM;
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goto done;
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}
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dd->ipath_pd[0] = kzalloc(sizeof(*pd), GFP_KERNEL);
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if (!dd->ipath_pd[0]) {
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ipath_dev_err(dd, "Unable to allocate portdata for port "
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"0, failing\n");
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ret = -ENOMEM;
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goto done;
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}
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pd = dd->ipath_pd[0];
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pd->port_dd = dd;
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pd->port_port = 0;
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pd->port_cnt = 1;
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/* The port 0 pkey table is used by the layer interface. */
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pd->port_pkeys[0] = IPS_DEFAULT_P_KEY;
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dd->ipath_rcvtidcnt =
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ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
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dd->ipath_rcvtidbase =
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ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
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dd->ipath_rcvegrcnt =
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ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
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dd->ipath_rcvegrbase =
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ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
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dd->ipath_palign =
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ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
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dd->ipath_piobufbase =
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ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufbase);
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val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiosize);
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dd->ipath_piosize2k = val & ~0U;
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dd->ipath_piosize4k = val >> 32;
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dd->ipath_ibmtu = 4096; /* default to largest legal MTU */
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val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufcnt);
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dd->ipath_piobcnt2k = val & ~0U;
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dd->ipath_piobcnt4k = val >> 32;
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dd->ipath_pio2kbase =
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(u32 __iomem *) (((char __iomem *) dd->ipath_kregbase) +
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(dd->ipath_piobufbase & 0xffffffff));
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if (dd->ipath_piobcnt4k) {
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dd->ipath_pio4kbase = (u32 __iomem *)
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(((char __iomem *) dd->ipath_kregbase) +
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(dd->ipath_piobufbase >> 32));
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/*
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* 4K buffers take 2 pages; we use roundup just to be
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* paranoid; we calculate it once here, rather than on
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* ever buf allocate
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*/
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dd->ipath_4kalign = ALIGN(dd->ipath_piosize4k,
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dd->ipath_palign);
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ipath_dbg("%u 2k(%x) piobufs @ %p, %u 4k(%x) @ %p "
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"(%x aligned)\n",
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dd->ipath_piobcnt2k, dd->ipath_piosize2k,
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dd->ipath_pio2kbase, dd->ipath_piobcnt4k,
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dd->ipath_piosize4k, dd->ipath_pio4kbase,
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dd->ipath_4kalign);
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}
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else ipath_dbg("%u 2k piobufs @ %p\n",
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dd->ipath_piobcnt2k, dd->ipath_pio2kbase);
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spin_lock_init(&dd->ipath_tid_lock);
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done:
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*pdp = pd;
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return ret;
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}
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/**
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* init_chip_reset - re-initialize after a reset, or enable
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* @dd: the infinipath device
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* @pdp: output for port data
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*
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* sanity check at least some of the values after reset, and
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* ensure no receive or transmit (explictly, in case reset
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* failed
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*/
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static int init_chip_reset(struct ipath_devdata *dd,
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struct ipath_portdata **pdp)
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{
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struct ipath_portdata *pd;
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u32 rtmp;
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*pdp = pd = dd->ipath_pd[0];
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/* ensure chip does no sends or receives while we re-initialize */
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dd->ipath_control = dd->ipath_sendctrl = dd->ipath_rcvctrl = 0U;
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ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl, 0);
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ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, 0);
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ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0);
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rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
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if (dd->ipath_portcnt != rtmp)
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dev_info(&dd->pcidev->dev, "portcnt was %u before "
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"reset, now %u, using original\n",
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dd->ipath_portcnt, rtmp);
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rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
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if (rtmp != dd->ipath_rcvtidcnt)
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dev_info(&dd->pcidev->dev, "tidcnt was %u before "
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"reset, now %u, using original\n",
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dd->ipath_rcvtidcnt, rtmp);
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rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
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if (rtmp != dd->ipath_rcvtidbase)
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dev_info(&dd->pcidev->dev, "tidbase was %u before "
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"reset, now %u, using original\n",
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dd->ipath_rcvtidbase, rtmp);
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rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
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if (rtmp != dd->ipath_rcvegrcnt)
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dev_info(&dd->pcidev->dev, "egrcnt was %u before "
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"reset, now %u, using original\n",
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dd->ipath_rcvegrcnt, rtmp);
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rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
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if (rtmp != dd->ipath_rcvegrbase)
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dev_info(&dd->pcidev->dev, "egrbase was %u before "
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"reset, now %u, using original\n",
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dd->ipath_rcvegrbase, rtmp);
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return 0;
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}
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static int init_pioavailregs(struct ipath_devdata *dd)
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{
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int ret;
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dd->ipath_pioavailregs_dma = dma_alloc_coherent(
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&dd->pcidev->dev, PAGE_SIZE, &dd->ipath_pioavailregs_phys,
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GFP_KERNEL);
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if (!dd->ipath_pioavailregs_dma) {
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ipath_dev_err(dd, "failed to allocate PIOavail reg area "
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"in memory\n");
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ret = -ENOMEM;
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goto done;
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}
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/*
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* we really want L2 cache aligned, but for current CPUs of
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* interest, they are the same.
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*/
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dd->ipath_statusp = (u64 *)
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((char *)dd->ipath_pioavailregs_dma +
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((2 * L1_CACHE_BYTES +
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dd->ipath_pioavregs * sizeof(u64)) & ~L1_CACHE_BYTES));
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/* copy the current value now that it's really allocated */
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*dd->ipath_statusp = dd->_ipath_status;
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/*
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* setup buffer to hold freeze msg, accessible to apps,
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* following statusp
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*/
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dd->ipath_freezemsg = (char *)&dd->ipath_statusp[1];
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/* and its length */
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dd->ipath_freezelen = L1_CACHE_BYTES - sizeof(dd->ipath_statusp[0]);
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if (dd->ipath_unit * 64 > (IPATH_PORT0_RCVHDRTAIL_SIZE - 64)) {
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ipath_dev_err(dd, "unit %u too large for port 0 "
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"rcvhdrtail buffer size\n", dd->ipath_unit);
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ret = -ENODEV;
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}
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else
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ret = 0;
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/* so we can get current tail in ipath_kreceive(), per chip */
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dd->ipath_hdrqtailptr = &ipath_port0_rcvhdrtail[
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dd->ipath_unit * (64 / sizeof(*ipath_port0_rcvhdrtail))];
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done:
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return ret;
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}
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/**
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* init_shadow_tids - allocate the shadow TID array
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* @dd: the infinipath device
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*
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* allocate the shadow TID array, so we can ipath_munlock previous
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* entries. It may make more sense to move the pageshadow to the
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* port data structure, so we only allocate memory for ports actually
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* in use, since we at 8k per port, now.
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*/
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static void init_shadow_tids(struct ipath_devdata *dd)
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{
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dd->ipath_pageshadow = (struct page **)
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vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
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sizeof(struct page *));
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if (!dd->ipath_pageshadow)
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ipath_dev_err(dd, "failed to allocate shadow page * "
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"array, no expected sends!\n");
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else
|
|
memset(dd->ipath_pageshadow, 0,
|
|
dd->ipath_cfgports * dd->ipath_rcvtidcnt *
|
|
sizeof(struct page *));
|
|
}
|
|
|
|
static void enable_chip(struct ipath_devdata *dd,
|
|
struct ipath_portdata *pd, int reinit)
|
|
{
|
|
u32 val;
|
|
int i;
|
|
|
|
if (!reinit) {
|
|
init_waitqueue_head(&ipath_sma_state_wait);
|
|
}
|
|
ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
|
|
dd->ipath_rcvctrl);
|
|
|
|
/* Enable PIO send, and update of PIOavail regs to memory. */
|
|
dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE |
|
|
INFINIPATH_S_PIOBUFAVAILUPD;
|
|
ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
|
|
dd->ipath_sendctrl);
|
|
|
|
/*
|
|
* enable port 0 receive, and receive interrupt. other ports
|
|
* done as user opens and inits them.
|
|
*/
|
|
dd->ipath_rcvctrl = INFINIPATH_R_TAILUPD |
|
|
(1ULL << INFINIPATH_R_PORTENABLE_SHIFT) |
|
|
(1ULL << INFINIPATH_R_INTRAVAIL_SHIFT);
|
|
ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
|
|
dd->ipath_rcvctrl);
|
|
|
|
/*
|
|
* now ready for use. this should be cleared whenever we
|
|
* detect a reset, or initiate one.
|
|
*/
|
|
dd->ipath_flags |= IPATH_INITTED;
|
|
|
|
/*
|
|
* init our shadow copies of head from tail values, and write
|
|
* head values to match.
|
|
*/
|
|
val = ipath_read_ureg32(dd, ur_rcvegrindextail, 0);
|
|
(void)ipath_write_ureg(dd, ur_rcvegrindexhead, val, 0);
|
|
dd->ipath_port0head = ipath_read_ureg32(dd, ur_rcvhdrtail, 0);
|
|
|
|
/* Initialize so we interrupt on next packet received */
|
|
(void)ipath_write_ureg(dd, ur_rcvhdrhead,
|
|
dd->ipath_rhdrhead_intr_off |
|
|
dd->ipath_port0head, 0);
|
|
|
|
/*
|
|
* by now pioavail updates to memory should have occurred, so
|
|
* copy them into our working/shadow registers; this is in
|
|
* case something went wrong with abort, but mostly to get the
|
|
* initial values of the generation bit correct.
|
|
*/
|
|
for (i = 0; i < dd->ipath_pioavregs; i++) {
|
|
__le64 val;
|
|
|
|
/*
|
|
* Chip Errata bug 6641; even and odd qwords>3 are swapped.
|
|
*/
|
|
if (i > 3) {
|
|
if (i & 1)
|
|
val = dd->ipath_pioavailregs_dma[i - 1];
|
|
else
|
|
val = dd->ipath_pioavailregs_dma[i + 1];
|
|
}
|
|
else
|
|
val = dd->ipath_pioavailregs_dma[i];
|
|
dd->ipath_pioavailshadow[i] = le64_to_cpu(val);
|
|
}
|
|
/* can get counters, stats, etc. */
|
|
dd->ipath_flags |= IPATH_PRESENT;
|
|
}
|
|
|
|
static int init_housekeeping(struct ipath_devdata *dd,
|
|
struct ipath_portdata **pdp, int reinit)
|
|
{
|
|
char boardn[32];
|
|
int ret = 0;
|
|
|
|
/*
|
|
* have to clear shadow copies of registers at init that are
|
|
* not otherwise set here, or all kinds of bizarre things
|
|
* happen with driver on chip reset
|
|
*/
|
|
dd->ipath_rcvhdrsize = 0;
|
|
|
|
/*
|
|
* Don't clear ipath_flags as 8bit mode was set before
|
|
* entering this func. However, we do set the linkstate to
|
|
* unknown, so we can watch for a transition.
|
|
* PRESENT is set because we want register reads to work,
|
|
* and the kernel infrastructure saw it in config space;
|
|
* We clear it if we have failures.
|
|
*/
|
|
dd->ipath_flags |= IPATH_LINKUNK | IPATH_PRESENT;
|
|
dd->ipath_flags &= ~(IPATH_LINKACTIVE | IPATH_LINKARMED |
|
|
IPATH_LINKDOWN | IPATH_LINKINIT);
|
|
|
|
ipath_cdbg(VERBOSE, "Try to read spc chip revision\n");
|
|
dd->ipath_revision =
|
|
ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
|
|
|
|
/*
|
|
* set up fundamental info we need to use the chip; we assume
|
|
* if the revision reg and these regs are OK, we don't need to
|
|
* special case the rest
|
|
*/
|
|
dd->ipath_sregbase =
|
|
ipath_read_kreg32(dd, dd->ipath_kregs->kr_sendregbase);
|
|
dd->ipath_cregbase =
|
|
ipath_read_kreg32(dd, dd->ipath_kregs->kr_counterregbase);
|
|
dd->ipath_uregbase =
|
|
ipath_read_kreg32(dd, dd->ipath_kregs->kr_userregbase);
|
|
ipath_cdbg(VERBOSE, "ipath_kregbase %p, sendbase %x usrbase %x, "
|
|
"cntrbase %x\n", dd->ipath_kregbase, dd->ipath_sregbase,
|
|
dd->ipath_uregbase, dd->ipath_cregbase);
|
|
if ((dd->ipath_revision & 0xffffffff) == 0xffffffff
|
|
|| (dd->ipath_sregbase & 0xffffffff) == 0xffffffff
|
|
|| (dd->ipath_cregbase & 0xffffffff) == 0xffffffff
|
|
|| (dd->ipath_uregbase & 0xffffffff) == 0xffffffff) {
|
|
ipath_dev_err(dd, "Register read failures from chip, "
|
|
"giving up initialization\n");
|
|
dd->ipath_flags &= ~IPATH_PRESENT;
|
|
ret = -ENODEV;
|
|
goto done;
|
|
}
|
|
|
|
/* clear the initial reset flag, in case first driver load */
|
|
ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear,
|
|
INFINIPATH_E_RESET);
|
|
|
|
if (reinit)
|
|
ret = init_chip_reset(dd, pdp);
|
|
else
|
|
ret = init_chip_first(dd, pdp);
|
|
|
|
if (ret)
|
|
goto done;
|
|
|
|
ipath_cdbg(VERBOSE, "Revision %llx (PCI %x), %u ports, %u tids, "
|
|
"%u egrtids\n", (unsigned long long) dd->ipath_revision,
|
|
dd->ipath_pcirev, dd->ipath_portcnt, dd->ipath_rcvtidcnt,
|
|
dd->ipath_rcvegrcnt);
|
|
|
|
if (((dd->ipath_revision >> INFINIPATH_R_SOFTWARE_SHIFT) &
|
|
INFINIPATH_R_SOFTWARE_MASK) != IPATH_CHIP_SWVERSION) {
|
|
ipath_dev_err(dd, "Driver only handles version %d, "
|
|
"chip swversion is %d (%llx), failng\n",
|
|
IPATH_CHIP_SWVERSION,
|
|
(int)(dd->ipath_revision >>
|
|
INFINIPATH_R_SOFTWARE_SHIFT) &
|
|
INFINIPATH_R_SOFTWARE_MASK,
|
|
(unsigned long long) dd->ipath_revision);
|
|
ret = -ENOSYS;
|
|
goto done;
|
|
}
|
|
dd->ipath_majrev = (u8) ((dd->ipath_revision >>
|
|
INFINIPATH_R_CHIPREVMAJOR_SHIFT) &
|
|
INFINIPATH_R_CHIPREVMAJOR_MASK);
|
|
dd->ipath_minrev = (u8) ((dd->ipath_revision >>
|
|
INFINIPATH_R_CHIPREVMINOR_SHIFT) &
|
|
INFINIPATH_R_CHIPREVMINOR_MASK);
|
|
dd->ipath_boardrev = (u8) ((dd->ipath_revision >>
|
|
INFINIPATH_R_BOARDID_SHIFT) &
|
|
INFINIPATH_R_BOARDID_MASK);
|
|
|
|
ret = dd->ipath_f_get_boardname(dd, boardn, sizeof boardn);
|
|
|
|
snprintf(dd->ipath_boardversion, sizeof(dd->ipath_boardversion),
|
|
"Driver %u.%u, %s, InfiniPath%u %u.%u, PCI %u, "
|
|
"SW Compat %u\n",
|
|
IPATH_CHIP_VERS_MAJ, IPATH_CHIP_VERS_MIN, boardn,
|
|
(unsigned)(dd->ipath_revision >> INFINIPATH_R_ARCH_SHIFT) &
|
|
INFINIPATH_R_ARCH_MASK,
|
|
dd->ipath_majrev, dd->ipath_minrev, dd->ipath_pcirev,
|
|
(unsigned)(dd->ipath_revision >>
|
|
INFINIPATH_R_SOFTWARE_SHIFT) &
|
|
INFINIPATH_R_SOFTWARE_MASK);
|
|
|
|
ipath_dbg("%s", dd->ipath_boardversion);
|
|
|
|
done:
|
|
return ret;
|
|
}
|
|
|
|
|
|
/**
|
|
* ipath_init_chip - do the actual initialization sequence on the chip
|
|
* @dd: the infinipath device
|
|
* @reinit: reinitializing, so don't allocate new memory
|
|
*
|
|
* Do the actual initialization sequence on the chip. This is done
|
|
* both from the init routine called from the PCI infrastructure, and
|
|
* when we reset the chip, or detect that it was reset internally,
|
|
* or it's administratively re-enabled.
|
|
*
|
|
* Memory allocation here and in called routines is only done in
|
|
* the first case (reinit == 0). We have to be careful, because even
|
|
* without memory allocation, we need to re-write all the chip registers
|
|
* TIDs, etc. after the reset or enable has completed.
|
|
*/
|
|
int ipath_init_chip(struct ipath_devdata *dd, int reinit)
|
|
{
|
|
int ret = 0, i;
|
|
u32 val32, kpiobufs;
|
|
u64 val, atmp;
|
|
struct ipath_portdata *pd = NULL; /* keep gcc4 happy */
|
|
|
|
ret = init_housekeeping(dd, &pd, reinit);
|
|
if (ret)
|
|
goto done;
|
|
|
|
/*
|
|
* we ignore most issues after reporting them, but have to specially
|
|
* handle hardware-disabled chips.
|
|
*/
|
|
if (ret == 2) {
|
|
/* unique error, known to ipath_init_one */
|
|
ret = -EPERM;
|
|
goto done;
|
|
}
|
|
|
|
/*
|
|
* We could bump this to allow for full rcvegrcnt + rcvtidcnt,
|
|
* but then it no longer nicely fits power of two, and since
|
|
* we now use routines that backend onto __get_free_pages, the
|
|
* rest would be wasted.
|
|
*/
|
|
dd->ipath_rcvhdrcnt = dd->ipath_rcvegrcnt;
|
|
ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrcnt,
|
|
dd->ipath_rcvhdrcnt);
|
|
|
|
/*
|
|
* Set up the shadow copies of the piobufavail registers,
|
|
* which we compare against the chip registers for now, and
|
|
* the in memory DMA'ed copies of the registers. This has to
|
|
* be done early, before we calculate lastport, etc.
|
|
*/
|
|
val = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
|
|
/*
|
|
* calc number of pioavail registers, and save it; we have 2
|
|
* bits per buffer.
|
|
*/
|
|
dd->ipath_pioavregs = ALIGN(val, sizeof(u64) * BITS_PER_BYTE / 2)
|
|
/ (sizeof(u64) * BITS_PER_BYTE / 2);
|
|
if (ipath_kpiobufs == 0) {
|
|
/* not set by user, or set explictly to default */
|
|
if ((dd->ipath_piobcnt2k + dd->ipath_piobcnt4k) > 128)
|
|
kpiobufs = 32;
|
|
else
|
|
kpiobufs = 16;
|
|
}
|
|
else
|
|
kpiobufs = ipath_kpiobufs;
|
|
|
|
if (kpiobufs >
|
|
(dd->ipath_piobcnt2k + dd->ipath_piobcnt4k -
|
|
(dd->ipath_cfgports * IPATH_MIN_USER_PORT_BUFCNT))) {
|
|
i = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k -
|
|
(dd->ipath_cfgports * IPATH_MIN_USER_PORT_BUFCNT);
|
|
if (i < 0)
|
|
i = 0;
|
|
dev_info(&dd->pcidev->dev, "Allocating %d PIO bufs for "
|
|
"kernel leaves too few for %d user ports "
|
|
"(%d each); using %u\n", kpiobufs,
|
|
dd->ipath_cfgports - 1,
|
|
IPATH_MIN_USER_PORT_BUFCNT, i);
|
|
/*
|
|
* shouldn't change ipath_kpiobufs, because could be
|
|
* different for different devices...
|
|
*/
|
|
kpiobufs = i;
|
|
}
|
|
dd->ipath_lastport_piobuf =
|
|
dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - kpiobufs;
|
|
dd->ipath_pbufsport = dd->ipath_cfgports > 1
|
|
? dd->ipath_lastport_piobuf / (dd->ipath_cfgports - 1)
|
|
: 0;
|
|
val32 = dd->ipath_lastport_piobuf -
|
|
(dd->ipath_pbufsport * (dd->ipath_cfgports - 1));
|
|
if (val32 > 0) {
|
|
ipath_dbg("allocating %u pbufs/port leaves %u unused, "
|
|
"add to kernel\n", dd->ipath_pbufsport, val32);
|
|
dd->ipath_lastport_piobuf -= val32;
|
|
ipath_dbg("%u pbufs/port leaves %u unused, add to kernel\n",
|
|
dd->ipath_pbufsport, val32);
|
|
}
|
|
dd->ipath_lastpioindex = dd->ipath_lastport_piobuf;
|
|
ipath_cdbg(VERBOSE, "%d PIO bufs for kernel out of %d total %u "
|
|
"each for %u user ports\n", kpiobufs,
|
|
dd->ipath_piobcnt2k + dd->ipath_piobcnt4k,
|
|
dd->ipath_pbufsport, dd->ipath_cfgports - 1);
|
|
|
|
dd->ipath_f_early_init(dd);
|
|
|
|
/* early_init sets rcvhdrentsize and rcvhdrsize, so this must be
|
|
* done after early_init */
|
|
dd->ipath_hdrqlast =
|
|
dd->ipath_rcvhdrentsize * (dd->ipath_rcvhdrcnt - 1);
|
|
ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrentsize,
|
|
dd->ipath_rcvhdrentsize);
|
|
ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize,
|
|
dd->ipath_rcvhdrsize);
|
|
|
|
if (!reinit) {
|
|
ret = init_pioavailregs(dd);
|
|
init_shadow_tids(dd);
|
|
if (ret)
|
|
goto done;
|
|
}
|
|
|
|
(void)ipath_write_kreg(dd, dd->ipath_kregs->kr_sendpioavailaddr,
|
|
dd->ipath_pioavailregs_phys);
|
|
/*
|
|
* this is to detect s/w errors, which the h/w works around by
|
|
* ignoring the low 6 bits of address, if it wasn't aligned.
|
|
*/
|
|
val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpioavailaddr);
|
|
if (val != dd->ipath_pioavailregs_phys) {
|
|
ipath_dev_err(dd, "Catastrophic software error, "
|
|
"SendPIOAvailAddr written as %lx, "
|
|
"read back as %llx\n",
|
|
(unsigned long) dd->ipath_pioavailregs_phys,
|
|
(unsigned long long) val);
|
|
ret = -EINVAL;
|
|
goto done;
|
|
}
|
|
|
|
val = ipath_port0_rcvhdrtail_dma + dd->ipath_unit * 64;
|
|
|
|
/* verify that the alignment requirement was met */
|
|
ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdrtailaddr,
|
|
0, val);
|
|
atmp = ipath_read_kreg64_port(
|
|
dd, dd->ipath_kregs->kr_rcvhdrtailaddr, 0);
|
|
if (val != atmp) {
|
|
ipath_dev_err(dd, "Catastrophic software error, "
|
|
"RcvHdrTailAddr0 written as %llx, "
|
|
"read back as %llx from %x\n",
|
|
(unsigned long long) val,
|
|
(unsigned long long) atmp,
|
|
dd->ipath_kregs->kr_rcvhdrtailaddr);
|
|
ret = -EINVAL;
|
|
goto done;
|
|
}
|
|
|
|
ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvbthqp, IPATH_KD_QP);
|
|
|
|
/*
|
|
* make sure we are not in freeze, and PIO send enabled, so
|
|
* writes to pbc happen
|
|
*/
|
|
ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, 0ULL);
|
|
ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
|
|
~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
|
|
ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0ULL);
|
|
ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
|
|
INFINIPATH_S_PIOENABLE);
|
|
|
|
/*
|
|
* before error clears, since we expect serdes pll errors during
|
|
* this, the first time after reset
|
|
*/
|
|
if (bringup_link(dd)) {
|
|
dev_info(&dd->pcidev->dev, "Failed to bringup IB link\n");
|
|
ret = -ENETDOWN;
|
|
goto done;
|
|
}
|
|
|
|
/*
|
|
* clear any "expected" hwerrs from reset and/or initialization
|
|
* clear any that aren't enabled (at least this once), and then
|
|
* set the enable mask
|
|
*/
|
|
dd->ipath_f_init_hwerrors(dd);
|
|
ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
|
|
~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
|
|
ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
|
|
dd->ipath_hwerrmask);
|
|
|
|
dd->ipath_maskederrs = dd->ipath_ignorederrs;
|
|
/* clear all */
|
|
ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL);
|
|
/* enable errors that are masked, at least this first time. */
|
|
ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
|
|
~dd->ipath_maskederrs);
|
|
/* clear any interrups up to this point (ints still not enabled) */
|
|
ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL);
|
|
|
|
ipath_stats.sps_lid[dd->ipath_unit] = dd->ipath_lid;
|
|
|
|
/*
|
|
* Set up the port 0 (kernel) rcvhdr q and egr TIDs. If doing
|
|
* re-init, the simplest way to handle this is to free
|
|
* existing, and re-allocate.
|
|
*/
|
|
if (reinit)
|
|
ipath_free_pddata(dd, 0, 0);
|
|
dd->ipath_f_tidtemplate(dd);
|
|
ret = ipath_create_rcvhdrq(dd, pd);
|
|
if (!ret)
|
|
ret = create_port0_egr(dd);
|
|
if (ret)
|
|
ipath_dev_err(dd, "failed to allocate port 0 (kernel) "
|
|
"rcvhdrq and/or egr bufs\n");
|
|
else
|
|
enable_chip(dd, pd, reinit);
|
|
|
|
/*
|
|
* cause retrigger of pending interrupts ignored during init,
|
|
* even if we had errors
|
|
*/
|
|
ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL);
|
|
|
|
if(!dd->ipath_stats_timer_active) {
|
|
/*
|
|
* first init, or after an admin disable/enable
|
|
* set up stats retrieval timer, even if we had errors
|
|
* in last portion of setup
|
|
*/
|
|
init_timer(&dd->ipath_stats_timer);
|
|
dd->ipath_stats_timer.function = ipath_get_faststats;
|
|
dd->ipath_stats_timer.data = (unsigned long) dd;
|
|
/* every 5 seconds; */
|
|
dd->ipath_stats_timer.expires = jiffies + 5 * HZ;
|
|
/* takes ~16 seconds to overflow at full IB 4x bandwdith */
|
|
add_timer(&dd->ipath_stats_timer);
|
|
dd->ipath_stats_timer_active = 1;
|
|
}
|
|
|
|
done:
|
|
if (!ret) {
|
|
*dd->ipath_statusp |= IPATH_STATUS_CHIP_PRESENT;
|
|
if (!dd->ipath_f_intrsetup(dd)) {
|
|
/* now we can enable all interrupts from the chip */
|
|
ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask,
|
|
-1LL);
|
|
/* force re-interrupt of any pending interrupts. */
|
|
ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear,
|
|
0ULL);
|
|
/* chip is usable; mark it as initialized */
|
|
*dd->ipath_statusp |= IPATH_STATUS_INITTED;
|
|
} else
|
|
ipath_dev_err(dd, "No interrupts enabled, couldn't "
|
|
"setup interrupt address\n");
|
|
|
|
if (dd->ipath_cfgports > ipath_stats.sps_nports)
|
|
/*
|
|
* sps_nports is a global, so, we set it to
|
|
* the highest number of ports of any of the
|
|
* chips we find; we never decrement it, at
|
|
* least for now. Since this might have changed
|
|
* over disable/enable or prior to reset, always
|
|
* do the check and potentially adjust.
|
|
*/
|
|
ipath_stats.sps_nports = dd->ipath_cfgports;
|
|
} else
|
|
ipath_dbg("Failed (%d) to initialize chip\n", ret);
|
|
|
|
/* if ret is non-zero, we probably should do some cleanup
|
|
here... */
|
|
return ret;
|
|
}
|
|
|
|
static int ipath_set_kpiobufs(const char *str, struct kernel_param *kp)
|
|
{
|
|
struct ipath_devdata *dd;
|
|
unsigned long flags;
|
|
unsigned short val;
|
|
int ret;
|
|
|
|
ret = ipath_parse_ushort(str, &val);
|
|
|
|
spin_lock_irqsave(&ipath_devs_lock, flags);
|
|
|
|
if (ret < 0)
|
|
goto bail;
|
|
|
|
if (val == 0) {
|
|
ret = -EINVAL;
|
|
goto bail;
|
|
}
|
|
|
|
list_for_each_entry(dd, &ipath_dev_list, ipath_list) {
|
|
if (dd->ipath_kregbase)
|
|
continue;
|
|
if (val > (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k -
|
|
(dd->ipath_cfgports *
|
|
IPATH_MIN_USER_PORT_BUFCNT)))
|
|
{
|
|
ipath_dev_err(
|
|
dd,
|
|
"Allocating %d PIO bufs for kernel leaves "
|
|
"too few for %d user ports (%d each)\n",
|
|
val, dd->ipath_cfgports - 1,
|
|
IPATH_MIN_USER_PORT_BUFCNT);
|
|
ret = -EINVAL;
|
|
goto bail;
|
|
}
|
|
dd->ipath_lastport_piobuf =
|
|
dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - val;
|
|
}
|
|
|
|
ret = 0;
|
|
bail:
|
|
spin_unlock_irqrestore(&ipath_devs_lock, flags);
|
|
|
|
return ret;
|
|
}
|