![Chris Zankel](/assets/img/avatar_default.png)
The attached patches provides part 6 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
51 lines
1.2 KiB
C
51 lines
1.2 KiB
C
/*
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* include/asm-xtensa/delay.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 - 2005 Tensilica Inc.
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*
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*/
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#ifndef _XTENSA_DELAY_H
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#define _XTENSA_DELAY_H
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#include <linux/config.h>
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#include <asm/processor.h>
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#include <asm/param.h>
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extern unsigned long loops_per_jiffy;
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extern __inline__ void __delay(unsigned long loops)
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{
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/* 2 cycles per loop. */
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__asm__ __volatile__ ("1: addi %0, %0, -2; bgeui %0, 1, 1b"
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: "=r" (loops) : "0" (loops));
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}
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static __inline__ u32 xtensa_get_ccount(void)
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{
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u32 ccount;
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asm volatile ("rsr %0, 234; # CCOUNT\n" : "=r" (ccount));
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return ccount;
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}
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/* For SMP/NUMA systems, change boot_cpu_data to something like
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* local_cpu_data->... where local_cpu_data points to the current
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* cpu. */
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static __inline__ void udelay (unsigned long usecs)
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{
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unsigned long start = xtensa_get_ccount();
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unsigned long cycles = usecs * (loops_per_jiffy / (1000000UL / HZ));
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/* Note: all variables are unsigned (can wrap around)! */
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while (((unsigned long)xtensa_get_ccount()) - start < cycles)
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;
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}
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#endif
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