c3e337f88a
Some later SEC v3.x are equipped with a second IRQ line. By correctly assigning IRQ affinity, this feature can be used to increase performance on dual core parts, like the MPC8572E and P2020E. The existence of the 2nd IRQ is determined from the device node's interrupt property. If present, the driver remaps two of four channels, which in turn makes those channels trigger their interrupts on the 2nd line instead of the first. To handle single- and dual-IRQ combinations efficiently, talitos gets two new interrupt handlers and back-half workers. [includes a fix to MCR_LO's address.] Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> |
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| .. | ||
| amcc | ||
| caam | ||
| Kconfig | ||
| Makefile | ||
| geode-aes.c | ||
| geode-aes.h | ||
| hifn_795x.c | ||
| ixp4xx_crypto.c | ||
| mv_cesa.c | ||
| mv_cesa.h | ||
| n2_asm.S | ||
| n2_core.c | ||
| n2_core.h | ||
| omap-aes.c | ||
| omap-sham.c | ||
| padlock-aes.c | ||
| padlock-sha.c | ||
| picoxcell_crypto.c | ||
| picoxcell_crypto_regs.h | ||
| s5p-sss.c | ||
| talitos.c | ||
| talitos.h | ||