cccd21027c
set_irq_chained_handler overwrites MPIC's handle_irq function (handle_fasteoi_irq) thus MPIC never gets eoi event from the cascaded IRQ. This situation hangs MPIC on MPC8568E. To solve this problem efficiently, QEIC needs pluggable handlers, specific to the underlaying interrupt controller. Patch extends qe_ic_init() function to accept low and high interrupt handlers. To avoid #ifdefs, stack of interrupt handlers specified in the header file and functions are marked 'static inline', thus handlers are compiled-in only if actually used (in the board file). Another option would be to lookup for parent controller and automatically detect handlers (will waste text size because of never used handlers, so this option abolished). qe_ic_init() also changed in regard to support multiplexed high/low lines as found in MPC8568E-MDS, plus qe_ic_cascade_muxed_mpic() handler implemented appropriately. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
180 lines
4.2 KiB
C
180 lines
4.2 KiB
C
/*
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* arch/powerpc/platforms/83xx/mpc832x_rdb.c
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*
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* Copyright (C) Freescale Semiconductor, Inc. 2007. All rights reserved.
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*
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* Description:
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* MPC832x RDB board specific routines.
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* This file is based on mpc832x_mds.c and mpc8313_rdb.c
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* Author: Michael Barkowski <michael.barkowski@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/pci.h>
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#include <linux/spi/spi.h>
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#include <asm/of_platform.h>
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#include <asm/time.h>
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#include <asm/ipic.h>
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#include <asm/udbg.h>
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#include <asm/qe.h>
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#include <asm/qe_ic.h>
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#include <sysdev/fsl_soc.h>
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#include "mpc83xx.h"
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(fmt...) udbg_printf(fmt)
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#else
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#define DBG(fmt...)
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#endif
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static void mpc83xx_spi_activate_cs(u8 cs, u8 polarity)
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{
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pr_debug("%s %d %d\n", __func__, cs, polarity);
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par_io_data_set(3, 13, polarity);
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}
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static void mpc83xx_spi_deactivate_cs(u8 cs, u8 polarity)
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{
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pr_debug("%s %d %d\n", __func__, cs, polarity);
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par_io_data_set(3, 13, !polarity);
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}
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static struct spi_board_info mpc832x_spi_boardinfo = {
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.bus_num = 0x4c0,
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.chip_select = 0,
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.max_speed_hz = 50000000,
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/*
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* XXX: This is spidev (spi in userspace) stub, should
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* be replaced by "mmc_spi" when mmc_spi will hit mainline.
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*/
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.modalias = "spidev",
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};
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static int __init mpc832x_spi_init(void)
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{
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if (!machine_is(mpc832x_rdb))
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return 0;
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par_io_config_pin(3, 0, 3, 0, 1, 0); /* SPI1 MOSI, I/O */
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par_io_config_pin(3, 1, 3, 0, 1, 0); /* SPI1 MISO, I/O */
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par_io_config_pin(3, 2, 3, 0, 1, 0); /* SPI1 CLK, I/O */
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par_io_config_pin(3, 3, 2, 0, 1, 0); /* SPI1 SEL, I */
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par_io_config_pin(3, 13, 1, 0, 0, 0); /* !SD_CS, O */
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par_io_config_pin(3, 14, 2, 0, 0, 0); /* SD_INSERT, I */
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par_io_config_pin(3, 15, 2, 0, 0, 0); /* SD_PROTECT,I */
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return fsl_spi_init(&mpc832x_spi_boardinfo, 1,
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mpc83xx_spi_activate_cs,
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mpc83xx_spi_deactivate_cs);
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}
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device_initcall(mpc832x_spi_init);
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/* ************************************************************************
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*
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* Setup the architecture
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*
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*/
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static void __init mpc832x_rdb_setup_arch(void)
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{
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#if defined(CONFIG_PCI) || defined(CONFIG_QUICC_ENGINE)
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struct device_node *np;
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#endif
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if (ppc_md.progress)
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ppc_md.progress("mpc832x_rdb_setup_arch()", 0);
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#ifdef CONFIG_PCI
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for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
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mpc83xx_add_bridge(np);
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#endif
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#ifdef CONFIG_QUICC_ENGINE
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qe_reset();
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if ((np = of_find_node_by_name(np, "par_io")) != NULL) {
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par_io_init(np);
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of_node_put(np);
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for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
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par_io_of_config(np);
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}
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#endif /* CONFIG_QUICC_ENGINE */
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}
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static struct of_device_id mpc832x_ids[] = {
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{ .type = "soc", },
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{ .compatible = "soc", },
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{ .type = "qe", },
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{},
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};
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static int __init mpc832x_declare_of_platform_devices(void)
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{
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if (!machine_is(mpc832x_rdb))
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return 0;
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/* Publish the QE devices */
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of_platform_bus_probe(NULL, mpc832x_ids, NULL);
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return 0;
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}
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device_initcall(mpc832x_declare_of_platform_devices);
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void __init mpc832x_rdb_init_IRQ(void)
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{
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struct device_node *np;
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np = of_find_node_by_type(NULL, "ipic");
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if (!np)
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return;
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ipic_init(np, 0);
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/* Initialize the default interrupt mapping priorities,
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* in case the boot rom changed something on us.
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*/
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ipic_set_default_priority();
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of_node_put(np);
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#ifdef CONFIG_QUICC_ENGINE
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np = of_find_node_by_type(NULL, "qeic");
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if (!np)
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return;
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qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
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of_node_put(np);
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#endif /* CONFIG_QUICC_ENGINE */
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}
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/*
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* Called very early, MMU is off, device-tree isn't unflattened
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*/
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static int __init mpc832x_rdb_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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return of_flat_dt_is_compatible(root, "MPC832xRDB");
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}
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define_machine(mpc832x_rdb) {
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.name = "MPC832x RDB",
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.probe = mpc832x_rdb_probe,
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.setup_arch = mpc832x_rdb_setup_arch,
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.init_IRQ = mpc832x_rdb_init_IRQ,
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.get_irq = ipic_get_irq,
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.restart = mpc83xx_restart,
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.time_init = mpc83xx_time_init,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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