![]() When using simultaneously the two DMA channels on a same engine, some transfers are never completed. For example, an endless lock can occur while writing heavily on a RAID5 array (with async-tx offload support enabled). Note that this issue can also be reproduced by using the DMA test client. On a same engine, the interrupt cause register is shared between two DMA channels. This patch make sure that the cause bit is only cleared for the requested channel. Signed-off-by: Simon Guinot <sguinot@lacie.com> Tested-by: Luc Saillard <luc@saillard.org> Acked-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@fluxnic.net> |
||
---|---|---|
.. | ||
ioat | ||
ipu | ||
ppc4xx | ||
at_hdmac.c | ||
at_hdmac_regs.h | ||
coh901318.c | ||
coh901318_lli.c | ||
coh901318_lli.h | ||
dmaengine.c | ||
dmatest.c | ||
dw_dmac.c | ||
dw_dmac_regs.h | ||
fsldma.c | ||
fsldma.h | ||
intel_mid_dma.c | ||
intel_mid_dma_regs.h | ||
iop-adma.c | ||
iovlock.c | ||
Kconfig | ||
Makefile | ||
mpc512x_dma.c | ||
mv_xor.c | ||
mv_xor.h | ||
pch_dma.c | ||
pl330.c | ||
shdma.c | ||
shdma.h | ||
ste_dma40.c | ||
ste_dma40_ll.c | ||
ste_dma40_ll.h | ||
timb_dma.c | ||
txx9dmac.c | ||
txx9dmac.h |