130 lines
3.8 KiB
C
130 lines
3.8 KiB
C
/*
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* File: include/asm-blackfin/cplbinit.h
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* Based on:
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* Author:
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*
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* Created:
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* Description:
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*
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* Modified:
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* Copyright 2004-2006 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __ASM_CPLBINIT_H__
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#define __ASM_CPLBINIT_H__
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#include <asm/blackfin.h>
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#include <asm/cplb.h>
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#ifdef CONFIG_MPU
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#include <asm/cplb-mpu.h>
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extern void bfin_icache_init(struct cplb_entry *icplb_tbl);
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extern void bfin_dcache_init(struct cplb_entry *icplb_tbl);
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#else
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#define INITIAL_T 0x1
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#define SWITCH_T 0x2
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#define I_CPLB 0x4
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#define D_CPLB 0x8
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#define IN_KERNEL 1
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#define ASYNC_MEMORY_CPLB_COVERAGE ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
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ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M)
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#define CPLB_MEM CONFIG_MAX_MEM_SIZE
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/*
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* Number of required data CPLB switchtable entries
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* MEMSIZE / 4 (we mostly install 4M page size CPLBs
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* approx 16 for smaller 1MB page size CPLBs for allignment purposes
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* 1 for L1 Data Memory
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* possibly 1 for L2 Data Memory
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* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
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* 1 for ASYNC Memory
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*/
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#define MAX_SWITCH_D_CPLBS (((CPLB_MEM / 4) + 16 + 1 + 1 + 1 \
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+ ASYNC_MEMORY_CPLB_COVERAGE) * 2)
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/*
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* Number of required instruction CPLB switchtable entries
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* MEMSIZE / 4 (we mostly install 4M page size CPLBs
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* approx 12 for smaller 1MB page size CPLBs for allignment purposes
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* 1 for L1 Instruction Memory
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* possibly 1 for L2 Instruction Memory
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* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
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*/
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#define MAX_SWITCH_I_CPLBS (((CPLB_MEM / 4) + 12 + 1 + 1 + 1) * 2)
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/* Number of CPLB table entries, used for cplb-nompu. */
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#define CPLB_TBL_ENTRIES (16 * 4)
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enum {
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ZERO_P, L1I_MEM, L1D_MEM, L2_MEM, SDRAM_KERN, SDRAM_RAM_MTD, SDRAM_DMAZ,
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RES_MEM, ASYNC_MEM, OCB_ROM
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};
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struct cplb_desc {
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u32 start; /* start address */
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u32 end; /* end address */
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u32 psize; /* prefered size if any otherwise 1MB or 4MB*/
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u16 attr;/* attributes */
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u16 i_conf;/* I-CPLB DATA */
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u16 d_conf;/* D-CPLB DATA */
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u16 valid;/* valid */
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const s8 name[30];/* name */
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};
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struct cplb_tab {
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u_long *tab;
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u16 pos;
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u16 size;
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};
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extern u_long icplb_tables[NR_CPUS][CPLB_TBL_ENTRIES+1];
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extern u_long dcplb_tables[NR_CPUS][CPLB_TBL_ENTRIES+1];
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/* Till here we are discussing about the static memory management model.
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* However, the operating envoronments commonly define more CPLB
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* descriptors to cover the entire addressable memory than will fit into
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* the available on-chip 16 CPLB MMRs. When this happens, the below table
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* will be used which will hold all the potentially required CPLB descriptors
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*
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* This is how Page descriptor Table is implemented in uClinux/Blackfin.
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*/
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extern u_long ipdt_tables[NR_CPUS][MAX_SWITCH_I_CPLBS+1];
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extern u_long dpdt_tables[NR_CPUS][MAX_SWITCH_D_CPLBS+1];
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#ifdef CONFIG_CPLB_INFO
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extern u_long ipdt_swapcount_tables[NR_CPUS][MAX_SWITCH_I_CPLBS];
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extern u_long dpdt_swapcount_tables[NR_CPUS][MAX_SWITCH_D_CPLBS];
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#endif
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extern void bfin_icache_init(u_long icplbs[]);
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extern void bfin_dcache_init(u_long dcplbs[]);
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#endif /* CONFIG_MPU */
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#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
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extern void generate_cplb_tables_cpu(unsigned int cpu);
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#endif
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#endif
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