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Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
175 lines
5.3 KiB
C
175 lines
5.3 KiB
C
/*
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* arch/v850/kernel/v850e_cache.c -- Cache control for V850E cache memories
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*
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* Copyright (C) 2003 NEC Electronics Corporation
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* Copyright (C) 2003 Miles Bader <miles@gnu.org>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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* Written by Miles Bader <miles@gnu.org>
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*/
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/* This file implements cache control for the rather simple cache used on
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some V850E CPUs, specifically the NB85E/TEG CPU-core and the V850E/ME2
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CPU. V850E2 processors have their own (better) cache
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implementation. */
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#include <asm/entry.h>
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#include <asm/cacheflush.h>
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#include <asm/v850e_cache.h>
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#define WAIT_UNTIL_CLEAR(value) while (value) {}
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/* Set caching params via the BHC and DCC registers. */
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void v850e_cache_enable (u16 bhc, u16 icc, u16 dcc)
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{
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unsigned long *r0_ram = (unsigned long *)R0_RAM_ADDR;
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register u16 bhc_val asm ("r6") = bhc;
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/* Read the instruction cache control register (ICC) and confirm
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that bits 0 and 1 (TCLR0, TCLR1) are all cleared. */
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WAIT_UNTIL_CLEAR (V850E_CACHE_ICC & 0x3);
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V850E_CACHE_ICC = icc;
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#ifdef V850E_CACHE_DCC
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/* Configure data-cache. */
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V850E_CACHE_DCC = dcc;
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#endif /* V850E_CACHE_DCC */
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/* Configure caching for various memory regions by writing the BHC
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register. The documentation says that an instruction _cannot_
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enable/disable caching for the memory region in which the
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instruction itself exists; to work around this, we store
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appropriate instructions into the on-chip RAM area (which is never
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cached), and briefly jump there to do the work. */
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#ifdef V850E_CACHE_WRITE_IBS
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*r0_ram++ = 0xf0720760; /* st.h r0, 0xfffff072[r0] */
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#endif
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*r0_ram++ = 0xf06a3760; /* st.h r6, 0xfffff06a[r0] */
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*r0_ram = 0x5640006b; /* jmp [r11] */
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asm ("mov hilo(1f), r11; jmp [%1]; 1:;"
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:: "r" (bhc_val), "r" (R0_RAM_ADDR) : "r11");
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}
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static void clear_icache (void)
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{
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/* 1. Read the instruction cache control register (ICC) and confirm
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that bits 0 and 1 (TCLR0, TCLR1) are all cleared. */
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WAIT_UNTIL_CLEAR (V850E_CACHE_ICC & 0x3);
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/* 2. Read the ICC register and confirm that bit 12 (LOCK0) is
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cleared. Bit 13 of the ICC register is always cleared. */
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WAIT_UNTIL_CLEAR (V850E_CACHE_ICC & 0x1000);
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/* 3. Set the TCLR0 and TCLR1 bits of the ICC register as follows,
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when clearing way 0 and way 1 at the same time:
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(a) Set the TCLR0 and TCLR1 bits.
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(b) Read the TCLR0 and TCLR1 bits to confirm that these bits
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are cleared.
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(c) Perform (a) and (b) above again. */
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V850E_CACHE_ICC |= 0x3;
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WAIT_UNTIL_CLEAR (V850E_CACHE_ICC & 0x3);
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#ifdef V850E_CACHE_REPEAT_ICC_WRITE
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/* Do it again. */
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V850E_CACHE_ICC |= 0x3;
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WAIT_UNTIL_CLEAR (V850E_CACHE_ICC & 0x3);
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#endif
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}
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#ifdef V850E_CACHE_DCC
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/* Flush or clear (or both) the data cache, depending on the value of FLAGS;
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the procedure is the same for both, just the control bits used differ (and
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both may be performed simultaneously). */
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static void dcache_op (unsigned short flags)
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{
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/* 1. Read the data cache control register (DCC) and confirm that bits
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0, 1, 4, and 5 (DC00, DC01, DC04, DC05) are all cleared. */
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WAIT_UNTIL_CLEAR (V850E_CACHE_DCC & 0x33);
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/* 2. Clear DCC register bit 12 (DC12), bit 13 (DC13), or both
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depending on the way for which tags are to be cleared. */
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V850E_CACHE_DCC &= ~0xC000;
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/* 3. Set DCC register bit 0 (DC00), bit 1 (DC01) or both depending on
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the way for which tags are to be cleared.
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...
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Set DCC register bit 4 (DC04), bit 5 (DC05), or both depending
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on the way to be data flushed. */
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V850E_CACHE_DCC |= flags;
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/* 4. Read DCC register bit DC00, DC01 [DC04, DC05], or both depending
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on the way for which tags were cleared [flushed] and confirm
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that that bit is cleared. */
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WAIT_UNTIL_CLEAR (V850E_CACHE_DCC & flags);
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}
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#endif /* V850E_CACHE_DCC */
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/* Flushes the contents of the dcache to memory. */
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static inline void flush_dcache (void)
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{
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#ifdef V850E_CACHE_DCC
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/* We only need to do something if in write-back mode. */
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if (V850E_CACHE_DCC & 0x0400)
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dcache_op (0x30);
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#endif /* V850E_CACHE_DCC */
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}
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/* Flushes the contents of the dcache to memory, and then clears it. */
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static inline void clear_dcache (void)
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{
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#ifdef V850E_CACHE_DCC
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/* We only need to do something if the dcache is enabled. */
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if (V850E_CACHE_DCC & 0x0C00)
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dcache_op (0x33);
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#endif /* V850E_CACHE_DCC */
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}
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/* Clears the dcache without flushing to memory first. */
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static inline void clear_dcache_no_flush (void)
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{
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#ifdef V850E_CACHE_DCC
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/* We only need to do something if the dcache is enabled. */
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if (V850E_CACHE_DCC & 0x0C00)
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dcache_op (0x3);
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#endif /* V850E_CACHE_DCC */
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}
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static inline void cache_exec_after_store (void)
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{
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flush_dcache ();
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clear_icache ();
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}
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/* Exported functions. */
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void flush_icache (void)
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{
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cache_exec_after_store ();
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}
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void flush_icache_range (unsigned long start, unsigned long end)
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{
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cache_exec_after_store ();
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}
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void flush_icache_page (struct vm_area_struct *vma, struct page *page)
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{
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cache_exec_after_store ();
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}
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void flush_icache_user_range (struct vm_area_struct *vma, struct page *page,
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unsigned long adr, int len)
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{
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cache_exec_after_store ();
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}
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void flush_cache_sigtramp (unsigned long addr)
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{
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cache_exec_after_store ();
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}
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