![Ahmed S. Darwish](/assets/img/avatar_default.png)
Use ARRAY_SIZE macro already defined in linux/kernel.h Signed-off-by: Ahmed S. Darwish <darwish.07@gmail.com> Cc: Miles Bader <uclinux-v850@lsi.nec.co.jp> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
820 lines
21 KiB
C
820 lines
21 KiB
C
/*
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* arch/v850/kernel/mb_a_pci.c -- PCI support for Midas lab RTE-MOTHER-A board
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*
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* Copyright (C) 2001,02,03,05 NEC Electronics Corporation
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* Copyright (C) 2001,02,03,05 Miles Bader <miles@gnu.org>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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* Written by Miles Bader <miles@gnu.org>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/pci.h>
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#include <asm/machdep.h>
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/* __nomods_init is like __devinit, but is a no-op when modules are enabled.
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This is used by some routines that can be called either during boot
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or by a module. */
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#ifdef CONFIG_MODULES
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#define __nomods_init /*nothing*/
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#else
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#define __nomods_init __devinit
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#endif
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/* PCI devices on the Mother-A board can only do DMA to/from the MB SRAM
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(the RTE-V850E/MA1-CB cpu board doesn't support PCI access to
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CPU-board memory), and since linux DMA buffers are allocated in
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normal kernel memory, we basically have to copy DMA blocks around
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(this is like a `bounce buffer'). When a DMA block is `mapped', we
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allocate an identically sized block in MB SRAM, and if we're doing
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output to the device, copy the CPU-memory block to the MB-SRAM block.
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When an active block is `unmapped', we will copy the block back to
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CPU memory if necessary, and then deallocate the MB SRAM block.
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Ack. */
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/* Where the motherboard SRAM is in the PCI-bus address space (the
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first 512K of it is also mapped at PCI address 0). */
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#define PCI_MB_SRAM_ADDR 0x800000
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/* Convert CPU-view MB SRAM address to/from PCI-view addresses of the
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same memory. */
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#define MB_SRAM_TO_PCI(mb_sram_addr) \
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((dma_addr_t)mb_sram_addr - MB_A_SRAM_ADDR + PCI_MB_SRAM_ADDR)
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#define PCI_TO_MB_SRAM(pci_addr) \
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(void *)(pci_addr - PCI_MB_SRAM_ADDR + MB_A_SRAM_ADDR)
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static void pcibios_assign_resources (void);
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struct mb_pci_dev_irq {
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unsigned dev; /* PCI device number */
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unsigned irq_base; /* First IRQ */
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unsigned query_pin; /* True if we should read the device's
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Interrupt Pin info, and allocate
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interrupt IRQ_BASE + PIN. */
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};
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/* PCI interrupts are mapped statically to GBUS interrupts. */
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static struct mb_pci_dev_irq mb_pci_dev_irqs[] = {
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/* Motherboard SB82558 ethernet controller */
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{ 10, IRQ_MB_A_LAN, 0 },
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/* PCI slot 1 */
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{ 8, IRQ_MB_A_PCI1(0), 1 },
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/* PCI slot 2 */
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{ 9, IRQ_MB_A_PCI2(0), 1 }
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};
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#define NUM_MB_PCI_DEV_IRQS ARRAY_SIZE(mb_pci_dev_irqs)
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/* PCI configuration primitives. */
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#define CONFIG_DMCFGA(bus, devfn, offs) \
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(0x80000000 \
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| ((offs) & ~0x3) \
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| ((devfn) << 8) \
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| ((bus)->number << 16))
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static int
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mb_pci_read (struct pci_bus *bus, unsigned devfn, int offs, int size, u32 *rval)
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{
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u32 addr;
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int flags;
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local_irq_save (flags);
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MB_A_PCI_PCICR = 0x7;
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MB_A_PCI_DMCFGA = CONFIG_DMCFGA (bus, devfn, offs);
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addr = MB_A_PCI_IO_ADDR + (offs & 0x3);
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switch (size) {
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case 1: *rval = *(volatile u8 *)addr; break;
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case 2: *rval = *(volatile u16 *)addr; break;
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case 4: *rval = *(volatile u32 *)addr; break;
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}
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if (MB_A_PCI_PCISR & 0x2000) {
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MB_A_PCI_PCISR = 0x2000;
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*rval = ~0;
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}
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MB_A_PCI_DMCFGA = 0;
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local_irq_restore (flags);
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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mb_pci_write (struct pci_bus *bus, unsigned devfn, int offs, int size, u32 val)
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{
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u32 addr;
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int flags;
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local_irq_save (flags);
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MB_A_PCI_PCICR = 0x7;
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MB_A_PCI_DMCFGA = CONFIG_DMCFGA (bus, devfn, offs);
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addr = MB_A_PCI_IO_ADDR + (offs & 0x3);
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switch (size) {
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case 1: *(volatile u8 *)addr = val; break;
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case 2: *(volatile u16 *)addr = val; break;
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case 4: *(volatile u32 *)addr = val; break;
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}
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if (MB_A_PCI_PCISR & 0x2000)
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MB_A_PCI_PCISR = 0x2000;
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MB_A_PCI_DMCFGA = 0;
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local_irq_restore (flags);
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops mb_pci_config_ops = {
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.read = mb_pci_read,
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.write = mb_pci_write,
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};
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/* PCI Initialization. */
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static struct pci_bus *mb_pci_bus = 0;
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/* Do initial PCI setup. */
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static int __devinit pcibios_init (void)
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{
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u32 id = MB_A_PCI_PCIHIDR;
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u16 vendor = id & 0xFFFF;
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u16 device = (id >> 16) & 0xFFFF;
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if (vendor == PCI_VENDOR_ID_PLX && device == PCI_DEVICE_ID_PLX_9080) {
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printk (KERN_INFO
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"PCI: PLX Technology PCI9080 HOST/PCI bridge\n");
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MB_A_PCI_PCICR = 0x147;
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MB_A_PCI_PCIBAR0 = 0x007FFF00;
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MB_A_PCI_PCIBAR1 = 0x0000FF00;
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MB_A_PCI_PCIBAR2 = 0x00800000;
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MB_A_PCI_PCILTR = 0x20;
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MB_A_PCI_PCIPBAM |= 0x3;
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MB_A_PCI_PCISR = ~0; /* Clear errors. */
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/* Reprogram the motherboard's IO/config address space,
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as we don't support the GCS7 address space that the
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default uses. */
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/* Significant address bits used for decoding PCI GCS5 space
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accessess. */
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MB_A_PCI_DMRR = ~(MB_A_PCI_MEM_SIZE - 1);
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/* I don't understand this, but the SolutionGear example code
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uses such an offset, and it doesn't work without it. XXX */
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#if GCS5_SIZE == 0x00800000
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#define GCS5_CFG_OFFS 0x00800000
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#else
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#define GCS5_CFG_OFFS 0
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#endif
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/* Address bit values for matching. Note that we have to give
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the address from the motherboard's point of view, which is
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different than the CPU's. */
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/* PCI memory space. */
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MB_A_PCI_DMLBAM = GCS5_CFG_OFFS + 0x0;
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/* PCI I/O space. */
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MB_A_PCI_DMLBAI =
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GCS5_CFG_OFFS + (MB_A_PCI_IO_ADDR - GCS5_ADDR);
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mb_pci_bus = pci_scan_bus (0, &mb_pci_config_ops, 0);
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pcibios_assign_resources ();
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} else
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printk (KERN_ERR "PCI: HOST/PCI bridge not found\n");
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return 0;
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}
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subsys_initcall (pcibios_init);
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char __devinit *pcibios_setup (char *option)
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{
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/* Don't handle any options. */
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return option;
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}
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int __nomods_init pcibios_enable_device (struct pci_dev *dev, int mask)
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{
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u16 cmd, old_cmd;
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int idx;
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struct resource *r;
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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old_cmd = cmd;
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for (idx = 0; idx < 6; idx++) {
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r = &dev->resource[idx];
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if (!r->start && r->end) {
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printk(KERN_ERR "PCI: Device %s not available because "
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"of resource collisions\n", pci_name(dev));
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return -EINVAL;
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}
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if (r->flags & IORESOURCE_IO)
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cmd |= PCI_COMMAND_IO;
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if (r->flags & IORESOURCE_MEM)
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cmd |= PCI_COMMAND_MEMORY;
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}
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if (cmd != old_cmd) {
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printk("PCI: Enabling device %s (%04x -> %04x)\n",
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pci_name(dev), old_cmd, cmd);
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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}
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return 0;
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}
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/* Resource allocation. */
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static void __devinit pcibios_assign_resources (void)
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{
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struct pci_dev *dev = NULL;
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struct resource *r;
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for_each_pci_dev(dev) {
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unsigned di_num;
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unsigned class = dev->class >> 8;
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if (class && class != PCI_CLASS_BRIDGE_HOST) {
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unsigned r_num;
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for(r_num = 0; r_num < 6; r_num++) {
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r = &dev->resource[r_num];
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if (!r->start && r->end)
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pci_assign_resource (dev, r_num);
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}
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}
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/* Assign interrupts. */
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for (di_num = 0; di_num < NUM_MB_PCI_DEV_IRQS; di_num++) {
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struct mb_pci_dev_irq *di = &mb_pci_dev_irqs[di_num];
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if (di->dev == PCI_SLOT (dev->devfn)) {
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unsigned irq = di->irq_base;
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if (di->query_pin) {
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/* Find out which interrupt pin
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this device uses (each PCI
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slot has 4). */
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u8 irq_pin;
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pci_read_config_byte (dev,
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PCI_INTERRUPT_PIN,
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&irq_pin);
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if (irq_pin == 0)
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/* Doesn't use interrupts. */
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continue;
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else
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irq += irq_pin - 1;
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}
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pcibios_update_irq (dev, irq);
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}
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}
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}
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}
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void __devinit pcibios_update_irq (struct pci_dev *dev, int irq)
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{
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dev->irq = irq;
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pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
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}
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void __devinit
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pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
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struct resource *res)
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{
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unsigned long offset = 0;
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if (res->flags & IORESOURCE_IO) {
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offset = MB_A_PCI_IO_ADDR;
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} else if (res->flags & IORESOURCE_MEM) {
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offset = MB_A_PCI_MEM_ADDR;
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}
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region->start = res->start - offset;
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region->end = res->end - offset;
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}
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/* Stubs for things we don't use. */
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/* Called after each bus is probed, but before its children are examined. */
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void pcibios_fixup_bus(struct pci_bus *b)
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{
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}
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void
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pcibios_align_resource (void *data, struct resource *res,
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resource_size_t size, resource_size_t align)
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{
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}
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void pcibios_set_master (struct pci_dev *dev)
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{
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}
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/* Mother-A SRAM memory allocation. This is a simple first-fit allocator. */
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/* A memory free-list node. */
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struct mb_sram_free_area {
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void *mem;
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unsigned long size;
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struct mb_sram_free_area *next;
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};
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/* The tail of the free-list, which starts out containing all the SRAM. */
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static struct mb_sram_free_area mb_sram_free_tail = {
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(void *)MB_A_SRAM_ADDR, MB_A_SRAM_SIZE, 0
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};
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/* The free-list. */
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static struct mb_sram_free_area *mb_sram_free_areas = &mb_sram_free_tail;
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/* The free-list of free free-list nodes. (:-) */
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static struct mb_sram_free_area *mb_sram_free_free_areas = 0;
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/* Spinlock protecting the above globals. */
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static DEFINE_SPINLOCK(mb_sram_lock);
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/* Allocate a memory block at least SIZE bytes long in the Mother-A SRAM
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space. */
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static void *alloc_mb_sram (size_t size)
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{
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struct mb_sram_free_area *prev, *fa;
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unsigned long flags;
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void *mem = 0;
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spin_lock_irqsave (mb_sram_lock, flags);
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/* Look for a free area that can contain SIZE bytes. */
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for (prev = 0, fa = mb_sram_free_areas; fa; prev = fa, fa = fa->next)
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if (fa->size >= size) {
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/* Found one! */
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mem = fa->mem;
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if (fa->size == size) {
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/* In fact, it fits exactly, so remove
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this node from the free-list. */
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if (prev)
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prev->next = fa->next;
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else
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mb_sram_free_areas = fa->next;
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/* Put it on the free-list-entry-free-list. */
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fa->next = mb_sram_free_free_areas;
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mb_sram_free_free_areas = fa;
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} else {
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/* FA is bigger than SIZE, so just
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reduce its size to account for this
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allocation. */
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fa->mem += size;
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fa->size -= size;
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}
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break;
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}
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spin_unlock_irqrestore (mb_sram_lock, flags);
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return mem;
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}
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/* Return the memory area MEM of size SIZE to the MB SRAM free pool. */
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static void free_mb_sram (void *mem, size_t size)
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{
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struct mb_sram_free_area *prev, *fa, *new_fa;
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unsigned long flags;
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void *end = mem + size;
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spin_lock_irqsave (mb_sram_lock, flags);
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retry:
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/* Find an adjacent free-list entry. */
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for (prev = 0, fa = mb_sram_free_areas; fa; prev = fa, fa = fa->next)
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if (fa->mem == end) {
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/* FA is just after MEM, grow down to encompass it. */
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fa->mem = mem;
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fa->size += size;
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goto done;
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} else if (fa->mem + fa->size == mem) {
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struct mb_sram_free_area *next_fa = fa->next;
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/* FA is just before MEM, expand to encompass it. */
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fa->size += size;
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/* See if FA can now be merged with its successor. */
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if (next_fa && fa->mem + fa->size == next_fa->mem) {
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/* Yup; merge NEXT_FA's info into FA. */
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fa->size += next_fa->size;
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fa->next = next_fa->next;
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/* Free NEXT_FA. */
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next_fa->next = mb_sram_free_free_areas;
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mb_sram_free_free_areas = next_fa;
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}
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goto done;
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} else if (fa->mem > mem)
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/* We've reached the right spot in the free-list
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without finding an adjacent free-area, so add
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a new free area to hold mem. */
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break;
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/* Make a new free-list entry. */
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/* First, get a free-list entry. */
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if (! mb_sram_free_free_areas) {
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/* There are none, so make some. */
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void *block;
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size_t block_size = sizeof (struct mb_sram_free_area) * 8;
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/* Don't hold the lock while calling kmalloc (I'm not
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sure whether it would be a problem, since we use
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GFP_ATOMIC, but it makes me nervous). */
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spin_unlock_irqrestore (mb_sram_lock, flags);
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block = kmalloc (block_size, GFP_ATOMIC);
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if (! block)
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panic ("free_mb_sram: can't allocate free-list entry");
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/* Now get the lock back. */
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spin_lock_irqsave (mb_sram_lock, flags);
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/* Add the new free free-list entries. */
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while (block_size > 0) {
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struct mb_sram_free_area *nfa = block;
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nfa->next = mb_sram_free_free_areas;
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mb_sram_free_free_areas = nfa;
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block += sizeof *nfa;
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block_size -= sizeof *nfa;
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}
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/* Since we dropped the lock to call kmalloc, the
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free-list could have changed, so retry from the
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beginning. */
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goto retry;
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}
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/* Remove NEW_FA from the free-list of free-list entries. */
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new_fa = mb_sram_free_free_areas;
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mb_sram_free_free_areas = new_fa->next;
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/* NEW_FA initially holds only MEM. */
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new_fa->mem = mem;
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new_fa->size = size;
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/* Insert NEW_FA in the free-list between PREV and FA. */
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new_fa->next = fa;
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if (prev)
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prev->next = new_fa;
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else
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mb_sram_free_areas = new_fa;
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done:
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spin_unlock_irqrestore (mb_sram_lock, flags);
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}
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/* Maintainence of CPU -> Mother-A DMA mappings. */
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struct dma_mapping {
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void *cpu_addr;
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void *mb_sram_addr;
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size_t size;
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struct dma_mapping *next;
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};
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/* A list of mappings from CPU addresses to MB SRAM addresses for active
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DMA blocks (that have been `granted' to the PCI device). */
|
||
static struct dma_mapping *active_dma_mappings = 0;
|
||
|
||
/* A list of free mapping objects. */
|
||
static struct dma_mapping *free_dma_mappings = 0;
|
||
|
||
/* Spinlock protecting the above globals. */
|
||
static DEFINE_SPINLOCK(dma_mappings_lock);
|
||
|
||
static struct dma_mapping *new_dma_mapping (size_t size)
|
||
{
|
||
unsigned long flags;
|
||
struct dma_mapping *mapping;
|
||
void *mb_sram_block = alloc_mb_sram (size);
|
||
|
||
if (! mb_sram_block)
|
||
return 0;
|
||
|
||
spin_lock_irqsave (dma_mappings_lock, flags);
|
||
|
||
if (! free_dma_mappings) {
|
||
/* We're out of mapping structures, make more. */
|
||
void *mblock;
|
||
size_t mblock_size = sizeof (struct dma_mapping) * 8;
|
||
|
||
/* Don't hold the lock while calling kmalloc (I'm not
|
||
sure whether it would be a problem, since we use
|
||
GFP_ATOMIC, but it makes me nervous). */
|
||
spin_unlock_irqrestore (dma_mappings_lock, flags);
|
||
|
||
mblock = kmalloc (mblock_size, GFP_ATOMIC);
|
||
if (! mblock) {
|
||
free_mb_sram (mb_sram_block, size);
|
||
return 0;
|
||
}
|
||
|
||
/* Get the lock back. */
|
||
spin_lock_irqsave (dma_mappings_lock, flags);
|
||
|
||
/* Add the new mapping structures to the free-list. */
|
||
while (mblock_size > 0) {
|
||
struct dma_mapping *fm = mblock;
|
||
fm->next = free_dma_mappings;
|
||
free_dma_mappings = fm;
|
||
mblock += sizeof *fm;
|
||
mblock_size -= sizeof *fm;
|
||
}
|
||
}
|
||
|
||
/* Get a mapping struct from the freelist. */
|
||
mapping = free_dma_mappings;
|
||
free_dma_mappings = mapping->next;
|
||
|
||
/* Initialize the mapping. Other fields should be filled in by
|
||
caller. */
|
||
mapping->mb_sram_addr = mb_sram_block;
|
||
mapping->size = size;
|
||
|
||
/* Add it to the list of active mappings. */
|
||
mapping->next = active_dma_mappings;
|
||
active_dma_mappings = mapping;
|
||
|
||
spin_unlock_irqrestore (dma_mappings_lock, flags);
|
||
|
||
return mapping;
|
||
}
|
||
|
||
static struct dma_mapping *find_dma_mapping (void *mb_sram_addr)
|
||
{
|
||
unsigned long flags;
|
||
struct dma_mapping *mapping;
|
||
|
||
spin_lock_irqsave (dma_mappings_lock, flags);
|
||
|
||
for (mapping = active_dma_mappings; mapping; mapping = mapping->next)
|
||
if (mapping->mb_sram_addr == mb_sram_addr) {
|
||
spin_unlock_irqrestore (dma_mappings_lock, flags);
|
||
return mapping;
|
||
}
|
||
|
||
panic ("find_dma_mapping: unmapped PCI DMA addr 0x%x",
|
||
MB_SRAM_TO_PCI (mb_sram_addr));
|
||
}
|
||
|
||
static struct dma_mapping *deactivate_dma_mapping (void *mb_sram_addr)
|
||
{
|
||
unsigned long flags;
|
||
struct dma_mapping *mapping, *prev;
|
||
|
||
spin_lock_irqsave (dma_mappings_lock, flags);
|
||
|
||
for (prev = 0, mapping = active_dma_mappings;
|
||
mapping;
|
||
prev = mapping, mapping = mapping->next)
|
||
{
|
||
if (mapping->mb_sram_addr == mb_sram_addr) {
|
||
/* This is the MAPPING; deactivate it. */
|
||
if (prev)
|
||
prev->next = mapping->next;
|
||
else
|
||
active_dma_mappings = mapping->next;
|
||
|
||
spin_unlock_irqrestore (dma_mappings_lock, flags);
|
||
|
||
return mapping;
|
||
}
|
||
}
|
||
|
||
panic ("deactivate_dma_mapping: unmapped PCI DMA addr 0x%x",
|
||
MB_SRAM_TO_PCI (mb_sram_addr));
|
||
}
|
||
|
||
/* Return MAPPING to the freelist. */
|
||
static inline void
|
||
free_dma_mapping (struct dma_mapping *mapping)
|
||
{
|
||
unsigned long flags;
|
||
|
||
free_mb_sram (mapping->mb_sram_addr, mapping->size);
|
||
|
||
spin_lock_irqsave (dma_mappings_lock, flags);
|
||
|
||
mapping->next = free_dma_mappings;
|
||
free_dma_mappings = mapping;
|
||
|
||
spin_unlock_irqrestore (dma_mappings_lock, flags);
|
||
}
|
||
|
||
|
||
/* Single PCI DMA mappings. */
|
||
|
||
/* `Grant' to PDEV the memory block at CPU_ADDR, for doing DMA. The
|
||
32-bit PCI bus mastering address to use is returned. the device owns
|
||
this memory until either pci_unmap_single or pci_dma_sync_single is
|
||
performed. */
|
||
dma_addr_t
|
||
pci_map_single (struct pci_dev *pdev, void *cpu_addr, size_t size, int dir)
|
||
{
|
||
struct dma_mapping *mapping = new_dma_mapping (size);
|
||
|
||
if (! mapping)
|
||
return 0;
|
||
|
||
mapping->cpu_addr = cpu_addr;
|
||
|
||
if (dir == PCI_DMA_BIDIRECTIONAL || dir == PCI_DMA_TODEVICE)
|
||
memcpy (mapping->mb_sram_addr, cpu_addr, size);
|
||
|
||
return MB_SRAM_TO_PCI (mapping->mb_sram_addr);
|
||
}
|
||
|
||
/* Return to the CPU the PCI DMA memory block previously `granted' to
|
||
PDEV, at DMA_ADDR. */
|
||
void pci_unmap_single (struct pci_dev *pdev, dma_addr_t dma_addr, size_t size,
|
||
int dir)
|
||
{
|
||
void *mb_sram_addr = PCI_TO_MB_SRAM (dma_addr);
|
||
struct dma_mapping *mapping = deactivate_dma_mapping (mb_sram_addr);
|
||
|
||
if (size != mapping->size)
|
||
panic ("pci_unmap_single: size (%d) doesn't match"
|
||
" size of mapping at PCI DMA addr 0x%x (%d)\n",
|
||
size, dma_addr, mapping->size);
|
||
|
||
/* Copy back the DMA'd contents if necessary. */
|
||
if (dir == PCI_DMA_BIDIRECTIONAL || dir == PCI_DMA_FROMDEVICE)
|
||
memcpy (mapping->cpu_addr, mb_sram_addr, size);
|
||
|
||
/* Return mapping to the freelist. */
|
||
free_dma_mapping (mapping);
|
||
}
|
||
|
||
/* Make physical memory consistent for a single streaming mode DMA
|
||
translation after a transfer.
|
||
|
||
If you perform a pci_map_single() but wish to interrogate the
|
||
buffer using the cpu, yet do not wish to teardown the PCI dma
|
||
mapping, you must call this function before doing so. At the next
|
||
point you give the PCI dma address back to the card, you must first
|
||
perform a pci_dma_sync_for_device, and then the device again owns
|
||
the buffer. */
|
||
void
|
||
pci_dma_sync_single_for_cpu (struct pci_dev *pdev, dma_addr_t dma_addr, size_t size,
|
||
int dir)
|
||
{
|
||
void *mb_sram_addr = PCI_TO_MB_SRAM (dma_addr);
|
||
struct dma_mapping *mapping = find_dma_mapping (mb_sram_addr);
|
||
|
||
/* Synchronize the DMA buffer with the CPU buffer if necessary. */
|
||
if (dir == PCI_DMA_FROMDEVICE)
|
||
memcpy (mapping->cpu_addr, mb_sram_addr, size);
|
||
else if (dir == PCI_DMA_TODEVICE)
|
||
; /* nothing to do */
|
||
else
|
||
panic("pci_dma_sync_single: unsupported sync dir: %d", dir);
|
||
}
|
||
|
||
void
|
||
pci_dma_sync_single_for_device (struct pci_dev *pdev, dma_addr_t dma_addr, size_t size,
|
||
int dir)
|
||
{
|
||
void *mb_sram_addr = PCI_TO_MB_SRAM (dma_addr);
|
||
struct dma_mapping *mapping = find_dma_mapping (mb_sram_addr);
|
||
|
||
/* Synchronize the DMA buffer with the CPU buffer if necessary. */
|
||
if (dir == PCI_DMA_FROMDEVICE)
|
||
; /* nothing to do */
|
||
else if (dir == PCI_DMA_TODEVICE)
|
||
memcpy (mb_sram_addr, mapping->cpu_addr, size);
|
||
else
|
||
panic("pci_dma_sync_single: unsupported sync dir: %d", dir);
|
||
}
|
||
|
||
|
||
/* Scatter-gather PCI DMA mappings. */
|
||
|
||
/* Do multiple DMA mappings at once. */
|
||
int
|
||
pci_map_sg (struct pci_dev *pdev, struct scatterlist *sg, int sg_len, int dir)
|
||
{
|
||
BUG ();
|
||
return 0;
|
||
}
|
||
|
||
/* Unmap multiple DMA mappings at once. */
|
||
void
|
||
pci_unmap_sg (struct pci_dev *pdev, struct scatterlist *sg, int sg_len,int dir)
|
||
{
|
||
BUG ();
|
||
}
|
||
|
||
/* Make physical memory consistent for a set of streaming mode DMA
|
||
translations after a transfer. The same as pci_dma_sync_single_* but
|
||
for a scatter-gather list, same rules and usage. */
|
||
|
||
void
|
||
pci_dma_sync_sg_for_cpu (struct pci_dev *dev,
|
||
struct scatterlist *sg, int sg_len,
|
||
int dir)
|
||
{
|
||
BUG ();
|
||
}
|
||
|
||
void
|
||
pci_dma_sync_sg_for_device (struct pci_dev *dev,
|
||
struct scatterlist *sg, int sg_len,
|
||
int dir)
|
||
{
|
||
BUG ();
|
||
}
|
||
|
||
|
||
/* PCI mem mapping. */
|
||
|
||
/* Allocate and map kernel buffer using consistent mode DMA for PCI
|
||
device. Returns non-NULL cpu-view pointer to the buffer if
|
||
successful and sets *DMA_ADDR to the pci side dma address as well,
|
||
else DMA_ADDR is undefined. */
|
||
void *
|
||
pci_alloc_consistent (struct pci_dev *pdev, size_t size, dma_addr_t *dma_addr)
|
||
{
|
||
void *mb_sram_mem = alloc_mb_sram (size);
|
||
if (mb_sram_mem)
|
||
*dma_addr = MB_SRAM_TO_PCI (mb_sram_mem);
|
||
return mb_sram_mem;
|
||
}
|
||
|
||
/* Free and unmap a consistent DMA buffer. CPU_ADDR and DMA_ADDR must
|
||
be values that were returned from pci_alloc_consistent. SIZE must be
|
||
the same as what as passed into pci_alloc_consistent. References to
|
||
the memory and mappings assosciated with CPU_ADDR or DMA_ADDR past
|
||
this call are illegal. */
|
||
void
|
||
pci_free_consistent (struct pci_dev *pdev, size_t size, void *cpu_addr,
|
||
dma_addr_t dma_addr)
|
||
{
|
||
void *mb_sram_mem = PCI_TO_MB_SRAM (dma_addr);
|
||
free_mb_sram (mb_sram_mem, size);
|
||
}
|
||
|
||
|
||
/* iomap/iomap */
|
||
|
||
void __iomem *pci_iomap (struct pci_dev *dev, int bar, unsigned long max)
|
||
{
|
||
unsigned long start = pci_resource_start (dev, bar);
|
||
unsigned long len = pci_resource_len (dev, bar);
|
||
|
||
if (!start || len == 0)
|
||
return 0;
|
||
|
||
/* None of the ioremap functions actually do anything, other than
|
||
re-casting their argument, so don't bother differentiating them. */
|
||
return ioremap (start, len);
|
||
}
|
||
|
||
void pci_iounmap (struct pci_dev *dev, void __iomem *addr)
|
||
{
|
||
/* nothing */
|
||
}
|
||
|
||
|
||
/* symbol exports (for modules) */
|
||
|
||
EXPORT_SYMBOL (pci_map_single);
|
||
EXPORT_SYMBOL (pci_unmap_single);
|
||
EXPORT_SYMBOL (pci_alloc_consistent);
|
||
EXPORT_SYMBOL (pci_free_consistent);
|
||
EXPORT_SYMBOL (pci_dma_sync_single_for_cpu);
|
||
EXPORT_SYMBOL (pci_dma_sync_single_for_device);
|
||
EXPORT_SYMBOL (pci_iomap);
|
||
EXPORT_SYMBOL (pci_iounmap);
|