![Ingo Molnar](/assets/img/avatar_default.png)
This patch (written by me and also containing many suggestions of Arjan van de Ven) does a major cleanup of the spinlock code. It does the following things: - consolidates and enhances the spinlock/rwlock debugging code - simplifies the asm/spinlock.h files - encapsulates the raw spinlock type and moves generic spinlock features (such as ->break_lock) into the generic code. - cleans up the spinlock code hierarchy to get rid of the spaghetti. Most notably there's now only a single variant of the debugging code, located in lib/spinlock_debug.c. (previously we had one SMP debugging variant per architecture, plus a separate generic one for UP builds) Also, i've enhanced the rwlock debugging facility, it will now track write-owners. There is new spinlock-owner/CPU-tracking on SMP builds too. All locks have lockup detection now, which will work for both soft and hard spin/rwlock lockups. The arch-level include files now only contain the minimally necessary subset of the spinlock code - all the rest that can be generalized now lives in the generic headers: include/asm-i386/spinlock_types.h | 16 include/asm-x86_64/spinlock_types.h | 16 I have also split up the various spinlock variants into separate files, making it easier to see which does what. The new layout is: SMP | UP ----------------------------|----------------------------------- asm/spinlock_types_smp.h | linux/spinlock_types_up.h linux/spinlock_types.h | linux/spinlock_types.h asm/spinlock_smp.h | linux/spinlock_up.h linux/spinlock_api_smp.h | linux/spinlock_api_up.h linux/spinlock.h | linux/spinlock.h /* * here's the role of the various spinlock/rwlock related include files: * * on SMP builds: * * asm/spinlock_types.h: contains the raw_spinlock_t/raw_rwlock_t and the * initializers * * linux/spinlock_types.h: * defines the generic type and initializers * * asm/spinlock.h: contains the __raw_spin_*()/etc. lowlevel * implementations, mostly inline assembly code * * (also included on UP-debug builds:) * * linux/spinlock_api_smp.h: * contains the prototypes for the _spin_*() APIs. * * linux/spinlock.h: builds the final spin_*() APIs. * * on UP builds: * * linux/spinlock_type_up.h: * contains the generic, simplified UP spinlock type. * (which is an empty structure on non-debug builds) * * linux/spinlock_types.h: * defines the generic type and initializers * * linux/spinlock_up.h: * contains the __raw_spin_*()/etc. version of UP * builds. (which are NOPs on non-debug, non-preempt * builds) * * (included on UP-non-debug builds:) * * linux/spinlock_api_up.h: * builds the _spin_*() APIs. * * linux/spinlock.h: builds the final spin_*() APIs. */ All SMP and UP architectures are converted by this patch. arm, i386, ia64, ppc, ppc64, s390/s390x, x64 was build-tested via crosscompilers. m32r, mips, sh, sparc, have not been tested yet, but should be mostly fine. From: Grant Grundler <grundler@parisc-linux.org> Booted and lightly tested on a500-44 (64-bit, SMP kernel, dual CPU). Builds 32-bit SMP kernel (not booted or tested). I did not try to build non-SMP kernels. That should be trivial to fix up later if necessary. I converted bit ops atomic_hash lock to raw_spinlock_t. Doing so avoids some ugly nesting of linux/*.h and asm/*.h files. Those particular locks are well tested and contained entirely inside arch specific code. I do NOT expect any new issues to arise with them. If someone does ever need to use debug/metrics with them, then they will need to unravel this hairball between spinlocks, atomic ops, and bit ops that exist only because parisc has exactly one atomic instruction: LDCW (load and clear word). From: "Luck, Tony" <tony.luck@intel.com> ia64 fix Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Arjan van de Ven <arjanv@infradead.org> Signed-off-by: Grant Grundler <grundler@parisc-linux.org> Cc: Matthew Wilcox <willy@debian.org> Signed-off-by: Hirokazu Takata <takata@linux-m32r.org> Signed-off-by: Mikael Pettersson <mikpe@csd.uu.se> Signed-off-by: Benoit Boissinot <benoit.boissinot@ens-lyon.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
242 lines
5.6 KiB
C
242 lines
5.6 KiB
C
#ifndef __ASM_SPINLOCK_H
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#define __ASM_SPINLOCK_H
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/*
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* Simple spin lock operations.
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*
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* Copyright (C) 2001-2004 Paul Mackerras <paulus@au.ibm.com>, IBM
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* Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
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* Copyright (C) 2002 Dave Engebretsen <engebret@us.ibm.com>, IBM
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* Rework to support virtual processors
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*
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* Type of int is used as a full 64b word is not necessary.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* (the type definitions are in asm/spinlock_types.h)
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*/
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#include <linux/config.h>
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#include <asm/paca.h>
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#include <asm/hvcall.h>
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#include <asm/iSeries/HvCall.h>
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#define __raw_spin_is_locked(x) ((x)->slock != 0)
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/*
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* This returns the old value in the lock, so we succeeded
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* in getting the lock if the return value is 0.
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*/
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static __inline__ unsigned long __spin_trylock(raw_spinlock_t *lock)
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{
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unsigned long tmp, tmp2;
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__asm__ __volatile__(
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" lwz %1,%3(13) # __spin_trylock\n\
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1: lwarx %0,0,%2\n\
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cmpwi 0,%0,0\n\
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bne- 2f\n\
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stwcx. %1,0,%2\n\
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bne- 1b\n\
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isync\n\
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2:" : "=&r" (tmp), "=&r" (tmp2)
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: "r" (&lock->slock), "i" (offsetof(struct paca_struct, lock_token))
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: "cr0", "memory");
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return tmp;
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}
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static int __inline__ __raw_spin_trylock(raw_spinlock_t *lock)
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{
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return __spin_trylock(lock) == 0;
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}
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/*
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* On a system with shared processors (that is, where a physical
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* processor is multiplexed between several virtual processors),
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* there is no point spinning on a lock if the holder of the lock
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* isn't currently scheduled on a physical processor. Instead
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* we detect this situation and ask the hypervisor to give the
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* rest of our timeslice to the lock holder.
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*
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* So that we can tell which virtual processor is holding a lock,
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* we put 0x80000000 | smp_processor_id() in the lock when it is
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* held. Conveniently, we have a word in the paca that holds this
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* value.
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*/
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#if defined(CONFIG_PPC_SPLPAR) || defined(CONFIG_PPC_ISERIES)
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/* We only yield to the hypervisor if we are in shared processor mode */
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#define SHARED_PROCESSOR (get_paca()->lppaca.shared_proc)
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extern void __spin_yield(raw_spinlock_t *lock);
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extern void __rw_yield(raw_rwlock_t *lock);
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#else /* SPLPAR || ISERIES */
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#define __spin_yield(x) barrier()
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#define __rw_yield(x) barrier()
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#define SHARED_PROCESSOR 0
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#endif
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static void __inline__ __raw_spin_lock(raw_spinlock_t *lock)
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{
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while (1) {
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if (likely(__spin_trylock(lock) == 0))
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break;
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do {
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HMT_low();
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if (SHARED_PROCESSOR)
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__spin_yield(lock);
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} while (unlikely(lock->slock != 0));
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HMT_medium();
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}
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}
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static void __inline__ __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
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{
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unsigned long flags_dis;
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while (1) {
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if (likely(__spin_trylock(lock) == 0))
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break;
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local_save_flags(flags_dis);
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local_irq_restore(flags);
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do {
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HMT_low();
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if (SHARED_PROCESSOR)
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__spin_yield(lock);
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} while (unlikely(lock->slock != 0));
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HMT_medium();
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local_irq_restore(flags_dis);
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}
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}
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static __inline__ void __raw_spin_unlock(raw_spinlock_t *lock)
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{
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__asm__ __volatile__("lwsync # __raw_spin_unlock": : :"memory");
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lock->slock = 0;
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}
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extern void __raw_spin_unlock_wait(raw_spinlock_t *lock);
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/*
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* Read-write spinlocks, allowing multiple readers
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* but only one writer.
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*
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* NOTE! it is quite common to have readers in interrupts
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* but no interrupt writers. For those circumstances we
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* can "mix" irq-safe locks - any writer needs to get a
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* irq-safe write-lock, but readers can get non-irqsafe
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* read-locks.
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*/
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#define __raw_read_can_lock(rw) ((rw)->lock >= 0)
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#define __raw_write_can_lock(rw) (!(rw)->lock)
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/*
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* This returns the old value in the lock + 1,
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* so we got a read lock if the return value is > 0.
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*/
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static long __inline__ __read_trylock(raw_rwlock_t *rw)
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{
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long tmp;
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__asm__ __volatile__(
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"1: lwarx %0,0,%1 # read_trylock\n\
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extsw %0,%0\n\
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addic. %0,%0,1\n\
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ble- 2f\n\
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stwcx. %0,0,%1\n\
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bne- 1b\n\
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isync\n\
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2:" : "=&r" (tmp)
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: "r" (&rw->lock)
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: "cr0", "xer", "memory");
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return tmp;
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}
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/*
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* This returns the old value in the lock,
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* so we got the write lock if the return value is 0.
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*/
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static __inline__ long __write_trylock(raw_rwlock_t *rw)
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{
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long tmp, tmp2;
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__asm__ __volatile__(
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" lwz %1,%3(13) # write_trylock\n\
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1: lwarx %0,0,%2\n\
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cmpwi 0,%0,0\n\
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bne- 2f\n\
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stwcx. %1,0,%2\n\
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bne- 1b\n\
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isync\n\
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2:" : "=&r" (tmp), "=&r" (tmp2)
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: "r" (&rw->lock), "i" (offsetof(struct paca_struct, lock_token))
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: "cr0", "memory");
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return tmp;
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}
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static void __inline__ __raw_read_lock(raw_rwlock_t *rw)
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{
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while (1) {
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if (likely(__read_trylock(rw) > 0))
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break;
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do {
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HMT_low();
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if (SHARED_PROCESSOR)
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__rw_yield(rw);
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} while (unlikely(rw->lock < 0));
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HMT_medium();
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}
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}
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static void __inline__ __raw_write_lock(raw_rwlock_t *rw)
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{
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while (1) {
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if (likely(__write_trylock(rw) == 0))
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break;
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do {
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HMT_low();
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if (SHARED_PROCESSOR)
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__rw_yield(rw);
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} while (unlikely(rw->lock != 0));
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HMT_medium();
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}
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}
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static int __inline__ __raw_read_trylock(raw_rwlock_t *rw)
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{
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return __read_trylock(rw) > 0;
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}
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static int __inline__ __raw_write_trylock(raw_rwlock_t *rw)
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{
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return __write_trylock(rw) == 0;
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}
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static void __inline__ __raw_read_unlock(raw_rwlock_t *rw)
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{
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long tmp;
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__asm__ __volatile__(
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"eieio # read_unlock\n\
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1: lwarx %0,0,%1\n\
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addic %0,%0,-1\n\
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stwcx. %0,0,%1\n\
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bne- 1b"
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: "=&r"(tmp)
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: "r"(&rw->lock)
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: "cr0", "memory");
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}
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static __inline__ void __raw_write_unlock(raw_rwlock_t *rw)
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{
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__asm__ __volatile__("lwsync # write_unlock": : :"memory");
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rw->lock = 0;
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}
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#endif /* __ASM_SPINLOCK_H */
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