![Zachary Amsden](/assets/img/avatar_default.png)
The pushf/popf in switch_to are ONLY used to switch IOPL. Making this explicit in C code is more clear. This pushf/popf pair was added as a bugfix for leaking IOPL to unprivileged processes when using sysenter/sysexit based system calls (sysexit does not restore flags). When requesting an IOPL change in sys_iopl(), it is just as easy to change the current flags and the flags in the stack image (in case an IRET is required), but there is no reason to force an IRET if we came in from the SYSENTER path. This change is the minimal solution for supporting a paravirtualized Linux kernel that allows user processes to run with I/O privilege. Other solutions require radical rewrites of part of the low level fault / system call handling code, or do not fully support sysenter based system calls. Unfortunately, this added one field to the thread_struct. But as a bonus, on P4, the fastest time measured for switch_to() went from 312 to 260 cycles, a win of about 17% in the fast case through this performance critical path. Signed-off-by: Zachary Amsden <zach@vmware.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
494 lines
14 KiB
C
494 lines
14 KiB
C
#ifndef __ASM_SYSTEM_H
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#define __ASM_SYSTEM_H
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <asm/segment.h>
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#include <asm/cpufeature.h>
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#include <linux/bitops.h> /* for LOCK_PREFIX */
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#ifdef __KERNEL__
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struct task_struct; /* one of the stranger aspects of C forward declarations.. */
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extern struct task_struct * FASTCALL(__switch_to(struct task_struct *prev, struct task_struct *next));
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#define switch_to(prev,next,last) do { \
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unsigned long esi,edi; \
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asm volatile("pushl %%ebp\n\t" \
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"movl %%esp,%0\n\t" /* save ESP */ \
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"movl %5,%%esp\n\t" /* restore ESP */ \
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"movl $1f,%1\n\t" /* save EIP */ \
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"pushl %6\n\t" /* restore EIP */ \
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"jmp __switch_to\n" \
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"1:\t" \
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"popl %%ebp\n\t" \
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:"=m" (prev->thread.esp),"=m" (prev->thread.eip), \
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"=a" (last),"=S" (esi),"=D" (edi) \
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:"m" (next->thread.esp),"m" (next->thread.eip), \
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"2" (prev), "d" (next)); \
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} while (0)
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#define _set_base(addr,base) do { unsigned long __pr; \
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__asm__ __volatile__ ("movw %%dx,%1\n\t" \
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"rorl $16,%%edx\n\t" \
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"movb %%dl,%2\n\t" \
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"movb %%dh,%3" \
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:"=&d" (__pr) \
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:"m" (*((addr)+2)), \
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"m" (*((addr)+4)), \
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"m" (*((addr)+7)), \
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"0" (base) \
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); } while(0)
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#define _set_limit(addr,limit) do { unsigned long __lr; \
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__asm__ __volatile__ ("movw %%dx,%1\n\t" \
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"rorl $16,%%edx\n\t" \
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"movb %2,%%dh\n\t" \
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"andb $0xf0,%%dh\n\t" \
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"orb %%dh,%%dl\n\t" \
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"movb %%dl,%2" \
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:"=&d" (__lr) \
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:"m" (*(addr)), \
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"m" (*((addr)+6)), \
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"0" (limit) \
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); } while(0)
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#define set_base(ldt,base) _set_base( ((char *)&(ldt)) , (base) )
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#define set_limit(ldt,limit) _set_limit( ((char *)&(ldt)) , ((limit)-1)>>12 )
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static inline unsigned long _get_base(char * addr)
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{
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unsigned long __base;
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__asm__("movb %3,%%dh\n\t"
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"movb %2,%%dl\n\t"
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"shll $16,%%edx\n\t"
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"movw %1,%%dx"
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:"=&d" (__base)
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:"m" (*((addr)+2)),
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"m" (*((addr)+4)),
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"m" (*((addr)+7)));
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return __base;
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}
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#define get_base(ldt) _get_base( ((char *)&(ldt)) )
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/*
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* Load a segment. Fall back on loading the zero
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* segment if something goes wrong..
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*/
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#define loadsegment(seg,value) \
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asm volatile("\n" \
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"1:\t" \
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"mov %0,%%" #seg "\n" \
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"2:\n" \
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".section .fixup,\"ax\"\n" \
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"3:\t" \
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"pushl $0\n\t" \
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"popl %%" #seg "\n\t" \
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"jmp 2b\n" \
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".previous\n" \
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".section __ex_table,\"a\"\n\t" \
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".align 4\n\t" \
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".long 1b,3b\n" \
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".previous" \
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: :"rm" (value))
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/*
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* Save a segment register away
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*/
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#define savesegment(seg, value) \
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asm volatile("mov %%" #seg ",%0":"=rm" (value))
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/*
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* Clear and set 'TS' bit respectively
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*/
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#define clts() __asm__ __volatile__ ("clts")
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#define read_cr0() ({ \
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unsigned int __dummy; \
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__asm__ __volatile__( \
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"movl %%cr0,%0\n\t" \
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:"=r" (__dummy)); \
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__dummy; \
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})
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#define write_cr0(x) \
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__asm__ __volatile__("movl %0,%%cr0": :"r" (x));
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#define read_cr2() ({ \
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unsigned int __dummy; \
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__asm__ __volatile__( \
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"movl %%cr2,%0\n\t" \
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:"=r" (__dummy)); \
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__dummy; \
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})
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#define write_cr2(x) \
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__asm__ __volatile__("movl %0,%%cr2": :"r" (x));
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#define read_cr3() ({ \
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unsigned int __dummy; \
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__asm__ ( \
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"movl %%cr3,%0\n\t" \
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:"=r" (__dummy)); \
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__dummy; \
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})
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#define write_cr3(x) \
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__asm__ __volatile__("movl %0,%%cr3": :"r" (x));
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#define read_cr4() ({ \
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unsigned int __dummy; \
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__asm__( \
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"movl %%cr4,%0\n\t" \
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:"=r" (__dummy)); \
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__dummy; \
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})
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#define write_cr4(x) \
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__asm__ __volatile__("movl %0,%%cr4": :"r" (x));
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#define stts() write_cr0(8 | read_cr0())
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#endif /* __KERNEL__ */
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#define wbinvd() \
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__asm__ __volatile__ ("wbinvd": : :"memory");
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static inline unsigned long get_limit(unsigned long segment)
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{
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unsigned long __limit;
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__asm__("lsll %1,%0"
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:"=r" (__limit):"r" (segment));
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return __limit+1;
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}
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#define nop() __asm__ __volatile__ ("nop")
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#define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
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#define tas(ptr) (xchg((ptr),1))
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struct __xchg_dummy { unsigned long a[100]; };
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#define __xg(x) ((struct __xchg_dummy *)(x))
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/*
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* The semantics of XCHGCMP8B are a bit strange, this is why
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* there is a loop and the loading of %%eax and %%edx has to
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* be inside. This inlines well in most cases, the cached
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* cost is around ~38 cycles. (in the future we might want
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* to do an SIMD/3DNOW!/MMX/FPU 64-bit store here, but that
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* might have an implicit FPU-save as a cost, so it's not
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* clear which path to go.)
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*
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* cmpxchg8b must be used with the lock prefix here to allow
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* the instruction to be executed atomically, see page 3-102
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* of the instruction set reference 24319102.pdf. We need
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* the reader side to see the coherent 64bit value.
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*/
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static inline void __set_64bit (unsigned long long * ptr,
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unsigned int low, unsigned int high)
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{
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__asm__ __volatile__ (
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"\n1:\t"
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"movl (%0), %%eax\n\t"
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"movl 4(%0), %%edx\n\t"
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"lock cmpxchg8b (%0)\n\t"
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"jnz 1b"
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: /* no outputs */
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: "D"(ptr),
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"b"(low),
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"c"(high)
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: "ax","dx","memory");
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}
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static inline void __set_64bit_constant (unsigned long long *ptr,
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unsigned long long value)
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{
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__set_64bit(ptr,(unsigned int)(value), (unsigned int)((value)>>32ULL));
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}
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#define ll_low(x) *(((unsigned int*)&(x))+0)
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#define ll_high(x) *(((unsigned int*)&(x))+1)
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static inline void __set_64bit_var (unsigned long long *ptr,
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unsigned long long value)
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{
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__set_64bit(ptr,ll_low(value), ll_high(value));
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}
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#define set_64bit(ptr,value) \
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(__builtin_constant_p(value) ? \
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__set_64bit_constant(ptr, value) : \
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__set_64bit_var(ptr, value) )
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#define _set_64bit(ptr,value) \
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(__builtin_constant_p(value) ? \
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__set_64bit(ptr, (unsigned int)(value), (unsigned int)((value)>>32ULL) ) : \
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__set_64bit(ptr, ll_low(value), ll_high(value)) )
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/*
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* Note: no "lock" prefix even on SMP: xchg always implies lock anyway
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* Note 2: xchg has side effect, so that attribute volatile is necessary,
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* but generally the primitive is invalid, *ptr is output argument. --ANK
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*/
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static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
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{
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switch (size) {
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case 1:
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__asm__ __volatile__("xchgb %b0,%1"
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:"=q" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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case 2:
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__asm__ __volatile__("xchgw %w0,%1"
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:"=r" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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case 4:
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__asm__ __volatile__("xchgl %0,%1"
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:"=r" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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}
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return x;
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}
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/*
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* Atomic compare and exchange. Compare OLD with MEM, if identical,
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* store NEW in MEM. Return the initial value in MEM. Success is
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* indicated by comparing RETURN with OLD.
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*/
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#ifdef CONFIG_X86_CMPXCHG
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#define __HAVE_ARCH_CMPXCHG 1
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#endif
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static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
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unsigned long new, int size)
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{
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unsigned long prev;
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switch (size) {
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case 1:
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__asm__ __volatile__(LOCK_PREFIX "cmpxchgb %b1,%2"
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: "=a"(prev)
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: "q"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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return prev;
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case 2:
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__asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
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: "=a"(prev)
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: "q"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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return prev;
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case 4:
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__asm__ __volatile__(LOCK_PREFIX "cmpxchgl %1,%2"
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: "=a"(prev)
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: "q"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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return prev;
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}
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return old;
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}
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#define cmpxchg(ptr,o,n)\
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((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
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(unsigned long)(n),sizeof(*(ptr))))
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#ifdef __KERNEL__
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struct alt_instr {
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__u8 *instr; /* original instruction */
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__u8 *replacement;
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__u8 cpuid; /* cpuid bit set for replacement */
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__u8 instrlen; /* length of original instruction */
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__u8 replacementlen; /* length of new instruction, <= instrlen */
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__u8 pad;
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};
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#endif
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/*
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* Alternative instructions for different CPU types or capabilities.
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*
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* This allows to use optimized instructions even on generic binary
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* kernels.
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*
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* length of oldinstr must be longer or equal the length of newinstr
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* It can be padded with nops as needed.
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*
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* For non barrier like inlines please define new variants
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* without volatile and memory clobber.
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*/
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#define alternative(oldinstr, newinstr, feature) \
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asm volatile ("661:\n\t" oldinstr "\n662:\n" \
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".section .altinstructions,\"a\"\n" \
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" .align 4\n" \
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" .long 661b\n" /* label */ \
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" .long 663f\n" /* new instruction */ \
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" .byte %c0\n" /* feature bit */ \
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" .byte 662b-661b\n" /* sourcelen */ \
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" .byte 664f-663f\n" /* replacementlen */ \
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".previous\n" \
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".section .altinstr_replacement,\"ax\"\n" \
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"663:\n\t" newinstr "\n664:\n" /* replacement */ \
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".previous" :: "i" (feature) : "memory")
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/*
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* Alternative inline assembly with input.
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*
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* Pecularities:
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* No memory clobber here.
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* Argument numbers start with 1.
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* Best is to use constraints that are fixed size (like (%1) ... "r")
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* If you use variable sized constraints like "m" or "g" in the
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* replacement maake sure to pad to the worst case length.
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*/
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#define alternative_input(oldinstr, newinstr, feature, input...) \
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asm volatile ("661:\n\t" oldinstr "\n662:\n" \
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".section .altinstructions,\"a\"\n" \
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" .align 4\n" \
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" .long 661b\n" /* label */ \
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" .long 663f\n" /* new instruction */ \
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" .byte %c0\n" /* feature bit */ \
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" .byte 662b-661b\n" /* sourcelen */ \
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" .byte 664f-663f\n" /* replacementlen */ \
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".previous\n" \
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".section .altinstr_replacement,\"ax\"\n" \
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"663:\n\t" newinstr "\n664:\n" /* replacement */ \
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".previous" :: "i" (feature), ##input)
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/*
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* Force strict CPU ordering.
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* And yes, this is required on UP too when we're talking
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* to devices.
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*
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* For now, "wmb()" doesn't actually do anything, as all
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* Intel CPU's follow what Intel calls a *Processor Order*,
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* in which all writes are seen in the program order even
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* outside the CPU.
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*
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* I expect future Intel CPU's to have a weaker ordering,
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* but I'd also expect them to finally get their act together
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* and add some real memory barriers if so.
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*
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* Some non intel clones support out of order store. wmb() ceases to be a
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* nop for these.
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*/
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/*
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* Actually only lfence would be needed for mb() because all stores done
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* by the kernel should be already ordered. But keep a full barrier for now.
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*/
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#define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
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#define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
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/**
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* read_barrier_depends - Flush all pending reads that subsequents reads
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* depend on.
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*
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* No data-dependent reads from memory-like regions are ever reordered
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* over this barrier. All reads preceding this primitive are guaranteed
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* to access memory (but not necessarily other CPUs' caches) before any
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* reads following this primitive that depend on the data return by
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* any of the preceding reads. This primitive is much lighter weight than
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* rmb() on most CPUs, and is never heavier weight than is
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* rmb().
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*
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* These ordering constraints are respected by both the local CPU
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* and the compiler.
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*
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* Ordering is not guaranteed by anything other than these primitives,
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* not even by data dependencies. See the documentation for
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* memory_barrier() for examples and URLs to more information.
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*
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* For example, the following code would force ordering (the initial
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* value of "a" is zero, "b" is one, and "p" is "&a"):
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*
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* <programlisting>
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* CPU 0 CPU 1
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*
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* b = 2;
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* memory_barrier();
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* p = &b; q = p;
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* read_barrier_depends();
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* d = *q;
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* </programlisting>
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*
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* because the read of "*q" depends on the read of "p" and these
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* two reads are separated by a read_barrier_depends(). However,
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* the following code, with the same initial values for "a" and "b":
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*
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* <programlisting>
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* CPU 0 CPU 1
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*
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* a = 2;
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* memory_barrier();
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* b = 3; y = b;
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* read_barrier_depends();
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* x = a;
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* </programlisting>
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*
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* does not enforce ordering, since there is no data dependency between
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* the read of "a" and the read of "b". Therefore, on some CPUs, such
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* as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
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* in cases like thiswhere there are no data dependencies.
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**/
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#define read_barrier_depends() do { } while(0)
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#ifdef CONFIG_X86_OOSTORE
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/* Actually there are no OOO store capable CPUs for now that do SSE,
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but make it already an possibility. */
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#define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
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#else
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#define wmb() __asm__ __volatile__ ("": : :"memory")
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#endif
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#ifdef CONFIG_SMP
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define smp_read_barrier_depends() read_barrier_depends()
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#define set_mb(var, value) do { xchg(&var, value); } while (0)
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#else
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() do { } while(0)
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#define set_mb(var, value) do { var = value; barrier(); } while (0)
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#endif
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#define set_wmb(var, value) do { var = value; wmb(); } while (0)
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/* interrupt control.. */
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#define local_save_flags(x) do { typecheck(unsigned long,x); __asm__ __volatile__("pushfl ; popl %0":"=g" (x): /* no input */); } while (0)
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#define local_irq_restore(x) do { typecheck(unsigned long,x); __asm__ __volatile__("pushl %0 ; popfl": /* no output */ :"g" (x):"memory", "cc"); } while (0)
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#define local_irq_disable() __asm__ __volatile__("cli": : :"memory")
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#define local_irq_enable() __asm__ __volatile__("sti": : :"memory")
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/* used in the idle loop; sti takes one instruction cycle to complete */
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#define safe_halt() __asm__ __volatile__("sti; hlt": : :"memory")
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/* used when interrupts are already enabled or to shutdown the processor */
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#define halt() __asm__ __volatile__("hlt": : :"memory")
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#define irqs_disabled() \
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({ \
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unsigned long flags; \
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local_save_flags(flags); \
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!(flags & (1<<9)); \
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})
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/* For spinlocks etc */
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#define local_irq_save(x) __asm__ __volatile__("pushfl ; popl %0 ; cli":"=g" (x): /* no input */ :"memory")
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/*
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* disable hlt during certain critical i/o operations
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*/
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#define HAVE_DISABLE_HLT
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void disable_hlt(void);
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void enable_hlt(void);
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extern int es7000_plat;
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void cpu_idle_wait(void);
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extern unsigned long arch_align_stack(unsigned long sp);
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#endif
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