![H. Peter Anvin](/assets/img/avatar_default.png)
Fix incorrect assembly constraints. In particular, fix memory constraints used inside push..pop, which can cause invalid operation since gcc may generate %esp-relative references. Additionally: outl() should have "dN" not "dn". query_mca() shouldn't listen 16/32-bit registers in an 8-bit only context. has_eflag(): the "mask" is only used well after both the stack pointer and the output registers have been touched; this requires the output registers to be earlyclobbers (=&) and the input to exclude memory (so "ri", not "g"). Thanks to Etienne Lorrain and Chuck Ebbert for prompting this review. Cc: Etienne Lorrain <etienne_lorrain@yahoo.fr> Cc: Chuck Ebbert <cebbert@redhat.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
268 lines
6.1 KiB
C
268 lines
6.1 KiB
C
/* -*- linux-c -*- ------------------------------------------------------- *
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*
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* Copyright (C) 1991, 1992 Linus Torvalds
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* Copyright 2007 rPath, Inc. - All Rights Reserved
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*
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* This file is part of the Linux kernel, and is made available under
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* the terms of the GNU General Public License version 2.
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*
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* ----------------------------------------------------------------------- */
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/*
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* arch/i386/boot/cpucheck.c
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*
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* Check for obligatory CPU features and abort if the features are not
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* present. This code should be compilable as 16-, 32- or 64-bit
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* code, so be very careful with types and inline assembly.
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*
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* This code should not contain any messages; that requires an
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* additional wrapper.
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*
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* As written, this code is not safe for inclusion into the kernel
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* proper (after FPU initialization, in particular).
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*/
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#ifdef _SETUP
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# include "boot.h"
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# include "bitops.h"
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#endif
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#include <linux/types.h>
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#include <asm/cpufeature.h>
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#include <asm/processor-flags.h>
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#include <asm/required-features.h>
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#include <asm/msr-index.h>
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struct cpu_features {
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int level; /* Family, or 64 for x86-64 */
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int model;
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u32 flags[NCAPINTS];
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};
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static struct cpu_features cpu;
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static u32 cpu_vendor[3];
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static u32 err_flags[NCAPINTS];
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#ifdef CONFIG_X86_64
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static const int req_level = 64;
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#elif defined(CONFIG_X86_MINIMUM_CPU_FAMILY)
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static const int req_level = CONFIG_X86_MINIMUM_CPU_FAMILY;
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#else
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static const int req_level = 3;
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#endif
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static const u32 req_flags[NCAPINTS] =
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{
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REQUIRED_MASK0,
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REQUIRED_MASK1,
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REQUIRED_MASK2,
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REQUIRED_MASK3,
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REQUIRED_MASK4,
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REQUIRED_MASK5,
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REQUIRED_MASK6,
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REQUIRED_MASK7,
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};
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#define A32(a,b,c,d) (((d) << 24)+((c) << 16)+((b) << 8)+(a))
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static int is_amd(void)
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{
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return cpu_vendor[0] == A32('A','u','t','h') &&
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cpu_vendor[1] == A32('e','n','t','i') &&
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cpu_vendor[2] == A32('c','A','M','D');
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}
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static int is_centaur(void)
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{
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return cpu_vendor[0] == A32('C','e','n','t') &&
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cpu_vendor[1] == A32('a','u','r','H') &&
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cpu_vendor[2] == A32('a','u','l','s');
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}
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static int is_transmeta(void)
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{
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return cpu_vendor[0] == A32('G','e','n','u') &&
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cpu_vendor[1] == A32('i','n','e','T') &&
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cpu_vendor[2] == A32('M','x','8','6');
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}
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static int has_fpu(void)
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{
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u16 fcw = -1, fsw = -1;
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u32 cr0;
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asm("movl %%cr0,%0" : "=r" (cr0));
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if (cr0 & (X86_CR0_EM|X86_CR0_TS)) {
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cr0 &= ~(X86_CR0_EM|X86_CR0_TS);
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asm volatile("movl %0,%%cr0" : : "r" (cr0));
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}
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asm("fninit ; fnstsw %0 ; fnstcw %1" : "+m" (fsw), "+m" (fcw));
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return fsw == 0 && (fcw & 0x103f) == 0x003f;
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}
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static int has_eflag(u32 mask)
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{
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u32 f0, f1;
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asm("pushfl ; "
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"pushfl ; "
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"popl %0 ; "
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"movl %0,%1 ; "
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"xorl %2,%1 ; "
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"pushl %1 ; "
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"popfl ; "
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"pushfl ; "
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"popl %1 ; "
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"popfl"
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: "=&r" (f0), "=&r" (f1)
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: "ri" (mask));
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return !!((f0^f1) & mask);
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}
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static void get_flags(void)
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{
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u32 max_intel_level, max_amd_level;
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u32 tfms;
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if (has_fpu())
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set_bit(X86_FEATURE_FPU, cpu.flags);
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if (has_eflag(X86_EFLAGS_ID)) {
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asm("cpuid"
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: "=a" (max_intel_level),
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"=b" (cpu_vendor[0]),
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"=d" (cpu_vendor[1]),
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"=c" (cpu_vendor[2])
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: "a" (0));
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if (max_intel_level >= 0x00000001 &&
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max_intel_level <= 0x0000ffff) {
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asm("cpuid"
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: "=a" (tfms),
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"=c" (cpu.flags[4]),
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"=d" (cpu.flags[0])
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: "a" (0x00000001)
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: "ebx");
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cpu.level = (tfms >> 8) & 15;
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cpu.model = (tfms >> 4) & 15;
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if (cpu.level >= 6)
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cpu.model += ((tfms >> 16) & 0xf) << 4;
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}
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asm("cpuid"
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: "=a" (max_amd_level)
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: "a" (0x80000000)
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: "ebx", "ecx", "edx");
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if (max_amd_level >= 0x80000001 &&
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max_amd_level <= 0x8000ffff) {
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u32 eax = 0x80000001;
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asm("cpuid"
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: "+a" (eax),
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"=c" (cpu.flags[6]),
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"=d" (cpu.flags[1])
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: : "ebx");
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}
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}
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}
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/* Returns a bitmask of which words we have error bits in */
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static int check_flags(void)
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{
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u32 err;
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int i;
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err = 0;
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for (i = 0; i < NCAPINTS; i++) {
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err_flags[i] = req_flags[i] & ~cpu.flags[i];
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if (err_flags[i])
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err |= 1 << i;
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}
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return err;
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}
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/*
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* Returns -1 on error.
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*
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* *cpu_level is set to the current CPU level; *req_level to the required
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* level. x86-64 is considered level 64 for this purpose.
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*
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* *err_flags_ptr is set to the flags error array if there are flags missing.
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*/
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int check_cpu(int *cpu_level_ptr, int *req_level_ptr, u32 **err_flags_ptr)
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{
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int err;
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memset(&cpu.flags, 0, sizeof cpu.flags);
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cpu.level = 3;
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if (has_eflag(X86_EFLAGS_AC))
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cpu.level = 4;
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get_flags();
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err = check_flags();
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if (test_bit(X86_FEATURE_LM, cpu.flags))
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cpu.level = 64;
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if (err == 0x01 &&
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!(err_flags[0] &
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~((1 << X86_FEATURE_XMM)|(1 << X86_FEATURE_XMM2))) &&
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is_amd()) {
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/* If this is an AMD and we're only missing SSE+SSE2, try to
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turn them on */
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u32 ecx = MSR_K7_HWCR;
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u32 eax, edx;
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asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
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eax &= ~(1 << 15);
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asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));
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get_flags(); /* Make sure it really did something */
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err = check_flags();
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} else if (err == 0x01 &&
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!(err_flags[0] & ~(1 << X86_FEATURE_CX8)) &&
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is_centaur() && cpu.model >= 6) {
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/* If this is a VIA C3, we might have to enable CX8
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explicitly */
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u32 ecx = MSR_VIA_FCR;
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u32 eax, edx;
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asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
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eax |= (1<<1)|(1<<7);
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asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));
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set_bit(X86_FEATURE_CX8, cpu.flags);
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err = check_flags();
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} else if (err == 0x01 && is_transmeta()) {
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/* Transmeta might have masked feature bits in word 0 */
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u32 ecx = 0x80860004;
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u32 eax, edx;
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u32 level = 1;
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asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
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asm("wrmsr" : : "a" (~0), "d" (edx), "c" (ecx));
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asm("cpuid"
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: "+a" (level), "=d" (cpu.flags[0])
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: : "ecx", "ebx");
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asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));
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err = check_flags();
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}
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if (err_flags_ptr)
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*err_flags_ptr = err ? err_flags : NULL;
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if (cpu_level_ptr)
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*cpu_level_ptr = cpu.level;
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if (req_level_ptr)
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*req_level_ptr = req_level;
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return (cpu.level < req_level || err) ? -1 : 0;
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}
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