![Suravee Suthikulpanit](/assets/img/avatar_default.png)
This patch adds the logic for enabling additional IBS control bits : * IBS-Fetch IbsRandEn bit (bit 57) * IBS-Op IbsOpCntCtl bit (bit 19) Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Robert Richter <robert.richter@amd.com>
547 lines
14 KiB
C
547 lines
14 KiB
C
/*
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* @file op_model_amd.c
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* athlon / K7 / K8 / Family 10h model-specific MSR operations
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*
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* @remark Copyright 2002-2008 OProfile authors
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* @remark Read the file COPYING
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*
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* @author John Levon
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* @author Philippe Elie
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* @author Graydon Hoare
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* @author Robert Richter <robert.richter@amd.com>
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* @author Barry Kasindorf
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*/
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#include <linux/oprofile.h>
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#include <linux/device.h>
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#include <linux/pci.h>
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#include <asm/ptrace.h>
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#include <asm/msr.h>
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#include <asm/nmi.h>
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#include "op_x86_model.h"
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#include "op_counter.h"
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#define NUM_COUNTERS 4
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#define NUM_CONTROLS 4
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#define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0)
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#define CTR_READ(l, h, msrs, c) do {rdmsr(msrs->counters[(c)].addr, (l), (h)); } while (0)
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#define CTR_WRITE(l, msrs, c) do {wrmsr(msrs->counters[(c)].addr, -(unsigned int)(l), -1); } while (0)
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#define CTR_OVERFLOWED(n) (!((n) & (1U<<31)))
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#define CTRL_IS_RESERVED(msrs, c) (msrs->controls[(c)].addr ? 1 : 0)
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#define CTRL_READ(l, h, msrs, c) do {rdmsr(msrs->controls[(c)].addr, (l), (h)); } while (0)
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#define CTRL_WRITE(l, h, msrs, c) do {wrmsr(msrs->controls[(c)].addr, (l), (h)); } while (0)
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#define CTRL_SET_ACTIVE(n) (n |= (1<<22))
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#define CTRL_SET_INACTIVE(n) (n &= ~(1<<22))
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#define CTRL_CLEAR_LO(x) (x &= (1<<21))
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#define CTRL_CLEAR_HI(x) (x &= 0xfffffcf0)
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#define CTRL_SET_ENABLE(val) (val |= 1<<20)
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#define CTRL_SET_USR(val, u) (val |= ((u & 1) << 16))
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#define CTRL_SET_KERN(val, k) (val |= ((k & 1) << 17))
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#define CTRL_SET_UM(val, m) (val |= (m << 8))
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#define CTRL_SET_EVENT_LOW(val, e) (val |= (e & 0xff))
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#define CTRL_SET_EVENT_HIGH(val, e) (val |= ((e >> 8) & 0xf))
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#define CTRL_SET_HOST_ONLY(val, h) (val |= ((h & 1) << 9))
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#define CTRL_SET_GUEST_ONLY(val, h) (val |= ((h & 1) << 8))
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static unsigned long reset_value[NUM_COUNTERS];
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#ifdef CONFIG_OPROFILE_IBS
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/* IbsFetchCtl bits/masks */
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#define IBS_FETCH_HIGH_VALID_BIT (1UL << 17) /* bit 49 */
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#define IBS_FETCH_HIGH_ENABLE (1UL << 16) /* bit 48 */
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#define IBS_FETCH_LOW_MAX_CNT_MASK 0x0000FFFFUL /* MaxCnt mask */
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/*IbsOpCtl bits */
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#define IBS_OP_LOW_VALID_BIT (1ULL<<18) /* bit 18 */
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#define IBS_OP_LOW_ENABLE (1ULL<<17) /* bit 17 */
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/* Codes used in cpu_buffer.c */
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/* This produces duplicate code, need to be fixed */
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#define IBS_FETCH_BEGIN 3
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#define IBS_OP_BEGIN 4
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/* The function interface needs to be fixed, something like add
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data. Should then be added to linux/oprofile.h. */
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extern void
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oprofile_add_ibs_sample(struct pt_regs *const regs,
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unsigned int *const ibs_sample, int ibs_code);
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struct ibs_fetch_sample {
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/* MSRC001_1031 IBS Fetch Linear Address Register */
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unsigned int ibs_fetch_lin_addr_low;
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unsigned int ibs_fetch_lin_addr_high;
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/* MSRC001_1030 IBS Fetch Control Register */
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unsigned int ibs_fetch_ctl_low;
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unsigned int ibs_fetch_ctl_high;
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/* MSRC001_1032 IBS Fetch Physical Address Register */
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unsigned int ibs_fetch_phys_addr_low;
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unsigned int ibs_fetch_phys_addr_high;
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};
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struct ibs_op_sample {
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/* MSRC001_1034 IBS Op Logical Address Register (IbsRIP) */
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unsigned int ibs_op_rip_low;
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unsigned int ibs_op_rip_high;
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/* MSRC001_1035 IBS Op Data Register */
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unsigned int ibs_op_data1_low;
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unsigned int ibs_op_data1_high;
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/* MSRC001_1036 IBS Op Data 2 Register */
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unsigned int ibs_op_data2_low;
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unsigned int ibs_op_data2_high;
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/* MSRC001_1037 IBS Op Data 3 Register */
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unsigned int ibs_op_data3_low;
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unsigned int ibs_op_data3_high;
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/* MSRC001_1038 IBS DC Linear Address Register (IbsDcLinAd) */
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unsigned int ibs_dc_linear_low;
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unsigned int ibs_dc_linear_high;
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/* MSRC001_1039 IBS DC Physical Address Register (IbsDcPhysAd) */
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unsigned int ibs_dc_phys_low;
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unsigned int ibs_dc_phys_high;
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};
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/*
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* unitialize the APIC for the IBS interrupts if needed on AMD Family10h+
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*/
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static void clear_ibs_nmi(void);
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static int ibs_allowed; /* AMD Family10h and later */
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struct op_ibs_config {
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unsigned long op_enabled;
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unsigned long fetch_enabled;
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unsigned long max_cnt_fetch;
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unsigned long max_cnt_op;
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unsigned long rand_en;
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unsigned long dispatched_ops;
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};
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static struct op_ibs_config ibs_config;
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#endif
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/* functions for op_amd_spec */
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static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
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{
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int i;
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for (i = 0; i < NUM_COUNTERS; i++) {
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if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
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msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
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else
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msrs->counters[i].addr = 0;
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}
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for (i = 0; i < NUM_CONTROLS; i++) {
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if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
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msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
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else
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msrs->controls[i].addr = 0;
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}
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}
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static void op_amd_setup_ctrs(struct op_msrs const * const msrs)
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{
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unsigned int low, high;
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int i;
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/* clear all counters */
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for (i = 0 ; i < NUM_CONTROLS; ++i) {
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if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
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continue;
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CTRL_READ(low, high, msrs, i);
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CTRL_CLEAR_LO(low);
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CTRL_CLEAR_HI(high);
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CTRL_WRITE(low, high, msrs, i);
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}
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/* avoid a false detection of ctr overflows in NMI handler */
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for (i = 0; i < NUM_COUNTERS; ++i) {
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if (unlikely(!CTR_IS_RESERVED(msrs, i)))
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continue;
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CTR_WRITE(1, msrs, i);
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}
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/* enable active counters */
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for (i = 0; i < NUM_COUNTERS; ++i) {
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if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) {
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reset_value[i] = counter_config[i].count;
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CTR_WRITE(counter_config[i].count, msrs, i);
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CTRL_READ(low, high, msrs, i);
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CTRL_CLEAR_LO(low);
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CTRL_CLEAR_HI(high);
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CTRL_SET_ENABLE(low);
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CTRL_SET_USR(low, counter_config[i].user);
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CTRL_SET_KERN(low, counter_config[i].kernel);
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CTRL_SET_UM(low, counter_config[i].unit_mask);
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CTRL_SET_EVENT_LOW(low, counter_config[i].event);
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CTRL_SET_EVENT_HIGH(high, counter_config[i].event);
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CTRL_SET_HOST_ONLY(high, 0);
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CTRL_SET_GUEST_ONLY(high, 0);
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CTRL_WRITE(low, high, msrs, i);
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} else {
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reset_value[i] = 0;
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}
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}
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}
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#ifdef CONFIG_OPROFILE_IBS
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static inline int
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op_amd_handle_ibs(struct pt_regs * const regs,
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struct op_msrs const * const msrs)
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{
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unsigned int low, high;
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struct ibs_fetch_sample ibs_fetch;
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struct ibs_op_sample ibs_op;
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if (!ibs_allowed)
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return 1;
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if (ibs_config.fetch_enabled) {
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rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
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if (high & IBS_FETCH_HIGH_VALID_BIT) {
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ibs_fetch.ibs_fetch_ctl_high = high;
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ibs_fetch.ibs_fetch_ctl_low = low;
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rdmsr(MSR_AMD64_IBSFETCHLINAD, low, high);
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ibs_fetch.ibs_fetch_lin_addr_high = high;
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ibs_fetch.ibs_fetch_lin_addr_low = low;
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rdmsr(MSR_AMD64_IBSFETCHPHYSAD, low, high);
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ibs_fetch.ibs_fetch_phys_addr_high = high;
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ibs_fetch.ibs_fetch_phys_addr_low = low;
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oprofile_add_ibs_sample(regs,
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(unsigned int *)&ibs_fetch,
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IBS_FETCH_BEGIN);
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/*reenable the IRQ */
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rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
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high &= ~IBS_FETCH_HIGH_VALID_BIT;
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high |= IBS_FETCH_HIGH_ENABLE;
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low &= IBS_FETCH_LOW_MAX_CNT_MASK;
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wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
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}
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}
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if (ibs_config.op_enabled) {
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rdmsr(MSR_AMD64_IBSOPCTL, low, high);
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if (low & IBS_OP_LOW_VALID_BIT) {
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rdmsr(MSR_AMD64_IBSOPRIP, low, high);
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ibs_op.ibs_op_rip_low = low;
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ibs_op.ibs_op_rip_high = high;
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rdmsr(MSR_AMD64_IBSOPDATA, low, high);
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ibs_op.ibs_op_data1_low = low;
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ibs_op.ibs_op_data1_high = high;
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rdmsr(MSR_AMD64_IBSOPDATA2, low, high);
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ibs_op.ibs_op_data2_low = low;
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ibs_op.ibs_op_data2_high = high;
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rdmsr(MSR_AMD64_IBSOPDATA3, low, high);
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ibs_op.ibs_op_data3_low = low;
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ibs_op.ibs_op_data3_high = high;
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rdmsr(MSR_AMD64_IBSDCLINAD, low, high);
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ibs_op.ibs_dc_linear_low = low;
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ibs_op.ibs_dc_linear_high = high;
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rdmsr(MSR_AMD64_IBSDCPHYSAD, low, high);
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ibs_op.ibs_dc_phys_low = low;
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ibs_op.ibs_dc_phys_high = high;
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/* reenable the IRQ */
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oprofile_add_ibs_sample(regs,
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(unsigned int *)&ibs_op,
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IBS_OP_BEGIN);
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rdmsr(MSR_AMD64_IBSOPCTL, low, high);
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high = 0;
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low &= ~IBS_OP_LOW_VALID_BIT;
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low |= IBS_OP_LOW_ENABLE;
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wrmsr(MSR_AMD64_IBSOPCTL, low, high);
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}
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}
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return 1;
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}
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#endif
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static int op_amd_check_ctrs(struct pt_regs * const regs,
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struct op_msrs const * const msrs)
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{
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unsigned int low, high;
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int i;
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for (i = 0 ; i < NUM_COUNTERS; ++i) {
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if (!reset_value[i])
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continue;
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CTR_READ(low, high, msrs, i);
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if (CTR_OVERFLOWED(low)) {
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oprofile_add_sample(regs, i);
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CTR_WRITE(reset_value[i], msrs, i);
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}
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}
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#ifdef CONFIG_OPROFILE_IBS
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op_amd_handle_ibs(regs, msrs);
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#endif
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/* See op_model_ppro.c */
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return 1;
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}
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static void op_amd_start(struct op_msrs const * const msrs)
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{
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unsigned int low, high;
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int i;
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for (i = 0 ; i < NUM_COUNTERS ; ++i) {
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if (reset_value[i]) {
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CTRL_READ(low, high, msrs, i);
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CTRL_SET_ACTIVE(low);
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CTRL_WRITE(low, high, msrs, i);
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}
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}
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#ifdef CONFIG_OPROFILE_IBS
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if (ibs_allowed && ibs_config.fetch_enabled) {
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low = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
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high = ((ibs_config.rand_en & 0x1) << 25) /* bit 57 */
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+ IBS_FETCH_HIGH_ENABLE;
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wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
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}
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if (ibs_allowed && ibs_config.op_enabled) {
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low = ((ibs_config.max_cnt_op >> 4) & 0xFFFF)
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+ ((ibs_config.dispatched_ops & 0x1) << 19) /* bit 19 */
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+ IBS_OP_LOW_ENABLE;
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high = 0;
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wrmsr(MSR_AMD64_IBSOPCTL, low, high);
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}
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#endif
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}
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static void op_amd_stop(struct op_msrs const * const msrs)
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{
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unsigned int low, high;
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int i;
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/* Subtle: stop on all counters to avoid race with
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* setting our pm callback */
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for (i = 0 ; i < NUM_COUNTERS ; ++i) {
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if (!reset_value[i])
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continue;
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CTRL_READ(low, high, msrs, i);
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CTRL_SET_INACTIVE(low);
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CTRL_WRITE(low, high, msrs, i);
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}
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#ifdef CONFIG_OPROFILE_IBS
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if (ibs_allowed && ibs_config.fetch_enabled) {
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low = 0; /* clear max count and enable */
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high = 0;
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wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
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}
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if (ibs_allowed && ibs_config.op_enabled) {
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low = 0; /* clear max count and enable */
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high = 0;
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wrmsr(MSR_AMD64_IBSOPCTL, low, high);
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}
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#endif
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}
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static void op_amd_shutdown(struct op_msrs const * const msrs)
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{
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int i;
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for (i = 0 ; i < NUM_COUNTERS ; ++i) {
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if (CTR_IS_RESERVED(msrs, i))
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release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
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}
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for (i = 0 ; i < NUM_CONTROLS ; ++i) {
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if (CTRL_IS_RESERVED(msrs, i))
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release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
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}
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}
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#ifndef CONFIG_OPROFILE_IBS
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/* no IBS support */
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static int op_amd_init(struct oprofile_operations *ops)
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{
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return 0;
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}
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static void op_amd_exit(void) {}
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#else
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static u8 ibs_eilvt_off;
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static inline void apic_init_ibs_nmi_per_cpu(void *arg)
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{
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ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
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}
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static inline void apic_clear_ibs_nmi_per_cpu(void *arg)
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{
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setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
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}
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static int pfm_amd64_setup_eilvt(void)
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{
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#define IBSCTL_LVTOFFSETVAL (1 << 8)
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#define IBSCTL 0x1cc
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struct pci_dev *cpu_cfg;
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int nodes;
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u32 value = 0;
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/* per CPU setup */
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on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1);
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nodes = 0;
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cpu_cfg = NULL;
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do {
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cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
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PCI_DEVICE_ID_AMD_10H_NB_MISC,
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cpu_cfg);
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if (!cpu_cfg)
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break;
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++nodes;
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pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
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| IBSCTL_LVTOFFSETVAL);
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pci_read_config_dword(cpu_cfg, IBSCTL, &value);
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if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) {
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printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
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"IBSCTL = 0x%08x", value);
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return 1;
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}
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} while (1);
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if (!nodes) {
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printk(KERN_DEBUG "No CPU node configured for IBS");
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return 1;
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}
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#ifdef CONFIG_NUMA
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/* Sanity check */
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/* Works only for 64bit with proper numa implementation. */
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if (nodes != num_possible_nodes()) {
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printk(KERN_DEBUG "Failed to setup CPU node(s) for IBS, "
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"found: %d, expected %d",
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nodes, num_possible_nodes());
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return 1;
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}
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#endif
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return 0;
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}
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/*
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* initialize the APIC for the IBS interrupts
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* if available (AMD Family10h rev B0 and later)
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*/
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static void setup_ibs(void)
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{
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ibs_allowed = boot_cpu_has(X86_FEATURE_IBS);
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if (!ibs_allowed)
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return;
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if (pfm_amd64_setup_eilvt()) {
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ibs_allowed = 0;
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return;
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}
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printk(KERN_INFO "oprofile: AMD IBS detected\n");
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|
}
|
|
|
|
|
|
/*
|
|
* unitialize the APIC for the IBS interrupts if needed on AMD Family10h
|
|
* rev B0 and later */
|
|
static void clear_ibs_nmi(void)
|
|
{
|
|
if (ibs_allowed)
|
|
on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1);
|
|
}
|
|
|
|
static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
|
|
|
|
static int setup_ibs_files(struct super_block *sb, struct dentry *root)
|
|
{
|
|
struct dentry *dir;
|
|
int ret = 0;
|
|
|
|
/* architecture specific files */
|
|
if (create_arch_files)
|
|
ret = create_arch_files(sb, root);
|
|
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (!ibs_allowed)
|
|
return ret;
|
|
|
|
/* model specific files */
|
|
|
|
/* setup some reasonable defaults */
|
|
ibs_config.max_cnt_fetch = 250000;
|
|
ibs_config.fetch_enabled = 0;
|
|
ibs_config.max_cnt_op = 250000;
|
|
ibs_config.op_enabled = 0;
|
|
ibs_config.dispatched_ops = 1;
|
|
|
|
dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
|
|
oprofilefs_create_ulong(sb, dir, "enable",
|
|
&ibs_config.fetch_enabled);
|
|
oprofilefs_create_ulong(sb, dir, "max_count",
|
|
&ibs_config.max_cnt_fetch);
|
|
oprofilefs_create_ulong(sb, dir, "rand_enable",
|
|
&ibs_config.rand_en);
|
|
|
|
dir = oprofilefs_mkdir(sb, root, "ibs_op");
|
|
oprofilefs_create_ulong(sb, dir, "enable",
|
|
&ibs_config.op_enabled);
|
|
oprofilefs_create_ulong(sb, dir, "max_count",
|
|
&ibs_config.max_cnt_op);
|
|
oprofilefs_create_ulong(sb, dir, "dispatched_ops",
|
|
&ibs_config.dispatched_ops);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int op_amd_init(struct oprofile_operations *ops)
|
|
{
|
|
setup_ibs();
|
|
create_arch_files = ops->create_files;
|
|
ops->create_files = setup_ibs_files;
|
|
return 0;
|
|
}
|
|
|
|
static void op_amd_exit(void)
|
|
{
|
|
clear_ibs_nmi();
|
|
}
|
|
|
|
#endif
|
|
|
|
struct op_x86_model_spec const op_amd_spec = {
|
|
.init = op_amd_init,
|
|
.exit = op_amd_exit,
|
|
.num_counters = NUM_COUNTERS,
|
|
.num_controls = NUM_CONTROLS,
|
|
.fill_in_addresses = &op_amd_fill_in_addresses,
|
|
.setup_ctrs = &op_amd_setup_ctrs,
|
|
.check_ctrs = &op_amd_check_ctrs,
|
|
.start = &op_amd_start,
|
|
.stop = &op_amd_stop,
|
|
.shutdown = &op_amd_shutdown
|
|
};
|