![Guillaume Thouvenin](/assets/img/avatar_default.png)
For instruction 'and al,imm' we use DstAcc instead of doing the emulation directly into the instruction's opcode. Signed-off-by: Guillaume Thouvenin <guillaume.thouvenin@ext.bull.net> Signed-off-by: Avi Kivity <avi@qumranet.com>
2080 lines
56 KiB
C
2080 lines
56 KiB
C
/******************************************************************************
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* x86_emulate.c
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*
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* Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
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*
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* Copyright (c) 2005 Keir Fraser
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*
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* Linux coding style, mod r/m decoder, segment base fixes, real-mode
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* privileged instructions:
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*
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* Copyright (C) 2006 Qumranet
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*
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* Avi Kivity <avi@qumranet.com>
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* Yaniv Kamay <yaniv@qumranet.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See
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* the COPYING file in the top-level directory.
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*
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* From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
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*/
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#ifndef __KERNEL__
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#include <stdio.h>
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#include <stdint.h>
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#include <public/xen.h>
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#define DPRINTF(_f, _a ...) printf(_f , ## _a)
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#else
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#include <linux/kvm_host.h>
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#include "kvm_cache_regs.h"
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#define DPRINTF(x...) do {} while (0)
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#endif
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#include <linux/module.h>
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#include <asm/kvm_x86_emulate.h>
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/*
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* Opcode effective-address decode tables.
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* Note that we only emulate instructions that have at least one memory
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* operand (excluding implicit stack references). We assume that stack
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* references and instruction fetches will never occur in special memory
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* areas that require emulation. So, for example, 'mov <imm>,<reg>' need
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* not be handled.
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*/
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/* Operand sizes: 8-bit operands or specified/overridden size. */
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#define ByteOp (1<<0) /* 8-bit operands. */
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/* Destination operand type. */
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#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
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#define DstReg (2<<1) /* Register operand. */
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#define DstMem (3<<1) /* Memory operand. */
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#define DstAcc (4<<1) /* Destination Accumulator */
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#define DstMask (7<<1)
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/* Source operand type. */
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#define SrcNone (0<<4) /* No source operand. */
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#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
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#define SrcReg (1<<4) /* Register operand. */
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#define SrcMem (2<<4) /* Memory operand. */
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#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
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#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
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#define SrcImm (5<<4) /* Immediate operand. */
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#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
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#define SrcMask (7<<4)
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/* Generic ModRM decode. */
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#define ModRM (1<<7)
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/* Destination is only written; never read. */
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#define Mov (1<<8)
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#define BitOp (1<<9)
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#define MemAbs (1<<10) /* Memory operand is absolute displacement */
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#define String (1<<12) /* String instruction (rep capable) */
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#define Stack (1<<13) /* Stack instruction (push/pop) */
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#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
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#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
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#define GroupMask 0xff /* Group number stored in bits 0:7 */
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enum {
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Group1_80, Group1_81, Group1_82, Group1_83,
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Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
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};
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static u16 opcode_table[256] = {
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/* 0x00 - 0x07 */
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ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
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ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
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0, 0, 0, 0,
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/* 0x08 - 0x0F */
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ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
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ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
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0, 0, 0, 0,
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/* 0x10 - 0x17 */
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ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
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ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
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0, 0, 0, 0,
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/* 0x18 - 0x1F */
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ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
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ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
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0, 0, 0, 0,
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/* 0x20 - 0x27 */
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ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
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ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
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DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
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/* 0x28 - 0x2F */
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ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
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ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
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0, 0, 0, 0,
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/* 0x30 - 0x37 */
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ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
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ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
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0, 0, 0, 0,
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/* 0x38 - 0x3F */
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ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
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ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
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ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
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0, 0,
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/* 0x40 - 0x47 */
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DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
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/* 0x48 - 0x4F */
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DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
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/* 0x50 - 0x57 */
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SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
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SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
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/* 0x58 - 0x5F */
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DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
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DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
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/* 0x60 - 0x67 */
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0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
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0, 0, 0, 0,
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/* 0x68 - 0x6F */
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SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
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SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
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SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
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/* 0x70 - 0x77 */
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ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
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ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
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/* 0x78 - 0x7F */
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ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
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ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
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/* 0x80 - 0x87 */
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Group | Group1_80, Group | Group1_81,
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Group | Group1_82, Group | Group1_83,
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ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
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ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
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/* 0x88 - 0x8F */
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ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
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ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
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DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
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DstReg | SrcMem | ModRM | Mov, Group | Group1A,
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/* 0x90 - 0x97 */
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DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
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/* 0x98 - 0x9F */
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0, 0, 0, 0, ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
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/* 0xA0 - 0xA7 */
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ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
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ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
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ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
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ByteOp | ImplicitOps | String, ImplicitOps | String,
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/* 0xA8 - 0xAF */
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0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
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ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
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ByteOp | ImplicitOps | String, ImplicitOps | String,
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/* 0xB0 - 0xB7 */
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ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
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ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
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ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
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ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
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/* 0xB8 - 0xBF */
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DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
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DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
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DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
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DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
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/* 0xC0 - 0xC7 */
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ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
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0, ImplicitOps | Stack, 0, 0,
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ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
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/* 0xC8 - 0xCF */
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0, 0, 0, 0, 0, 0, 0, 0,
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/* 0xD0 - 0xD7 */
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ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
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ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
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0, 0, 0, 0,
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/* 0xD8 - 0xDF */
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0, 0, 0, 0, 0, 0, 0, 0,
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/* 0xE0 - 0xE7 */
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0, 0, 0, 0,
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SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
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SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
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/* 0xE8 - 0xEF */
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ImplicitOps | Stack, SrcImm | ImplicitOps,
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ImplicitOps, SrcImmByte | ImplicitOps,
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SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
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SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
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/* 0xF0 - 0xF7 */
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0, 0, 0, 0,
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ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
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/* 0xF8 - 0xFF */
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ImplicitOps, 0, ImplicitOps, ImplicitOps,
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ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
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};
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static u16 twobyte_table[256] = {
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/* 0x00 - 0x0F */
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0, Group | GroupDual | Group7, 0, 0, 0, 0, ImplicitOps, 0,
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ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
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/* 0x10 - 0x1F */
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0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
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/* 0x20 - 0x2F */
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ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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/* 0x30 - 0x3F */
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ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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/* 0x40 - 0x47 */
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DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
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DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
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DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
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DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
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/* 0x48 - 0x4F */
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DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
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DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
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DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
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DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
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/* 0x50 - 0x5F */
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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/* 0x60 - 0x6F */
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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/* 0x70 - 0x7F */
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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/* 0x80 - 0x8F */
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ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
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ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
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ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
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ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
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/* 0x90 - 0x9F */
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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/* 0xA0 - 0xA7 */
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0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
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/* 0xA8 - 0xAF */
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0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, ModRM, 0,
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/* 0xB0 - 0xB7 */
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ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
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DstMem | SrcReg | ModRM | BitOp,
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0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
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DstReg | SrcMem16 | ModRM | Mov,
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/* 0xB8 - 0xBF */
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0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
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0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
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DstReg | SrcMem16 | ModRM | Mov,
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/* 0xC0 - 0xCF */
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0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
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0, 0, 0, 0, 0, 0, 0, 0,
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/* 0xD0 - 0xDF */
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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/* 0xE0 - 0xEF */
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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/* 0xF0 - 0xFF */
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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};
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static u16 group_table[] = {
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[Group1_80*8] =
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ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
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ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
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ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
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ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
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[Group1_81*8] =
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DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
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DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
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DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
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DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
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[Group1_82*8] =
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ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
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ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
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ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
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ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
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[Group1_83*8] =
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DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
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DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
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DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
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DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
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[Group1A*8] =
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DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
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[Group3_Byte*8] =
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ByteOp | SrcImm | DstMem | ModRM, 0,
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ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
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0, 0, 0, 0,
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[Group3*8] =
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DstMem | SrcImm | ModRM, 0,
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DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
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0, 0, 0, 0,
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[Group4*8] =
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ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
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0, 0, 0, 0, 0, 0,
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[Group5*8] =
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DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
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SrcMem | ModRM | Stack, 0,
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SrcMem | ModRM | Stack, 0, SrcMem | ModRM | Stack, 0,
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[Group7*8] =
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0, 0, ModRM | SrcMem, ModRM | SrcMem,
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SrcNone | ModRM | DstMem | Mov, 0,
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SrcMem16 | ModRM | Mov, SrcMem | ModRM | ByteOp,
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};
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static u16 group2_table[] = {
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[Group7*8] =
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SrcNone | ModRM, 0, 0, 0,
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SrcNone | ModRM | DstMem | Mov, 0,
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SrcMem16 | ModRM | Mov, 0,
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};
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/* EFLAGS bit definitions. */
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#define EFLG_OF (1<<11)
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#define EFLG_DF (1<<10)
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#define EFLG_SF (1<<7)
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#define EFLG_ZF (1<<6)
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#define EFLG_AF (1<<4)
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#define EFLG_PF (1<<2)
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#define EFLG_CF (1<<0)
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/*
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* Instruction emulation:
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* Most instructions are emulated directly via a fragment of inline assembly
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* code. This allows us to save/restore EFLAGS and thus very easily pick up
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* any modified flags.
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*/
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#if defined(CONFIG_X86_64)
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#define _LO32 "k" /* force 32-bit operand */
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#define _STK "%%rsp" /* stack pointer */
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#elif defined(__i386__)
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#define _LO32 "" /* force 32-bit operand */
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#define _STK "%%esp" /* stack pointer */
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#endif
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/*
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* These EFLAGS bits are restored from saved value during emulation, and
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* any changes are written back to the saved value after emulation.
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*/
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#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
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/* Before executing instruction: restore necessary bits in EFLAGS. */
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#define _PRE_EFLAGS(_sav, _msk, _tmp) \
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/* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
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"movl %"_sav",%"_LO32 _tmp"; " \
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"push %"_tmp"; " \
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"push %"_tmp"; " \
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"movl %"_msk",%"_LO32 _tmp"; " \
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"andl %"_LO32 _tmp",("_STK"); " \
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"pushf; " \
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"notl %"_LO32 _tmp"; " \
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"andl %"_LO32 _tmp",("_STK"); " \
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"andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
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"pop %"_tmp"; " \
|
|
"orl %"_LO32 _tmp",("_STK"); " \
|
|
"popf; " \
|
|
"pop %"_sav"; "
|
|
|
|
/* After executing instruction: write-back necessary bits in EFLAGS. */
|
|
#define _POST_EFLAGS(_sav, _msk, _tmp) \
|
|
/* _sav |= EFLAGS & _msk; */ \
|
|
"pushf; " \
|
|
"pop %"_tmp"; " \
|
|
"andl %"_msk",%"_LO32 _tmp"; " \
|
|
"orl %"_LO32 _tmp",%"_sav"; "
|
|
|
|
/* Raw emulation: instruction has two explicit operands. */
|
|
#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
|
|
do { \
|
|
unsigned long _tmp; \
|
|
\
|
|
switch ((_dst).bytes) { \
|
|
case 2: \
|
|
__asm__ __volatile__ ( \
|
|
_PRE_EFLAGS("0", "4", "2") \
|
|
_op"w %"_wx"3,%1; " \
|
|
_POST_EFLAGS("0", "4", "2") \
|
|
: "=m" (_eflags), "=m" ((_dst).val), \
|
|
"=&r" (_tmp) \
|
|
: _wy ((_src).val), "i" (EFLAGS_MASK)); \
|
|
break; \
|
|
case 4: \
|
|
__asm__ __volatile__ ( \
|
|
_PRE_EFLAGS("0", "4", "2") \
|
|
_op"l %"_lx"3,%1; " \
|
|
_POST_EFLAGS("0", "4", "2") \
|
|
: "=m" (_eflags), "=m" ((_dst).val), \
|
|
"=&r" (_tmp) \
|
|
: _ly ((_src).val), "i" (EFLAGS_MASK)); \
|
|
break; \
|
|
case 8: \
|
|
__emulate_2op_8byte(_op, _src, _dst, \
|
|
_eflags, _qx, _qy); \
|
|
break; \
|
|
} \
|
|
} while (0)
|
|
|
|
#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
|
|
do { \
|
|
unsigned long __tmp; \
|
|
switch ((_dst).bytes) { \
|
|
case 1: \
|
|
__asm__ __volatile__ ( \
|
|
_PRE_EFLAGS("0", "4", "2") \
|
|
_op"b %"_bx"3,%1; " \
|
|
_POST_EFLAGS("0", "4", "2") \
|
|
: "=m" (_eflags), "=m" ((_dst).val), \
|
|
"=&r" (__tmp) \
|
|
: _by ((_src).val), "i" (EFLAGS_MASK)); \
|
|
break; \
|
|
default: \
|
|
__emulate_2op_nobyte(_op, _src, _dst, _eflags, \
|
|
_wx, _wy, _lx, _ly, _qx, _qy); \
|
|
break; \
|
|
} \
|
|
} while (0)
|
|
|
|
/* Source operand is byte-sized and may be restricted to just %cl. */
|
|
#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
|
|
__emulate_2op(_op, _src, _dst, _eflags, \
|
|
"b", "c", "b", "c", "b", "c", "b", "c")
|
|
|
|
/* Source operand is byte, word, long or quad sized. */
|
|
#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
|
|
__emulate_2op(_op, _src, _dst, _eflags, \
|
|
"b", "q", "w", "r", _LO32, "r", "", "r")
|
|
|
|
/* Source operand is word, long or quad sized. */
|
|
#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
|
|
__emulate_2op_nobyte(_op, _src, _dst, _eflags, \
|
|
"w", "r", _LO32, "r", "", "r")
|
|
|
|
/* Instruction has only one explicit operand (no source operand). */
|
|
#define emulate_1op(_op, _dst, _eflags) \
|
|
do { \
|
|
unsigned long _tmp; \
|
|
\
|
|
switch ((_dst).bytes) { \
|
|
case 1: \
|
|
__asm__ __volatile__ ( \
|
|
_PRE_EFLAGS("0", "3", "2") \
|
|
_op"b %1; " \
|
|
_POST_EFLAGS("0", "3", "2") \
|
|
: "=m" (_eflags), "=m" ((_dst).val), \
|
|
"=&r" (_tmp) \
|
|
: "i" (EFLAGS_MASK)); \
|
|
break; \
|
|
case 2: \
|
|
__asm__ __volatile__ ( \
|
|
_PRE_EFLAGS("0", "3", "2") \
|
|
_op"w %1; " \
|
|
_POST_EFLAGS("0", "3", "2") \
|
|
: "=m" (_eflags), "=m" ((_dst).val), \
|
|
"=&r" (_tmp) \
|
|
: "i" (EFLAGS_MASK)); \
|
|
break; \
|
|
case 4: \
|
|
__asm__ __volatile__ ( \
|
|
_PRE_EFLAGS("0", "3", "2") \
|
|
_op"l %1; " \
|
|
_POST_EFLAGS("0", "3", "2") \
|
|
: "=m" (_eflags), "=m" ((_dst).val), \
|
|
"=&r" (_tmp) \
|
|
: "i" (EFLAGS_MASK)); \
|
|
break; \
|
|
case 8: \
|
|
__emulate_1op_8byte(_op, _dst, _eflags); \
|
|
break; \
|
|
} \
|
|
} while (0)
|
|
|
|
/* Emulate an instruction with quadword operands (x86/64 only). */
|
|
#if defined(CONFIG_X86_64)
|
|
#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \
|
|
do { \
|
|
__asm__ __volatile__ ( \
|
|
_PRE_EFLAGS("0", "4", "2") \
|
|
_op"q %"_qx"3,%1; " \
|
|
_POST_EFLAGS("0", "4", "2") \
|
|
: "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
|
|
: _qy ((_src).val), "i" (EFLAGS_MASK)); \
|
|
} while (0)
|
|
|
|
#define __emulate_1op_8byte(_op, _dst, _eflags) \
|
|
do { \
|
|
__asm__ __volatile__ ( \
|
|
_PRE_EFLAGS("0", "3", "2") \
|
|
_op"q %1; " \
|
|
_POST_EFLAGS("0", "3", "2") \
|
|
: "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
|
|
: "i" (EFLAGS_MASK)); \
|
|
} while (0)
|
|
|
|
#elif defined(__i386__)
|
|
#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
|
|
#define __emulate_1op_8byte(_op, _dst, _eflags)
|
|
#endif /* __i386__ */
|
|
|
|
/* Fetch next part of the instruction being emulated. */
|
|
#define insn_fetch(_type, _size, _eip) \
|
|
({ unsigned long _x; \
|
|
rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
|
|
if (rc != 0) \
|
|
goto done; \
|
|
(_eip) += (_size); \
|
|
(_type)_x; \
|
|
})
|
|
|
|
static inline unsigned long ad_mask(struct decode_cache *c)
|
|
{
|
|
return (1UL << (c->ad_bytes << 3)) - 1;
|
|
}
|
|
|
|
/* Access/update address held in a register, based on addressing mode. */
|
|
static inline unsigned long
|
|
address_mask(struct decode_cache *c, unsigned long reg)
|
|
{
|
|
if (c->ad_bytes == sizeof(unsigned long))
|
|
return reg;
|
|
else
|
|
return reg & ad_mask(c);
|
|
}
|
|
|
|
static inline unsigned long
|
|
register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
|
|
{
|
|
return base + address_mask(c, reg);
|
|
}
|
|
|
|
static inline void
|
|
register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
|
|
{
|
|
if (c->ad_bytes == sizeof(unsigned long))
|
|
*reg += inc;
|
|
else
|
|
*reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
|
|
}
|
|
|
|
static inline void jmp_rel(struct decode_cache *c, int rel)
|
|
{
|
|
register_address_increment(c, &c->eip, rel);
|
|
}
|
|
|
|
static void set_seg_override(struct decode_cache *c, int seg)
|
|
{
|
|
c->has_seg_override = true;
|
|
c->seg_override = seg;
|
|
}
|
|
|
|
static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
|
|
{
|
|
if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
|
|
return 0;
|
|
|
|
return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
|
|
}
|
|
|
|
static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
|
|
struct decode_cache *c)
|
|
{
|
|
if (!c->has_seg_override)
|
|
return 0;
|
|
|
|
return seg_base(ctxt, c->seg_override);
|
|
}
|
|
|
|
static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
return seg_base(ctxt, VCPU_SREG_ES);
|
|
}
|
|
|
|
static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
return seg_base(ctxt, VCPU_SREG_SS);
|
|
}
|
|
|
|
static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
|
|
struct x86_emulate_ops *ops,
|
|
unsigned long linear, u8 *dest)
|
|
{
|
|
struct fetch_cache *fc = &ctxt->decode.fetch;
|
|
int rc;
|
|
int size;
|
|
|
|
if (linear < fc->start || linear >= fc->end) {
|
|
size = min(15UL, PAGE_SIZE - offset_in_page(linear));
|
|
rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
|
|
if (rc)
|
|
return rc;
|
|
fc->start = linear;
|
|
fc->end = linear + size;
|
|
}
|
|
*dest = fc->data[linear - fc->start];
|
|
return 0;
|
|
}
|
|
|
|
static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
|
|
struct x86_emulate_ops *ops,
|
|
unsigned long eip, void *dest, unsigned size)
|
|
{
|
|
int rc = 0;
|
|
|
|
eip += ctxt->cs_base;
|
|
while (size--) {
|
|
rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
|
|
if (rc)
|
|
return rc;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Given the 'reg' portion of a ModRM byte, and a register block, return a
|
|
* pointer into the block that addresses the relevant register.
|
|
* @highbyte_regs specifies whether to decode AH,CH,DH,BH.
|
|
*/
|
|
static void *decode_register(u8 modrm_reg, unsigned long *regs,
|
|
int highbyte_regs)
|
|
{
|
|
void *p;
|
|
|
|
p = ®s[modrm_reg];
|
|
if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
|
|
p = (unsigned char *)®s[modrm_reg & 3] + 1;
|
|
return p;
|
|
}
|
|
|
|
static int read_descriptor(struct x86_emulate_ctxt *ctxt,
|
|
struct x86_emulate_ops *ops,
|
|
void *ptr,
|
|
u16 *size, unsigned long *address, int op_bytes)
|
|
{
|
|
int rc;
|
|
|
|
if (op_bytes == 2)
|
|
op_bytes = 3;
|
|
*address = 0;
|
|
rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
|
|
ctxt->vcpu);
|
|
if (rc)
|
|
return rc;
|
|
rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
|
|
ctxt->vcpu);
|
|
return rc;
|
|
}
|
|
|
|
static int test_cc(unsigned int condition, unsigned int flags)
|
|
{
|
|
int rc = 0;
|
|
|
|
switch ((condition & 15) >> 1) {
|
|
case 0: /* o */
|
|
rc |= (flags & EFLG_OF);
|
|
break;
|
|
case 1: /* b/c/nae */
|
|
rc |= (flags & EFLG_CF);
|
|
break;
|
|
case 2: /* z/e */
|
|
rc |= (flags & EFLG_ZF);
|
|
break;
|
|
case 3: /* be/na */
|
|
rc |= (flags & (EFLG_CF|EFLG_ZF));
|
|
break;
|
|
case 4: /* s */
|
|
rc |= (flags & EFLG_SF);
|
|
break;
|
|
case 5: /* p/pe */
|
|
rc |= (flags & EFLG_PF);
|
|
break;
|
|
case 7: /* le/ng */
|
|
rc |= (flags & EFLG_ZF);
|
|
/* fall through */
|
|
case 6: /* l/nge */
|
|
rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
|
|
break;
|
|
}
|
|
|
|
/* Odd condition identifiers (lsb == 1) have inverted sense. */
|
|
return (!!rc ^ (condition & 1));
|
|
}
|
|
|
|
static void decode_register_operand(struct operand *op,
|
|
struct decode_cache *c,
|
|
int inhibit_bytereg)
|
|
{
|
|
unsigned reg = c->modrm_reg;
|
|
int highbyte_regs = c->rex_prefix == 0;
|
|
|
|
if (!(c->d & ModRM))
|
|
reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
|
|
op->type = OP_REG;
|
|
if ((c->d & ByteOp) && !inhibit_bytereg) {
|
|
op->ptr = decode_register(reg, c->regs, highbyte_regs);
|
|
op->val = *(u8 *)op->ptr;
|
|
op->bytes = 1;
|
|
} else {
|
|
op->ptr = decode_register(reg, c->regs, 0);
|
|
op->bytes = c->op_bytes;
|
|
switch (op->bytes) {
|
|
case 2:
|
|
op->val = *(u16 *)op->ptr;
|
|
break;
|
|
case 4:
|
|
op->val = *(u32 *)op->ptr;
|
|
break;
|
|
case 8:
|
|
op->val = *(u64 *) op->ptr;
|
|
break;
|
|
}
|
|
}
|
|
op->orig_val = op->val;
|
|
}
|
|
|
|
static int decode_modrm(struct x86_emulate_ctxt *ctxt,
|
|
struct x86_emulate_ops *ops)
|
|
{
|
|
struct decode_cache *c = &ctxt->decode;
|
|
u8 sib;
|
|
int index_reg = 0, base_reg = 0, scale;
|
|
int rc = 0;
|
|
|
|
if (c->rex_prefix) {
|
|
c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
|
|
index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
|
|
c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
|
|
}
|
|
|
|
c->modrm = insn_fetch(u8, 1, c->eip);
|
|
c->modrm_mod |= (c->modrm & 0xc0) >> 6;
|
|
c->modrm_reg |= (c->modrm & 0x38) >> 3;
|
|
c->modrm_rm |= (c->modrm & 0x07);
|
|
c->modrm_ea = 0;
|
|
c->use_modrm_ea = 1;
|
|
|
|
if (c->modrm_mod == 3) {
|
|
c->modrm_ptr = decode_register(c->modrm_rm,
|
|
c->regs, c->d & ByteOp);
|
|
c->modrm_val = *(unsigned long *)c->modrm_ptr;
|
|
return rc;
|
|
}
|
|
|
|
if (c->ad_bytes == 2) {
|
|
unsigned bx = c->regs[VCPU_REGS_RBX];
|
|
unsigned bp = c->regs[VCPU_REGS_RBP];
|
|
unsigned si = c->regs[VCPU_REGS_RSI];
|
|
unsigned di = c->regs[VCPU_REGS_RDI];
|
|
|
|
/* 16-bit ModR/M decode. */
|
|
switch (c->modrm_mod) {
|
|
case 0:
|
|
if (c->modrm_rm == 6)
|
|
c->modrm_ea += insn_fetch(u16, 2, c->eip);
|
|
break;
|
|
case 1:
|
|
c->modrm_ea += insn_fetch(s8, 1, c->eip);
|
|
break;
|
|
case 2:
|
|
c->modrm_ea += insn_fetch(u16, 2, c->eip);
|
|
break;
|
|
}
|
|
switch (c->modrm_rm) {
|
|
case 0:
|
|
c->modrm_ea += bx + si;
|
|
break;
|
|
case 1:
|
|
c->modrm_ea += bx + di;
|
|
break;
|
|
case 2:
|
|
c->modrm_ea += bp + si;
|
|
break;
|
|
case 3:
|
|
c->modrm_ea += bp + di;
|
|
break;
|
|
case 4:
|
|
c->modrm_ea += si;
|
|
break;
|
|
case 5:
|
|
c->modrm_ea += di;
|
|
break;
|
|
case 6:
|
|
if (c->modrm_mod != 0)
|
|
c->modrm_ea += bp;
|
|
break;
|
|
case 7:
|
|
c->modrm_ea += bx;
|
|
break;
|
|
}
|
|
if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
|
|
(c->modrm_rm == 6 && c->modrm_mod != 0))
|
|
if (!c->has_seg_override)
|
|
set_seg_override(c, VCPU_SREG_SS);
|
|
c->modrm_ea = (u16)c->modrm_ea;
|
|
} else {
|
|
/* 32/64-bit ModR/M decode. */
|
|
if ((c->modrm_rm & 7) == 4) {
|
|
sib = insn_fetch(u8, 1, c->eip);
|
|
index_reg |= (sib >> 3) & 7;
|
|
base_reg |= sib & 7;
|
|
scale = sib >> 6;
|
|
|
|
if ((base_reg & 7) == 5 && c->modrm_mod == 0)
|
|
c->modrm_ea += insn_fetch(s32, 4, c->eip);
|
|
else
|
|
c->modrm_ea += c->regs[base_reg];
|
|
if (index_reg != 4)
|
|
c->modrm_ea += c->regs[index_reg] << scale;
|
|
} else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
|
|
if (ctxt->mode == X86EMUL_MODE_PROT64)
|
|
c->rip_relative = 1;
|
|
} else
|
|
c->modrm_ea += c->regs[c->modrm_rm];
|
|
switch (c->modrm_mod) {
|
|
case 0:
|
|
if (c->modrm_rm == 5)
|
|
c->modrm_ea += insn_fetch(s32, 4, c->eip);
|
|
break;
|
|
case 1:
|
|
c->modrm_ea += insn_fetch(s8, 1, c->eip);
|
|
break;
|
|
case 2:
|
|
c->modrm_ea += insn_fetch(s32, 4, c->eip);
|
|
break;
|
|
}
|
|
}
|
|
done:
|
|
return rc;
|
|
}
|
|
|
|
static int decode_abs(struct x86_emulate_ctxt *ctxt,
|
|
struct x86_emulate_ops *ops)
|
|
{
|
|
struct decode_cache *c = &ctxt->decode;
|
|
int rc = 0;
|
|
|
|
switch (c->ad_bytes) {
|
|
case 2:
|
|
c->modrm_ea = insn_fetch(u16, 2, c->eip);
|
|
break;
|
|
case 4:
|
|
c->modrm_ea = insn_fetch(u32, 4, c->eip);
|
|
break;
|
|
case 8:
|
|
c->modrm_ea = insn_fetch(u64, 8, c->eip);
|
|
break;
|
|
}
|
|
done:
|
|
return rc;
|
|
}
|
|
|
|
int
|
|
x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
|
|
{
|
|
struct decode_cache *c = &ctxt->decode;
|
|
int rc = 0;
|
|
int mode = ctxt->mode;
|
|
int def_op_bytes, def_ad_bytes, group;
|
|
|
|
/* Shadow copy of register state. Committed on successful emulation. */
|
|
|
|
memset(c, 0, sizeof(struct decode_cache));
|
|
c->eip = kvm_rip_read(ctxt->vcpu);
|
|
ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
|
|
memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
|
|
|
|
switch (mode) {
|
|
case X86EMUL_MODE_REAL:
|
|
case X86EMUL_MODE_PROT16:
|
|
def_op_bytes = def_ad_bytes = 2;
|
|
break;
|
|
case X86EMUL_MODE_PROT32:
|
|
def_op_bytes = def_ad_bytes = 4;
|
|
break;
|
|
#ifdef CONFIG_X86_64
|
|
case X86EMUL_MODE_PROT64:
|
|
def_op_bytes = 4;
|
|
def_ad_bytes = 8;
|
|
break;
|
|
#endif
|
|
default:
|
|
return -1;
|
|
}
|
|
|
|
c->op_bytes = def_op_bytes;
|
|
c->ad_bytes = def_ad_bytes;
|
|
|
|
/* Legacy prefixes. */
|
|
for (;;) {
|
|
switch (c->b = insn_fetch(u8, 1, c->eip)) {
|
|
case 0x66: /* operand-size override */
|
|
/* switch between 2/4 bytes */
|
|
c->op_bytes = def_op_bytes ^ 6;
|
|
break;
|
|
case 0x67: /* address-size override */
|
|
if (mode == X86EMUL_MODE_PROT64)
|
|
/* switch between 4/8 bytes */
|
|
c->ad_bytes = def_ad_bytes ^ 12;
|
|
else
|
|
/* switch between 2/4 bytes */
|
|
c->ad_bytes = def_ad_bytes ^ 6;
|
|
break;
|
|
case 0x26: /* ES override */
|
|
case 0x2e: /* CS override */
|
|
case 0x36: /* SS override */
|
|
case 0x3e: /* DS override */
|
|
set_seg_override(c, (c->b >> 3) & 3);
|
|
break;
|
|
case 0x64: /* FS override */
|
|
case 0x65: /* GS override */
|
|
set_seg_override(c, c->b & 7);
|
|
break;
|
|
case 0x40 ... 0x4f: /* REX */
|
|
if (mode != X86EMUL_MODE_PROT64)
|
|
goto done_prefixes;
|
|
c->rex_prefix = c->b;
|
|
continue;
|
|
case 0xf0: /* LOCK */
|
|
c->lock_prefix = 1;
|
|
break;
|
|
case 0xf2: /* REPNE/REPNZ */
|
|
c->rep_prefix = REPNE_PREFIX;
|
|
break;
|
|
case 0xf3: /* REP/REPE/REPZ */
|
|
c->rep_prefix = REPE_PREFIX;
|
|
break;
|
|
default:
|
|
goto done_prefixes;
|
|
}
|
|
|
|
/* Any legacy prefix after a REX prefix nullifies its effect. */
|
|
|
|
c->rex_prefix = 0;
|
|
}
|
|
|
|
done_prefixes:
|
|
|
|
/* REX prefix. */
|
|
if (c->rex_prefix)
|
|
if (c->rex_prefix & 8)
|
|
c->op_bytes = 8; /* REX.W */
|
|
|
|
/* Opcode byte(s). */
|
|
c->d = opcode_table[c->b];
|
|
if (c->d == 0) {
|
|
/* Two-byte opcode? */
|
|
if (c->b == 0x0f) {
|
|
c->twobyte = 1;
|
|
c->b = insn_fetch(u8, 1, c->eip);
|
|
c->d = twobyte_table[c->b];
|
|
}
|
|
}
|
|
|
|
if (c->d & Group) {
|
|
group = c->d & GroupMask;
|
|
c->modrm = insn_fetch(u8, 1, c->eip);
|
|
--c->eip;
|
|
|
|
group = (group << 3) + ((c->modrm >> 3) & 7);
|
|
if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
|
|
c->d = group2_table[group];
|
|
else
|
|
c->d = group_table[group];
|
|
}
|
|
|
|
/* Unrecognised? */
|
|
if (c->d == 0) {
|
|
DPRINTF("Cannot emulate %02x\n", c->b);
|
|
return -1;
|
|
}
|
|
|
|
if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
|
|
c->op_bytes = 8;
|
|
|
|
/* ModRM and SIB bytes. */
|
|
if (c->d & ModRM)
|
|
rc = decode_modrm(ctxt, ops);
|
|
else if (c->d & MemAbs)
|
|
rc = decode_abs(ctxt, ops);
|
|
if (rc)
|
|
goto done;
|
|
|
|
if (!c->has_seg_override)
|
|
set_seg_override(c, VCPU_SREG_DS);
|
|
|
|
if (!(!c->twobyte && c->b == 0x8d))
|
|
c->modrm_ea += seg_override_base(ctxt, c);
|
|
|
|
if (c->ad_bytes != 8)
|
|
c->modrm_ea = (u32)c->modrm_ea;
|
|
/*
|
|
* Decode and fetch the source operand: register, memory
|
|
* or immediate.
|
|
*/
|
|
switch (c->d & SrcMask) {
|
|
case SrcNone:
|
|
break;
|
|
case SrcReg:
|
|
decode_register_operand(&c->src, c, 0);
|
|
break;
|
|
case SrcMem16:
|
|
c->src.bytes = 2;
|
|
goto srcmem_common;
|
|
case SrcMem32:
|
|
c->src.bytes = 4;
|
|
goto srcmem_common;
|
|
case SrcMem:
|
|
c->src.bytes = (c->d & ByteOp) ? 1 :
|
|
c->op_bytes;
|
|
/* Don't fetch the address for invlpg: it could be unmapped. */
|
|
if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
|
|
break;
|
|
srcmem_common:
|
|
/*
|
|
* For instructions with a ModR/M byte, switch to register
|
|
* access if Mod = 3.
|
|
*/
|
|
if ((c->d & ModRM) && c->modrm_mod == 3) {
|
|
c->src.type = OP_REG;
|
|
c->src.val = c->modrm_val;
|
|
c->src.ptr = c->modrm_ptr;
|
|
break;
|
|
}
|
|
c->src.type = OP_MEM;
|
|
break;
|
|
case SrcImm:
|
|
c->src.type = OP_IMM;
|
|
c->src.ptr = (unsigned long *)c->eip;
|
|
c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
|
|
if (c->src.bytes == 8)
|
|
c->src.bytes = 4;
|
|
/* NB. Immediates are sign-extended as necessary. */
|
|
switch (c->src.bytes) {
|
|
case 1:
|
|
c->src.val = insn_fetch(s8, 1, c->eip);
|
|
break;
|
|
case 2:
|
|
c->src.val = insn_fetch(s16, 2, c->eip);
|
|
break;
|
|
case 4:
|
|
c->src.val = insn_fetch(s32, 4, c->eip);
|
|
break;
|
|
}
|
|
break;
|
|
case SrcImmByte:
|
|
c->src.type = OP_IMM;
|
|
c->src.ptr = (unsigned long *)c->eip;
|
|
c->src.bytes = 1;
|
|
c->src.val = insn_fetch(s8, 1, c->eip);
|
|
break;
|
|
}
|
|
|
|
/* Decode and fetch the destination operand: register or memory. */
|
|
switch (c->d & DstMask) {
|
|
case ImplicitOps:
|
|
/* Special instructions do their own operand decoding. */
|
|
return 0;
|
|
case DstReg:
|
|
decode_register_operand(&c->dst, c,
|
|
c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
|
|
break;
|
|
case DstMem:
|
|
if ((c->d & ModRM) && c->modrm_mod == 3) {
|
|
c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
|
|
c->dst.type = OP_REG;
|
|
c->dst.val = c->dst.orig_val = c->modrm_val;
|
|
c->dst.ptr = c->modrm_ptr;
|
|
break;
|
|
}
|
|
c->dst.type = OP_MEM;
|
|
break;
|
|
case DstAcc:
|
|
c->dst.type = OP_REG;
|
|
c->dst.bytes = c->op_bytes;
|
|
c->dst.ptr = &c->regs[VCPU_REGS_RAX];
|
|
switch (c->op_bytes) {
|
|
case 1:
|
|
c->dst.val = *(u8 *)c->dst.ptr;
|
|
break;
|
|
case 2:
|
|
c->dst.val = *(u16 *)c->dst.ptr;
|
|
break;
|
|
case 4:
|
|
c->dst.val = *(u32 *)c->dst.ptr;
|
|
break;
|
|
}
|
|
c->dst.orig_val = c->dst.val;
|
|
break;
|
|
}
|
|
|
|
if (c->rip_relative)
|
|
c->modrm_ea += c->eip;
|
|
|
|
done:
|
|
return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
|
|
}
|
|
|
|
static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
struct decode_cache *c = &ctxt->decode;
|
|
|
|
c->dst.type = OP_MEM;
|
|
c->dst.bytes = c->op_bytes;
|
|
c->dst.val = c->src.val;
|
|
register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
|
|
c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
|
|
c->regs[VCPU_REGS_RSP]);
|
|
}
|
|
|
|
static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
|
|
struct x86_emulate_ops *ops)
|
|
{
|
|
struct decode_cache *c = &ctxt->decode;
|
|
int rc;
|
|
|
|
rc = ops->read_std(register_address(c, ss_base(ctxt),
|
|
c->regs[VCPU_REGS_RSP]),
|
|
&c->dst.val, c->dst.bytes, ctxt->vcpu);
|
|
if (rc != 0)
|
|
return rc;
|
|
|
|
register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->dst.bytes);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
|
|
{
|
|
struct decode_cache *c = &ctxt->decode;
|
|
switch (c->modrm_reg) {
|
|
case 0: /* rol */
|
|
emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
|
|
break;
|
|
case 1: /* ror */
|
|
emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
|
|
break;
|
|
case 2: /* rcl */
|
|
emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
|
|
break;
|
|
case 3: /* rcr */
|
|
emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
|
|
break;
|
|
case 4: /* sal/shl */
|
|
case 6: /* sal/shl */
|
|
emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
|
|
break;
|
|
case 5: /* shr */
|
|
emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
|
|
break;
|
|
case 7: /* sar */
|
|
emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
|
|
struct x86_emulate_ops *ops)
|
|
{
|
|
struct decode_cache *c = &ctxt->decode;
|
|
int rc = 0;
|
|
|
|
switch (c->modrm_reg) {
|
|
case 0 ... 1: /* test */
|
|
emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
|
|
break;
|
|
case 2: /* not */
|
|
c->dst.val = ~c->dst.val;
|
|
break;
|
|
case 3: /* neg */
|
|
emulate_1op("neg", c->dst, ctxt->eflags);
|
|
break;
|
|
default:
|
|
DPRINTF("Cannot emulate %02x\n", c->b);
|
|
rc = X86EMUL_UNHANDLEABLE;
|
|
break;
|
|
}
|
|
return rc;
|
|
}
|
|
|
|
static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
|
|
struct x86_emulate_ops *ops)
|
|
{
|
|
struct decode_cache *c = &ctxt->decode;
|
|
|
|
switch (c->modrm_reg) {
|
|
case 0: /* inc */
|
|
emulate_1op("inc", c->dst, ctxt->eflags);
|
|
break;
|
|
case 1: /* dec */
|
|
emulate_1op("dec", c->dst, ctxt->eflags);
|
|
break;
|
|
case 2: /* call near abs */ {
|
|
long int old_eip;
|
|
old_eip = c->eip;
|
|
c->eip = c->src.val;
|
|
c->src.val = old_eip;
|
|
emulate_push(ctxt);
|
|
break;
|
|
}
|
|
case 4: /* jmp abs */
|
|
c->eip = c->src.val;
|
|
break;
|
|
case 6: /* push */
|
|
emulate_push(ctxt);
|
|
break;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
|
|
struct x86_emulate_ops *ops,
|
|
unsigned long memop)
|
|
{
|
|
struct decode_cache *c = &ctxt->decode;
|
|
u64 old, new;
|
|
int rc;
|
|
|
|
rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
|
|
if (rc != 0)
|
|
return rc;
|
|
|
|
if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
|
|
((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
|
|
|
|
c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
|
|
c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
|
|
ctxt->eflags &= ~EFLG_ZF;
|
|
|
|
} else {
|
|
new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
|
|
(u32) c->regs[VCPU_REGS_RBX];
|
|
|
|
rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
|
|
if (rc != 0)
|
|
return rc;
|
|
ctxt->eflags |= EFLG_ZF;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static inline int writeback(struct x86_emulate_ctxt *ctxt,
|
|
struct x86_emulate_ops *ops)
|
|
{
|
|
int rc;
|
|
struct decode_cache *c = &ctxt->decode;
|
|
|
|
switch (c->dst.type) {
|
|
case OP_REG:
|
|
/* The 4-byte case *is* correct:
|
|
* in 64-bit mode we zero-extend.
|
|
*/
|
|
switch (c->dst.bytes) {
|
|
case 1:
|
|
*(u8 *)c->dst.ptr = (u8)c->dst.val;
|
|
break;
|
|
case 2:
|
|
*(u16 *)c->dst.ptr = (u16)c->dst.val;
|
|
break;
|
|
case 4:
|
|
*c->dst.ptr = (u32)c->dst.val;
|
|
break; /* 64b: zero-ext */
|
|
case 8:
|
|
*c->dst.ptr = c->dst.val;
|
|
break;
|
|
}
|
|
break;
|
|
case OP_MEM:
|
|
if (c->lock_prefix)
|
|
rc = ops->cmpxchg_emulated(
|
|
(unsigned long)c->dst.ptr,
|
|
&c->dst.orig_val,
|
|
&c->dst.val,
|
|
c->dst.bytes,
|
|
ctxt->vcpu);
|
|
else
|
|
rc = ops->write_emulated(
|
|
(unsigned long)c->dst.ptr,
|
|
&c->dst.val,
|
|
c->dst.bytes,
|
|
ctxt->vcpu);
|
|
if (rc != 0)
|
|
return rc;
|
|
break;
|
|
case OP_NONE:
|
|
/* no writeback */
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
|
|
{
|
|
unsigned long memop = 0;
|
|
u64 msr_data;
|
|
unsigned long saved_eip = 0;
|
|
struct decode_cache *c = &ctxt->decode;
|
|
unsigned int port;
|
|
int io_dir_in;
|
|
int rc = 0;
|
|
|
|
/* Shadow copy of register state. Committed on successful emulation.
|
|
* NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
|
|
* modify them.
|
|
*/
|
|
|
|
memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
|
|
saved_eip = c->eip;
|
|
|
|
if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
|
|
memop = c->modrm_ea;
|
|
|
|
if (c->rep_prefix && (c->d & String)) {
|
|
/* All REP prefixes have the same first termination condition */
|
|
if (c->regs[VCPU_REGS_RCX] == 0) {
|
|
kvm_rip_write(ctxt->vcpu, c->eip);
|
|
goto done;
|
|
}
|
|
/* The second termination condition only applies for REPE
|
|
* and REPNE. Test if the repeat string operation prefix is
|
|
* REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
|
|
* corresponding termination condition according to:
|
|
* - if REPE/REPZ and ZF = 0 then done
|
|
* - if REPNE/REPNZ and ZF = 1 then done
|
|
*/
|
|
if ((c->b == 0xa6) || (c->b == 0xa7) ||
|
|
(c->b == 0xae) || (c->b == 0xaf)) {
|
|
if ((c->rep_prefix == REPE_PREFIX) &&
|
|
((ctxt->eflags & EFLG_ZF) == 0)) {
|
|
kvm_rip_write(ctxt->vcpu, c->eip);
|
|
goto done;
|
|
}
|
|
if ((c->rep_prefix == REPNE_PREFIX) &&
|
|
((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
|
|
kvm_rip_write(ctxt->vcpu, c->eip);
|
|
goto done;
|
|
}
|
|
}
|
|
c->regs[VCPU_REGS_RCX]--;
|
|
c->eip = kvm_rip_read(ctxt->vcpu);
|
|
}
|
|
|
|
if (c->src.type == OP_MEM) {
|
|
c->src.ptr = (unsigned long *)memop;
|
|
c->src.val = 0;
|
|
rc = ops->read_emulated((unsigned long)c->src.ptr,
|
|
&c->src.val,
|
|
c->src.bytes,
|
|
ctxt->vcpu);
|
|
if (rc != 0)
|
|
goto done;
|
|
c->src.orig_val = c->src.val;
|
|
}
|
|
|
|
if ((c->d & DstMask) == ImplicitOps)
|
|
goto special_insn;
|
|
|
|
|
|
if (c->dst.type == OP_MEM) {
|
|
c->dst.ptr = (unsigned long *)memop;
|
|
c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
|
|
c->dst.val = 0;
|
|
if (c->d & BitOp) {
|
|
unsigned long mask = ~(c->dst.bytes * 8 - 1);
|
|
|
|
c->dst.ptr = (void *)c->dst.ptr +
|
|
(c->src.val & mask) / 8;
|
|
}
|
|
if (!(c->d & Mov) &&
|
|
/* optimisation - avoid slow emulated read */
|
|
((rc = ops->read_emulated((unsigned long)c->dst.ptr,
|
|
&c->dst.val,
|
|
c->dst.bytes, ctxt->vcpu)) != 0))
|
|
goto done;
|
|
}
|
|
c->dst.orig_val = c->dst.val;
|
|
|
|
special_insn:
|
|
|
|
if (c->twobyte)
|
|
goto twobyte_insn;
|
|
|
|
switch (c->b) {
|
|
case 0x00 ... 0x05:
|
|
add: /* add */
|
|
emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
|
|
break;
|
|
case 0x08 ... 0x0d:
|
|
or: /* or */
|
|
emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
|
|
break;
|
|
case 0x10 ... 0x15:
|
|
adc: /* adc */
|
|
emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
|
|
break;
|
|
case 0x18 ... 0x1d:
|
|
sbb: /* sbb */
|
|
emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
|
|
break;
|
|
case 0x20 ... 0x25:
|
|
and: /* and */
|
|
emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
|
|
break;
|
|
case 0x28 ... 0x2d:
|
|
sub: /* sub */
|
|
emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
|
|
break;
|
|
case 0x30 ... 0x35:
|
|
xor: /* xor */
|
|
emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
|
|
break;
|
|
case 0x38 ... 0x3d:
|
|
cmp: /* cmp */
|
|
emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
|
|
break;
|
|
case 0x40 ... 0x47: /* inc r16/r32 */
|
|
emulate_1op("inc", c->dst, ctxt->eflags);
|
|
break;
|
|
case 0x48 ... 0x4f: /* dec r16/r32 */
|
|
emulate_1op("dec", c->dst, ctxt->eflags);
|
|
break;
|
|
case 0x50 ... 0x57: /* push reg */
|
|
c->dst.type = OP_MEM;
|
|
c->dst.bytes = c->op_bytes;
|
|
c->dst.val = c->src.val;
|
|
register_address_increment(c, &c->regs[VCPU_REGS_RSP],
|
|
-c->op_bytes);
|
|
c->dst.ptr = (void *) register_address(
|
|
c, ss_base(ctxt), c->regs[VCPU_REGS_RSP]);
|
|
break;
|
|
case 0x58 ... 0x5f: /* pop reg */
|
|
pop_instruction:
|
|
if ((rc = ops->read_std(register_address(c, ss_base(ctxt),
|
|
c->regs[VCPU_REGS_RSP]), c->dst.ptr,
|
|
c->op_bytes, ctxt->vcpu)) != 0)
|
|
goto done;
|
|
|
|
register_address_increment(c, &c->regs[VCPU_REGS_RSP],
|
|
c->op_bytes);
|
|
c->dst.type = OP_NONE; /* Disable writeback. */
|
|
break;
|
|
case 0x63: /* movsxd */
|
|
if (ctxt->mode != X86EMUL_MODE_PROT64)
|
|
goto cannot_emulate;
|
|
c->dst.val = (s32) c->src.val;
|
|
break;
|
|
case 0x68: /* push imm */
|
|
case 0x6a: /* push imm8 */
|
|
emulate_push(ctxt);
|
|
break;
|
|
case 0x6c: /* insb */
|
|
case 0x6d: /* insw/insd */
|
|
if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
|
|
1,
|
|
(c->d & ByteOp) ? 1 : c->op_bytes,
|
|
c->rep_prefix ?
|
|
address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
|
|
(ctxt->eflags & EFLG_DF),
|
|
register_address(c, es_base(ctxt),
|
|
c->regs[VCPU_REGS_RDI]),
|
|
c->rep_prefix,
|
|
c->regs[VCPU_REGS_RDX]) == 0) {
|
|
c->eip = saved_eip;
|
|
return -1;
|
|
}
|
|
return 0;
|
|
case 0x6e: /* outsb */
|
|
case 0x6f: /* outsw/outsd */
|
|
if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
|
|
0,
|
|
(c->d & ByteOp) ? 1 : c->op_bytes,
|
|
c->rep_prefix ?
|
|
address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
|
|
(ctxt->eflags & EFLG_DF),
|
|
register_address(c,
|
|
seg_override_base(ctxt, c),
|
|
c->regs[VCPU_REGS_RSI]),
|
|
c->rep_prefix,
|
|
c->regs[VCPU_REGS_RDX]) == 0) {
|
|
c->eip = saved_eip;
|
|
return -1;
|
|
}
|
|
return 0;
|
|
case 0x70 ... 0x7f: /* jcc (short) */ {
|
|
int rel = insn_fetch(s8, 1, c->eip);
|
|
|
|
if (test_cc(c->b, ctxt->eflags))
|
|
jmp_rel(c, rel);
|
|
break;
|
|
}
|
|
case 0x80 ... 0x83: /* Grp1 */
|
|
switch (c->modrm_reg) {
|
|
case 0:
|
|
goto add;
|
|
case 1:
|
|
goto or;
|
|
case 2:
|
|
goto adc;
|
|
case 3:
|
|
goto sbb;
|
|
case 4:
|
|
goto and;
|
|
case 5:
|
|
goto sub;
|
|
case 6:
|
|
goto xor;
|
|
case 7:
|
|
goto cmp;
|
|
}
|
|
break;
|
|
case 0x84 ... 0x85:
|
|
emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
|
|
break;
|
|
case 0x86 ... 0x87: /* xchg */
|
|
xchg:
|
|
/* Write back the register source. */
|
|
switch (c->dst.bytes) {
|
|
case 1:
|
|
*(u8 *) c->src.ptr = (u8) c->dst.val;
|
|
break;
|
|
case 2:
|
|
*(u16 *) c->src.ptr = (u16) c->dst.val;
|
|
break;
|
|
case 4:
|
|
*c->src.ptr = (u32) c->dst.val;
|
|
break; /* 64b reg: zero-extend */
|
|
case 8:
|
|
*c->src.ptr = c->dst.val;
|
|
break;
|
|
}
|
|
/*
|
|
* Write back the memory destination with implicit LOCK
|
|
* prefix.
|
|
*/
|
|
c->dst.val = c->src.val;
|
|
c->lock_prefix = 1;
|
|
break;
|
|
case 0x88 ... 0x8b: /* mov */
|
|
goto mov;
|
|
case 0x8c: { /* mov r/m, sreg */
|
|
struct kvm_segment segreg;
|
|
|
|
if (c->modrm_reg <= 5)
|
|
kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
|
|
else {
|
|
printk(KERN_INFO "0x8c: Invalid segreg in modrm byte 0x%02x\n",
|
|
c->modrm);
|
|
goto cannot_emulate;
|
|
}
|
|
c->dst.val = segreg.selector;
|
|
break;
|
|
}
|
|
case 0x8d: /* lea r16/r32, m */
|
|
c->dst.val = c->modrm_ea;
|
|
break;
|
|
case 0x8e: { /* mov seg, r/m16 */
|
|
uint16_t sel;
|
|
int type_bits;
|
|
int err;
|
|
|
|
sel = c->src.val;
|
|
if (c->modrm_reg <= 5) {
|
|
type_bits = (c->modrm_reg == 1) ? 9 : 1;
|
|
err = kvm_load_segment_descriptor(ctxt->vcpu, sel,
|
|
type_bits, c->modrm_reg);
|
|
} else {
|
|
printk(KERN_INFO "Invalid segreg in modrm byte 0x%02x\n",
|
|
c->modrm);
|
|
goto cannot_emulate;
|
|
}
|
|
|
|
if (err < 0)
|
|
goto cannot_emulate;
|
|
|
|
c->dst.type = OP_NONE; /* Disable writeback. */
|
|
break;
|
|
}
|
|
case 0x8f: /* pop (sole member of Grp1a) */
|
|
rc = emulate_grp1a(ctxt, ops);
|
|
if (rc != 0)
|
|
goto done;
|
|
break;
|
|
case 0x90: /* nop / xchg r8,rax */
|
|
if (!(c->rex_prefix & 1)) { /* nop */
|
|
c->dst.type = OP_NONE;
|
|
break;
|
|
}
|
|
case 0x91 ... 0x97: /* xchg reg,rax */
|
|
c->src.type = c->dst.type = OP_REG;
|
|
c->src.bytes = c->dst.bytes = c->op_bytes;
|
|
c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
|
|
c->src.val = *(c->src.ptr);
|
|
goto xchg;
|
|
case 0x9c: /* pushf */
|
|
c->src.val = (unsigned long) ctxt->eflags;
|
|
emulate_push(ctxt);
|
|
break;
|
|
case 0x9d: /* popf */
|
|
c->dst.ptr = (unsigned long *) &ctxt->eflags;
|
|
goto pop_instruction;
|
|
case 0xa0 ... 0xa1: /* mov */
|
|
c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
|
|
c->dst.val = c->src.val;
|
|
break;
|
|
case 0xa2 ... 0xa3: /* mov */
|
|
c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
|
|
break;
|
|
case 0xa4 ... 0xa5: /* movs */
|
|
c->dst.type = OP_MEM;
|
|
c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
|
|
c->dst.ptr = (unsigned long *)register_address(c,
|
|
es_base(ctxt),
|
|
c->regs[VCPU_REGS_RDI]);
|
|
if ((rc = ops->read_emulated(register_address(c,
|
|
seg_override_base(ctxt, c),
|
|
c->regs[VCPU_REGS_RSI]),
|
|
&c->dst.val,
|
|
c->dst.bytes, ctxt->vcpu)) != 0)
|
|
goto done;
|
|
register_address_increment(c, &c->regs[VCPU_REGS_RSI],
|
|
(ctxt->eflags & EFLG_DF) ? -c->dst.bytes
|
|
: c->dst.bytes);
|
|
register_address_increment(c, &c->regs[VCPU_REGS_RDI],
|
|
(ctxt->eflags & EFLG_DF) ? -c->dst.bytes
|
|
: c->dst.bytes);
|
|
break;
|
|
case 0xa6 ... 0xa7: /* cmps */
|
|
c->src.type = OP_NONE; /* Disable writeback. */
|
|
c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
|
|
c->src.ptr = (unsigned long *)register_address(c,
|
|
seg_override_base(ctxt, c),
|
|
c->regs[VCPU_REGS_RSI]);
|
|
if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
|
|
&c->src.val,
|
|
c->src.bytes,
|
|
ctxt->vcpu)) != 0)
|
|
goto done;
|
|
|
|
c->dst.type = OP_NONE; /* Disable writeback. */
|
|
c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
|
|
c->dst.ptr = (unsigned long *)register_address(c,
|
|
es_base(ctxt),
|
|
c->regs[VCPU_REGS_RDI]);
|
|
if ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
|
|
&c->dst.val,
|
|
c->dst.bytes,
|
|
ctxt->vcpu)) != 0)
|
|
goto done;
|
|
|
|
DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
|
|
|
|
emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
|
|
|
|
register_address_increment(c, &c->regs[VCPU_REGS_RSI],
|
|
(ctxt->eflags & EFLG_DF) ? -c->src.bytes
|
|
: c->src.bytes);
|
|
register_address_increment(c, &c->regs[VCPU_REGS_RDI],
|
|
(ctxt->eflags & EFLG_DF) ? -c->dst.bytes
|
|
: c->dst.bytes);
|
|
|
|
break;
|
|
case 0xaa ... 0xab: /* stos */
|
|
c->dst.type = OP_MEM;
|
|
c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
|
|
c->dst.ptr = (unsigned long *)register_address(c,
|
|
es_base(ctxt),
|
|
c->regs[VCPU_REGS_RDI]);
|
|
c->dst.val = c->regs[VCPU_REGS_RAX];
|
|
register_address_increment(c, &c->regs[VCPU_REGS_RDI],
|
|
(ctxt->eflags & EFLG_DF) ? -c->dst.bytes
|
|
: c->dst.bytes);
|
|
break;
|
|
case 0xac ... 0xad: /* lods */
|
|
c->dst.type = OP_REG;
|
|
c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
|
|
c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
|
|
if ((rc = ops->read_emulated(register_address(c,
|
|
seg_override_base(ctxt, c),
|
|
c->regs[VCPU_REGS_RSI]),
|
|
&c->dst.val,
|
|
c->dst.bytes,
|
|
ctxt->vcpu)) != 0)
|
|
goto done;
|
|
register_address_increment(c, &c->regs[VCPU_REGS_RSI],
|
|
(ctxt->eflags & EFLG_DF) ? -c->dst.bytes
|
|
: c->dst.bytes);
|
|
break;
|
|
case 0xae ... 0xaf: /* scas */
|
|
DPRINTF("Urk! I don't handle SCAS.\n");
|
|
goto cannot_emulate;
|
|
case 0xb0 ... 0xbf: /* mov r, imm */
|
|
goto mov;
|
|
case 0xc0 ... 0xc1:
|
|
emulate_grp2(ctxt);
|
|
break;
|
|
case 0xc3: /* ret */
|
|
c->dst.ptr = &c->eip;
|
|
goto pop_instruction;
|
|
case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
|
|
mov:
|
|
c->dst.val = c->src.val;
|
|
break;
|
|
case 0xd0 ... 0xd1: /* Grp2 */
|
|
c->src.val = 1;
|
|
emulate_grp2(ctxt);
|
|
break;
|
|
case 0xd2 ... 0xd3: /* Grp2 */
|
|
c->src.val = c->regs[VCPU_REGS_RCX];
|
|
emulate_grp2(ctxt);
|
|
break;
|
|
case 0xe4: /* inb */
|
|
case 0xe5: /* in */
|
|
port = insn_fetch(u8, 1, c->eip);
|
|
io_dir_in = 1;
|
|
goto do_io;
|
|
case 0xe6: /* outb */
|
|
case 0xe7: /* out */
|
|
port = insn_fetch(u8, 1, c->eip);
|
|
io_dir_in = 0;
|
|
goto do_io;
|
|
case 0xe8: /* call (near) */ {
|
|
long int rel;
|
|
switch (c->op_bytes) {
|
|
case 2:
|
|
rel = insn_fetch(s16, 2, c->eip);
|
|
break;
|
|
case 4:
|
|
rel = insn_fetch(s32, 4, c->eip);
|
|
break;
|
|
default:
|
|
DPRINTF("Call: Invalid op_bytes\n");
|
|
goto cannot_emulate;
|
|
}
|
|
c->src.val = (unsigned long) c->eip;
|
|
jmp_rel(c, rel);
|
|
c->op_bytes = c->ad_bytes;
|
|
emulate_push(ctxt);
|
|
break;
|
|
}
|
|
case 0xe9: /* jmp rel */
|
|
goto jmp;
|
|
case 0xea: /* jmp far */ {
|
|
uint32_t eip;
|
|
uint16_t sel;
|
|
|
|
switch (c->op_bytes) {
|
|
case 2:
|
|
eip = insn_fetch(u16, 2, c->eip);
|
|
break;
|
|
case 4:
|
|
eip = insn_fetch(u32, 4, c->eip);
|
|
break;
|
|
default:
|
|
DPRINTF("jmp far: Invalid op_bytes\n");
|
|
goto cannot_emulate;
|
|
}
|
|
sel = insn_fetch(u16, 2, c->eip);
|
|
if (kvm_load_segment_descriptor(ctxt->vcpu, sel, 9, VCPU_SREG_CS) < 0) {
|
|
DPRINTF("jmp far: Failed to load CS descriptor\n");
|
|
goto cannot_emulate;
|
|
}
|
|
|
|
c->eip = eip;
|
|
break;
|
|
}
|
|
case 0xeb:
|
|
jmp: /* jmp rel short */
|
|
jmp_rel(c, c->src.val);
|
|
c->dst.type = OP_NONE; /* Disable writeback. */
|
|
break;
|
|
case 0xec: /* in al,dx */
|
|
case 0xed: /* in (e/r)ax,dx */
|
|
port = c->regs[VCPU_REGS_RDX];
|
|
io_dir_in = 1;
|
|
goto do_io;
|
|
case 0xee: /* out al,dx */
|
|
case 0xef: /* out (e/r)ax,dx */
|
|
port = c->regs[VCPU_REGS_RDX];
|
|
io_dir_in = 0;
|
|
do_io: if (kvm_emulate_pio(ctxt->vcpu, NULL, io_dir_in,
|
|
(c->d & ByteOp) ? 1 : c->op_bytes,
|
|
port) != 0) {
|
|
c->eip = saved_eip;
|
|
goto cannot_emulate;
|
|
}
|
|
return 0;
|
|
case 0xf4: /* hlt */
|
|
ctxt->vcpu->arch.halt_request = 1;
|
|
break;
|
|
case 0xf5: /* cmc */
|
|
/* complement carry flag from eflags reg */
|
|
ctxt->eflags ^= EFLG_CF;
|
|
c->dst.type = OP_NONE; /* Disable writeback. */
|
|
break;
|
|
case 0xf6 ... 0xf7: /* Grp3 */
|
|
rc = emulate_grp3(ctxt, ops);
|
|
if (rc != 0)
|
|
goto done;
|
|
break;
|
|
case 0xf8: /* clc */
|
|
ctxt->eflags &= ~EFLG_CF;
|
|
c->dst.type = OP_NONE; /* Disable writeback. */
|
|
break;
|
|
case 0xfa: /* cli */
|
|
ctxt->eflags &= ~X86_EFLAGS_IF;
|
|
c->dst.type = OP_NONE; /* Disable writeback. */
|
|
break;
|
|
case 0xfb: /* sti */
|
|
ctxt->eflags |= X86_EFLAGS_IF;
|
|
c->dst.type = OP_NONE; /* Disable writeback. */
|
|
break;
|
|
case 0xfc: /* cld */
|
|
ctxt->eflags &= ~EFLG_DF;
|
|
c->dst.type = OP_NONE; /* Disable writeback. */
|
|
break;
|
|
case 0xfd: /* std */
|
|
ctxt->eflags |= EFLG_DF;
|
|
c->dst.type = OP_NONE; /* Disable writeback. */
|
|
break;
|
|
case 0xfe ... 0xff: /* Grp4/Grp5 */
|
|
rc = emulate_grp45(ctxt, ops);
|
|
if (rc != 0)
|
|
goto done;
|
|
break;
|
|
}
|
|
|
|
writeback:
|
|
rc = writeback(ctxt, ops);
|
|
if (rc != 0)
|
|
goto done;
|
|
|
|
/* Commit shadow register state. */
|
|
memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
|
|
kvm_rip_write(ctxt->vcpu, c->eip);
|
|
|
|
done:
|
|
if (rc == X86EMUL_UNHANDLEABLE) {
|
|
c->eip = saved_eip;
|
|
return -1;
|
|
}
|
|
return 0;
|
|
|
|
twobyte_insn:
|
|
switch (c->b) {
|
|
case 0x01: /* lgdt, lidt, lmsw */
|
|
switch (c->modrm_reg) {
|
|
u16 size;
|
|
unsigned long address;
|
|
|
|
case 0: /* vmcall */
|
|
if (c->modrm_mod != 3 || c->modrm_rm != 1)
|
|
goto cannot_emulate;
|
|
|
|
rc = kvm_fix_hypercall(ctxt->vcpu);
|
|
if (rc)
|
|
goto done;
|
|
|
|
/* Let the processor re-execute the fixed hypercall */
|
|
c->eip = kvm_rip_read(ctxt->vcpu);
|
|
/* Disable writeback. */
|
|
c->dst.type = OP_NONE;
|
|
break;
|
|
case 2: /* lgdt */
|
|
rc = read_descriptor(ctxt, ops, c->src.ptr,
|
|
&size, &address, c->op_bytes);
|
|
if (rc)
|
|
goto done;
|
|
realmode_lgdt(ctxt->vcpu, size, address);
|
|
/* Disable writeback. */
|
|
c->dst.type = OP_NONE;
|
|
break;
|
|
case 3: /* lidt/vmmcall */
|
|
if (c->modrm_mod == 3 && c->modrm_rm == 1) {
|
|
rc = kvm_fix_hypercall(ctxt->vcpu);
|
|
if (rc)
|
|
goto done;
|
|
kvm_emulate_hypercall(ctxt->vcpu);
|
|
} else {
|
|
rc = read_descriptor(ctxt, ops, c->src.ptr,
|
|
&size, &address,
|
|
c->op_bytes);
|
|
if (rc)
|
|
goto done;
|
|
realmode_lidt(ctxt->vcpu, size, address);
|
|
}
|
|
/* Disable writeback. */
|
|
c->dst.type = OP_NONE;
|
|
break;
|
|
case 4: /* smsw */
|
|
c->dst.bytes = 2;
|
|
c->dst.val = realmode_get_cr(ctxt->vcpu, 0);
|
|
break;
|
|
case 6: /* lmsw */
|
|
realmode_lmsw(ctxt->vcpu, (u16)c->src.val,
|
|
&ctxt->eflags);
|
|
c->dst.type = OP_NONE;
|
|
break;
|
|
case 7: /* invlpg*/
|
|
emulate_invlpg(ctxt->vcpu, memop);
|
|
/* Disable writeback. */
|
|
c->dst.type = OP_NONE;
|
|
break;
|
|
default:
|
|
goto cannot_emulate;
|
|
}
|
|
break;
|
|
case 0x06:
|
|
emulate_clts(ctxt->vcpu);
|
|
c->dst.type = OP_NONE;
|
|
break;
|
|
case 0x08: /* invd */
|
|
case 0x09: /* wbinvd */
|
|
case 0x0d: /* GrpP (prefetch) */
|
|
case 0x18: /* Grp16 (prefetch/nop) */
|
|
c->dst.type = OP_NONE;
|
|
break;
|
|
case 0x20: /* mov cr, reg */
|
|
if (c->modrm_mod != 3)
|
|
goto cannot_emulate;
|
|
c->regs[c->modrm_rm] =
|
|
realmode_get_cr(ctxt->vcpu, c->modrm_reg);
|
|
c->dst.type = OP_NONE; /* no writeback */
|
|
break;
|
|
case 0x21: /* mov from dr to reg */
|
|
if (c->modrm_mod != 3)
|
|
goto cannot_emulate;
|
|
rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
|
|
if (rc)
|
|
goto cannot_emulate;
|
|
c->dst.type = OP_NONE; /* no writeback */
|
|
break;
|
|
case 0x22: /* mov reg, cr */
|
|
if (c->modrm_mod != 3)
|
|
goto cannot_emulate;
|
|
realmode_set_cr(ctxt->vcpu,
|
|
c->modrm_reg, c->modrm_val, &ctxt->eflags);
|
|
c->dst.type = OP_NONE;
|
|
break;
|
|
case 0x23: /* mov from reg to dr */
|
|
if (c->modrm_mod != 3)
|
|
goto cannot_emulate;
|
|
rc = emulator_set_dr(ctxt, c->modrm_reg,
|
|
c->regs[c->modrm_rm]);
|
|
if (rc)
|
|
goto cannot_emulate;
|
|
c->dst.type = OP_NONE; /* no writeback */
|
|
break;
|
|
case 0x30:
|
|
/* wrmsr */
|
|
msr_data = (u32)c->regs[VCPU_REGS_RAX]
|
|
| ((u64)c->regs[VCPU_REGS_RDX] << 32);
|
|
rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
|
|
if (rc) {
|
|
kvm_inject_gp(ctxt->vcpu, 0);
|
|
c->eip = kvm_rip_read(ctxt->vcpu);
|
|
}
|
|
rc = X86EMUL_CONTINUE;
|
|
c->dst.type = OP_NONE;
|
|
break;
|
|
case 0x32:
|
|
/* rdmsr */
|
|
rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
|
|
if (rc) {
|
|
kvm_inject_gp(ctxt->vcpu, 0);
|
|
c->eip = kvm_rip_read(ctxt->vcpu);
|
|
} else {
|
|
c->regs[VCPU_REGS_RAX] = (u32)msr_data;
|
|
c->regs[VCPU_REGS_RDX] = msr_data >> 32;
|
|
}
|
|
rc = X86EMUL_CONTINUE;
|
|
c->dst.type = OP_NONE;
|
|
break;
|
|
case 0x40 ... 0x4f: /* cmov */
|
|
c->dst.val = c->dst.orig_val = c->src.val;
|
|
if (!test_cc(c->b, ctxt->eflags))
|
|
c->dst.type = OP_NONE; /* no writeback */
|
|
break;
|
|
case 0x80 ... 0x8f: /* jnz rel, etc*/ {
|
|
long int rel;
|
|
|
|
switch (c->op_bytes) {
|
|
case 2:
|
|
rel = insn_fetch(s16, 2, c->eip);
|
|
break;
|
|
case 4:
|
|
rel = insn_fetch(s32, 4, c->eip);
|
|
break;
|
|
case 8:
|
|
rel = insn_fetch(s64, 8, c->eip);
|
|
break;
|
|
default:
|
|
DPRINTF("jnz: Invalid op_bytes\n");
|
|
goto cannot_emulate;
|
|
}
|
|
if (test_cc(c->b, ctxt->eflags))
|
|
jmp_rel(c, rel);
|
|
c->dst.type = OP_NONE;
|
|
break;
|
|
}
|
|
case 0xa3:
|
|
bt: /* bt */
|
|
c->dst.type = OP_NONE;
|
|
/* only subword offset */
|
|
c->src.val &= (c->dst.bytes << 3) - 1;
|
|
emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
|
|
break;
|
|
case 0xab:
|
|
bts: /* bts */
|
|
/* only subword offset */
|
|
c->src.val &= (c->dst.bytes << 3) - 1;
|
|
emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
|
|
break;
|
|
case 0xae: /* clflush */
|
|
break;
|
|
case 0xb0 ... 0xb1: /* cmpxchg */
|
|
/*
|
|
* Save real source value, then compare EAX against
|
|
* destination.
|
|
*/
|
|
c->src.orig_val = c->src.val;
|
|
c->src.val = c->regs[VCPU_REGS_RAX];
|
|
emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
|
|
if (ctxt->eflags & EFLG_ZF) {
|
|
/* Success: write back to memory. */
|
|
c->dst.val = c->src.orig_val;
|
|
} else {
|
|
/* Failure: write the value we saw to EAX. */
|
|
c->dst.type = OP_REG;
|
|
c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
|
|
}
|
|
break;
|
|
case 0xb3:
|
|
btr: /* btr */
|
|
/* only subword offset */
|
|
c->src.val &= (c->dst.bytes << 3) - 1;
|
|
emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
|
|
break;
|
|
case 0xb6 ... 0xb7: /* movzx */
|
|
c->dst.bytes = c->op_bytes;
|
|
c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
|
|
: (u16) c->src.val;
|
|
break;
|
|
case 0xba: /* Grp8 */
|
|
switch (c->modrm_reg & 3) {
|
|
case 0:
|
|
goto bt;
|
|
case 1:
|
|
goto bts;
|
|
case 2:
|
|
goto btr;
|
|
case 3:
|
|
goto btc;
|
|
}
|
|
break;
|
|
case 0xbb:
|
|
btc: /* btc */
|
|
/* only subword offset */
|
|
c->src.val &= (c->dst.bytes << 3) - 1;
|
|
emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
|
|
break;
|
|
case 0xbe ... 0xbf: /* movsx */
|
|
c->dst.bytes = c->op_bytes;
|
|
c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
|
|
(s16) c->src.val;
|
|
break;
|
|
case 0xc3: /* movnti */
|
|
c->dst.bytes = c->op_bytes;
|
|
c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
|
|
(u64) c->src.val;
|
|
break;
|
|
case 0xc7: /* Grp9 (cmpxchg8b) */
|
|
rc = emulate_grp9(ctxt, ops, memop);
|
|
if (rc != 0)
|
|
goto done;
|
|
c->dst.type = OP_NONE;
|
|
break;
|
|
}
|
|
goto writeback;
|
|
|
|
cannot_emulate:
|
|
DPRINTF("Cannot emulate %02x\n", c->b);
|
|
c->eip = saved_eip;
|
|
return -1;
|
|
}
|