![Benjamin Herrenschmidt](/assets/img/avatar_default.png)
On CHRP platforms with only a 8259 controller, we should set the default IRQ host to the 8259 driver's one for the IRQ probing fallbacks to work in case the IRQ tree is incorrect (like on Pegasos for example). Without this fix, we get a bunch of WARN_ON's during boot. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
301 lines
7.2 KiB
C
301 lines
7.2 KiB
C
/*
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* i8259 interrupt controller driver.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#undef DEBUG
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include <asm/i8259.h>
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#include <asm/prom.h>
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static volatile void __iomem *pci_intack; /* RO, gives us the irq vector */
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static unsigned char cached_8259[2] = { 0xff, 0xff };
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#define cached_A1 (cached_8259[0])
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#define cached_21 (cached_8259[1])
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static DEFINE_SPINLOCK(i8259_lock);
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static struct device_node *i8259_node;
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static struct irq_host *i8259_host;
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/*
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* Acknowledge the IRQ using either the PCI host bridge's interrupt
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* acknowledge feature or poll. How i8259_init() is called determines
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* which is called. It should be noted that polling is broken on some
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* IBM and Motorola PReP boxes so we must use the int-ack feature on them.
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*/
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unsigned int i8259_irq(void)
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{
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int irq;
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int lock = 0;
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/* Either int-ack or poll for the IRQ */
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if (pci_intack)
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irq = readb(pci_intack);
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else {
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spin_lock(&i8259_lock);
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lock = 1;
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/* Perform an interrupt acknowledge cycle on controller 1. */
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outb(0x0C, 0x20); /* prepare for poll */
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irq = inb(0x20) & 7;
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if (irq == 2 ) {
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/*
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* Interrupt is cascaded so perform interrupt
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* acknowledge on controller 2.
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*/
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outb(0x0C, 0xA0); /* prepare for poll */
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irq = (inb(0xA0) & 7) + 8;
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}
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}
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if (irq == 7) {
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/*
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* This may be a spurious interrupt.
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*
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* Read the interrupt status register (ISR). If the most
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* significant bit is not set then there is no valid
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* interrupt.
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*/
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if (!pci_intack)
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outb(0x0B, 0x20); /* ISR register */
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if(~inb(0x20) & 0x80)
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irq = NO_IRQ;
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} else if (irq == 0xff)
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irq = NO_IRQ;
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if (lock)
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spin_unlock(&i8259_lock);
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return irq;
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}
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static void i8259_mask_and_ack_irq(unsigned int irq_nr)
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{
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unsigned long flags;
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spin_lock_irqsave(&i8259_lock, flags);
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if (irq_nr > 7) {
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cached_A1 |= 1 << (irq_nr-8);
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inb(0xA1); /* DUMMY */
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outb(cached_A1, 0xA1);
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outb(0x20, 0xA0); /* Non-specific EOI */
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outb(0x20, 0x20); /* Non-specific EOI to cascade */
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} else {
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cached_21 |= 1 << irq_nr;
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inb(0x21); /* DUMMY */
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outb(cached_21, 0x21);
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outb(0x20, 0x20); /* Non-specific EOI */
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}
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spin_unlock_irqrestore(&i8259_lock, flags);
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}
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static void i8259_set_irq_mask(int irq_nr)
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{
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outb(cached_A1,0xA1);
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outb(cached_21,0x21);
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}
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static void i8259_mask_irq(unsigned int irq_nr)
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{
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unsigned long flags;
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pr_debug("i8259_mask_irq(%d)\n", irq_nr);
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spin_lock_irqsave(&i8259_lock, flags);
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if (irq_nr < 8)
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cached_21 |= 1 << irq_nr;
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else
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cached_A1 |= 1 << (irq_nr-8);
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i8259_set_irq_mask(irq_nr);
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spin_unlock_irqrestore(&i8259_lock, flags);
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}
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static void i8259_unmask_irq(unsigned int irq_nr)
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{
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unsigned long flags;
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pr_debug("i8259_unmask_irq(%d)\n", irq_nr);
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spin_lock_irqsave(&i8259_lock, flags);
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if (irq_nr < 8)
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cached_21 &= ~(1 << irq_nr);
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else
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cached_A1 &= ~(1 << (irq_nr-8));
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i8259_set_irq_mask(irq_nr);
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spin_unlock_irqrestore(&i8259_lock, flags);
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}
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static struct irq_chip i8259_pic = {
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.typename = " i8259 ",
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.mask = i8259_mask_irq,
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.unmask = i8259_unmask_irq,
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.mask_ack = i8259_mask_and_ack_irq,
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};
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static struct resource pic1_iores = {
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.name = "8259 (master)",
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.start = 0x20,
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.end = 0x21,
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.flags = IORESOURCE_BUSY,
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};
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static struct resource pic2_iores = {
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.name = "8259 (slave)",
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.start = 0xa0,
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.end = 0xa1,
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.flags = IORESOURCE_BUSY,
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};
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static struct resource pic_edgectrl_iores = {
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.name = "8259 edge control",
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.start = 0x4d0,
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.end = 0x4d1,
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.flags = IORESOURCE_BUSY,
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};
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static int i8259_host_match(struct irq_host *h, struct device_node *node)
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{
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return i8259_node == NULL || i8259_node == node;
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}
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static int i8259_host_map(struct irq_host *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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pr_debug("i8259_host_map(%d, 0x%lx)\n", virq, hw);
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/* We block the internal cascade */
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if (hw == 2)
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get_irq_desc(virq)->status |= IRQ_NOREQUEST;
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/* We use the level handler only for now, we might want to
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* be more cautious here but that works for now
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*/
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get_irq_desc(virq)->status |= IRQ_LEVEL;
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set_irq_chip_and_handler(virq, &i8259_pic, handle_level_irq);
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return 0;
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}
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static void i8259_host_unmap(struct irq_host *h, unsigned int virq)
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{
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/* Make sure irq is masked in hardware */
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i8259_mask_irq(virq);
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/* remove chip and handler */
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set_irq_chip_and_handler(virq, NULL, NULL);
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/* Make sure it's completed */
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synchronize_irq(virq);
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}
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static int i8259_host_xlate(struct irq_host *h, struct device_node *ct,
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u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq, unsigned int *out_flags)
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{
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static unsigned char map_isa_senses[4] = {
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IRQ_TYPE_LEVEL_LOW,
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IRQ_TYPE_LEVEL_HIGH,
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IRQ_TYPE_EDGE_FALLING,
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IRQ_TYPE_EDGE_RISING,
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};
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*out_hwirq = intspec[0];
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if (intsize > 1 && intspec[1] < 4)
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*out_flags = map_isa_senses[intspec[1]];
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else
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*out_flags = IRQ_TYPE_NONE;
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return 0;
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}
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static struct irq_host_ops i8259_host_ops = {
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.match = i8259_host_match,
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.map = i8259_host_map,
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.unmap = i8259_host_unmap,
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.xlate = i8259_host_xlate,
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};
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struct irq_host *i8259_get_host(void)
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{
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return i8259_host;
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}
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/**
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* i8259_init - Initialize the legacy controller
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* @node: device node of the legacy PIC (can be NULL, but then, it will match
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* all interrupts, so beware)
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* @intack_addr: PCI interrupt acknowledge (real) address which will return
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* the active irq from the 8259
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*/
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void i8259_init(struct device_node *node, unsigned long intack_addr)
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{
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unsigned long flags;
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/* initialize the controller */
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spin_lock_irqsave(&i8259_lock, flags);
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/* Mask all first */
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outb(0xff, 0xA1);
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outb(0xff, 0x21);
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/* init master interrupt controller */
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outb(0x11, 0x20); /* Start init sequence */
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outb(0x00, 0x21); /* Vector base */
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outb(0x04, 0x21); /* edge tiggered, Cascade (slave) on IRQ2 */
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outb(0x01, 0x21); /* Select 8086 mode */
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/* init slave interrupt controller */
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outb(0x11, 0xA0); /* Start init sequence */
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outb(0x08, 0xA1); /* Vector base */
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outb(0x02, 0xA1); /* edge triggered, Cascade (slave) on IRQ2 */
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outb(0x01, 0xA1); /* Select 8086 mode */
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/* That thing is slow */
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udelay(100);
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/* always read ISR */
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outb(0x0B, 0x20);
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outb(0x0B, 0xA0);
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/* Unmask the internal cascade */
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cached_21 &= ~(1 << 2);
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/* Set interrupt masks */
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outb(cached_A1, 0xA1);
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outb(cached_21, 0x21);
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spin_unlock_irqrestore(&i8259_lock, flags);
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/* create a legacy host */
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if (node)
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i8259_node = of_node_get(node);
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i8259_host = irq_alloc_host(IRQ_HOST_MAP_LEGACY, 0, &i8259_host_ops, 0);
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if (i8259_host == NULL) {
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printk(KERN_ERR "i8259: failed to allocate irq host !\n");
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return;
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}
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/* reserve our resources */
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/* XXX should we continue doing that ? it seems to cause problems
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* with further requesting of PCI IO resources for that range...
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* need to look into it.
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*/
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request_resource(&ioport_resource, &pic1_iores);
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request_resource(&ioport_resource, &pic2_iores);
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request_resource(&ioport_resource, &pic_edgectrl_iores);
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if (intack_addr != 0)
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pci_intack = ioremap(intack_addr, 1);
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printk(KERN_INFO "i8259 legacy interrupt controller initialized\n");
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}
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