![Timur Tabi](/assets/img/avatar_default.png)
The rheap allocation functions return a pointer, but the actual value is based on how the heap was initialized, and so it can be anything, e.g. an offset into a buffer. A ulong is a better representation of the value returned by the allocation functions. This patch changes all of the relevant rheap functions to use a unsigned long integers instead of a pointer. In case of an error, the value returned is a negative error code that has been cast to an unsigned long. The caller can use the IS_ERR_VALUE() macro to check for this. All code which calls the rheap functions is updated accordingly. Macros IS_MURAM_ERR() and IS_DPERR(), have been deleted in favor of IS_ERR_VALUE(). Also added error checking to rh_attach_region(). Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
399 lines
9.9 KiB
C
399 lines
9.9 KiB
C
/*
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* General Purpose functions for the global management of the
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* Communication Processor Module.
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* Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
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*
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* In addition to the individual control of the communication
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* channels, there are a few functions that globally affect the
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* communication processor.
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*
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* Buffer descriptors must be allocated from the dual ported memory
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* space. The allocator for that is here. When the communication
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* process is reset, we reclaim the memory available. There is
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* currently no deallocator for this memory.
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* The amount of space available is platform dependent. On the
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* MBX, the EPPC software loads additional microcode into the
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* communication processor, and uses some of the DP ram for this
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* purpose. Current, the first 512 bytes and the last 256 bytes of
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* memory are used. Right now I am conservative and only use the
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* memory that can never be used for microcode. If there are
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* applications that require more DP ram, we can expand the boundaries
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* but then we have to be careful of any downloaded microcode.
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*/
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/dma-mapping.h>
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#include <linux/param.h>
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#include <linux/string.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <asm/mpc8xx.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/8xx_immap.h>
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#include <asm/commproc.h>
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#include <asm/io.h>
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#include <asm/tlbflush.h>
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#include <asm/rheap.h>
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#include <asm/prom.h>
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#include <asm/fs_pd.h>
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#define CPM_MAP_SIZE (0x4000)
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static void m8xx_cpm_dpinit(void);
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static uint host_buffer; /* One page of host buffer */
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static uint host_end; /* end + 1 */
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cpm8xx_t *cpmp; /* Pointer to comm processor space */
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cpic8xx_t *cpic_reg;
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static struct device_node *cpm_pic_node;
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static struct irq_host *cpm_pic_host;
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static void cpm_mask_irq(unsigned int irq)
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{
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unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;
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clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
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}
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static void cpm_unmask_irq(unsigned int irq)
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{
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unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;
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setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
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}
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static void cpm_end_irq(unsigned int irq)
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{
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unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;
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out_be32(&cpic_reg->cpic_cisr, (1 << cpm_vec));
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}
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static struct irq_chip cpm_pic = {
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.typename = " CPM PIC ",
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.mask = cpm_mask_irq,
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.unmask = cpm_unmask_irq,
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.eoi = cpm_end_irq,
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};
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int cpm_get_irq(void)
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{
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int cpm_vec;
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/* Get the vector by setting the ACK bit and then reading
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* the register.
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*/
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out_be16(&cpic_reg->cpic_civr, 1);
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cpm_vec = in_be16(&cpic_reg->cpic_civr);
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cpm_vec >>= 11;
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return irq_linear_revmap(cpm_pic_host, cpm_vec);
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}
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static int cpm_pic_host_match(struct irq_host *h, struct device_node *node)
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{
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return cpm_pic_node == node;
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}
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static int cpm_pic_host_map(struct irq_host *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw);
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get_irq_desc(virq)->status |= IRQ_LEVEL;
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set_irq_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq);
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return 0;
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}
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/* The CPM can generate the error interrupt when there is a race condition
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* between generating and masking interrupts. All we have to do is ACK it
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* and return. This is a no-op function so we don't need any special
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* tests in the interrupt handler.
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*/
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static irqreturn_t cpm_error_interrupt(int irq, void *dev)
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{
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return IRQ_HANDLED;
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}
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static struct irqaction cpm_error_irqaction = {
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.handler = cpm_error_interrupt,
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.mask = CPU_MASK_NONE,
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.name = "error",
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};
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static struct irq_host_ops cpm_pic_host_ops = {
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.match = cpm_pic_host_match,
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.map = cpm_pic_host_map,
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};
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unsigned int cpm_pic_init(void)
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{
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struct device_node *np = NULL;
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struct resource res;
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unsigned int sirq = NO_IRQ, hwirq, eirq;
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int ret;
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pr_debug("cpm_pic_init\n");
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np = of_find_compatible_node(NULL, "cpm-pic", "CPM");
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if (np == NULL) {
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printk(KERN_ERR "CPM PIC init: can not find cpm-pic node\n");
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return sirq;
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}
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ret = of_address_to_resource(np, 0, &res);
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if (ret)
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goto end;
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cpic_reg = (void *)ioremap(res.start, res.end - res.start + 1);
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if (cpic_reg == NULL)
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goto end;
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sirq = irq_of_parse_and_map(np, 0);
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if (sirq == NO_IRQ)
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goto end;
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/* Initialize the CPM interrupt controller. */
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hwirq = (unsigned int)irq_map[sirq].hwirq;
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out_be32(&cpic_reg->cpic_cicr,
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(CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) |
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((hwirq/2) << 13) | CICR_HP_MASK);
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out_be32(&cpic_reg->cpic_cimr, 0);
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cpm_pic_node = of_node_get(np);
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cpm_pic_host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, 64, &cpm_pic_host_ops, 64);
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if (cpm_pic_host == NULL) {
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printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n");
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sirq = NO_IRQ;
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goto end;
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}
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of_node_put(np);
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/* Install our own error handler. */
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np = of_find_node_by_type(NULL, "cpm");
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if (np == NULL) {
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printk(KERN_ERR "CPM PIC init: can not find cpm node\n");
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goto end;
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}
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eirq= irq_of_parse_and_map(np, 0);
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if (eirq == NO_IRQ)
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goto end;
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if (setup_irq(eirq, &cpm_error_irqaction))
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printk(KERN_ERR "Could not allocate CPM error IRQ!");
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setbits32(&cpic_reg->cpic_cicr, CICR_IEN);
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end:
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of_node_put(np);
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return sirq;
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}
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void cpm_reset(void)
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{
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cpm8xx_t *commproc;
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sysconf8xx_t *siu_conf;
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commproc = (cpm8xx_t *)ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE);
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#ifdef CONFIG_UCODE_PATCH
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/* Perform a reset.
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*/
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out_be16(&commproc->cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
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/* Wait for it.
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*/
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while (in_be16(&commproc->cp_cpcr) & CPM_CR_FLG);
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cpm_load_patch(commproc);
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#endif
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/* Set SDMA Bus Request priority 5.
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* On 860T, this also enables FEC priority 6. I am not sure
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* this is what we realy want for some applications, but the
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* manual recommends it.
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* Bit 25, FAM can also be set to use FEC aggressive mode (860T).
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*/
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siu_conf = (sysconf8xx_t*)immr_map(im_siu_conf);
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out_be32(&siu_conf->sc_sdcr, 1);
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immr_unmap(siu_conf);
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/* Reclaim the DP memory for our use. */
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m8xx_cpm_dpinit();
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/* Tell everyone where the comm processor resides.
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*/
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cpmp = commproc;
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}
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/* We used to do this earlier, but have to postpone as long as possible
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* to ensure the kernel VM is now running.
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*/
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static void
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alloc_host_memory(void)
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{
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dma_addr_t physaddr;
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/* Set the host page for allocation.
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*/
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host_buffer = (uint)dma_alloc_coherent(NULL, PAGE_SIZE, &physaddr,
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GFP_KERNEL);
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host_end = host_buffer + PAGE_SIZE;
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}
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/* We also own one page of host buffer space for the allocation of
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* UART "fifos" and the like.
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*/
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uint
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m8xx_cpm_hostalloc(uint size)
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{
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uint retloc;
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if (host_buffer == 0)
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alloc_host_memory();
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if ((host_buffer + size) >= host_end)
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return(0);
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retloc = host_buffer;
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host_buffer += size;
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return(retloc);
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}
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/* Set a baud rate generator. This needs lots of work. There are
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* four BRGs, any of which can be wired to any channel.
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* The internal baud rate clock is the system clock divided by 16.
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* This assumes the baudrate is 16x oversampled by the uart.
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*/
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#define BRG_INT_CLK (get_brgfreq())
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#define BRG_UART_CLK (BRG_INT_CLK/16)
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#define BRG_UART_CLK_DIV16 (BRG_UART_CLK/16)
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void
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cpm_setbrg(uint brg, uint rate)
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{
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volatile uint *bp;
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/* This is good enough to get SMCs running.....
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*/
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bp = (uint *)&cpmp->cp_brgc1;
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bp += brg;
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/* The BRG has a 12-bit counter. For really slow baud rates (or
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* really fast processors), we may have to further divide by 16.
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*/
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if (((BRG_UART_CLK / rate) - 1) < 4096)
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*bp = (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN;
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else
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*bp = (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) |
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CPM_BRG_EN | CPM_BRG_DIV16;
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}
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/*
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* dpalloc / dpfree bits.
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*/
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static spinlock_t cpm_dpmem_lock;
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/*
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* 16 blocks should be enough to satisfy all requests
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* until the memory subsystem goes up...
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*/
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static rh_block_t cpm_boot_dpmem_rh_block[16];
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static rh_info_t cpm_dpmem_info;
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#define CPM_DPMEM_ALIGNMENT 8
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static u8* dpram_vbase;
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static uint dpram_pbase;
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void m8xx_cpm_dpinit(void)
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{
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spin_lock_init(&cpm_dpmem_lock);
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dpram_vbase = immr_map_size(im_cpm.cp_dpmem, CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE);
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dpram_pbase = (uint)&((immap_t *)IMAP_ADDR)->im_cpm.cp_dpmem;
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/* Initialize the info header */
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rh_init(&cpm_dpmem_info, CPM_DPMEM_ALIGNMENT,
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sizeof(cpm_boot_dpmem_rh_block) /
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sizeof(cpm_boot_dpmem_rh_block[0]),
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cpm_boot_dpmem_rh_block);
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/*
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* Attach the usable dpmem area.
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* XXX: This is actually crap. CPM_DATAONLY_BASE and
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* CPM_DATAONLY_SIZE are a subset of the available dparm. It varies
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* with the processor and the microcode patches applied / activated.
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* But the following should be at least safe.
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*/
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rh_attach_region(&cpm_dpmem_info, CPM_DATAONLY_BASE, CPM_DATAONLY_SIZE);
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}
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/*
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* Allocate the requested size worth of DP memory.
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* This function returns an offset into the DPRAM area.
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* Use cpm_dpram_addr() to get the virtual address of the area.
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*/
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unsigned long cpm_dpalloc(uint size, uint align)
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{
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unsigned long start;
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unsigned long flags;
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spin_lock_irqsave(&cpm_dpmem_lock, flags);
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cpm_dpmem_info.alignment = align;
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start = rh_alloc(&cpm_dpmem_info, size, "commproc");
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spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
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return (uint)start;
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}
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EXPORT_SYMBOL(cpm_dpalloc);
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int cpm_dpfree(unsigned long offset)
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{
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int ret;
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unsigned long flags;
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spin_lock_irqsave(&cpm_dpmem_lock, flags);
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ret = rh_free(&cpm_dpmem_info, offset);
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spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
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return ret;
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}
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EXPORT_SYMBOL(cpm_dpfree);
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unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align)
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{
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unsigned long start;
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unsigned long flags;
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spin_lock_irqsave(&cpm_dpmem_lock, flags);
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cpm_dpmem_info.alignment = align;
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start = rh_alloc_fixed(&cpm_dpmem_info, offset, size, "commproc");
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spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
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return start;
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}
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EXPORT_SYMBOL(cpm_dpalloc_fixed);
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void cpm_dpdump(void)
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{
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rh_dump(&cpm_dpmem_info);
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}
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EXPORT_SYMBOL(cpm_dpdump);
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void *cpm_dpram_addr(unsigned long offset)
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{
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return (void *)(dpram_vbase + offset);
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}
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EXPORT_SYMBOL(cpm_dpram_addr);
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uint cpm_dpram_phys(u8* addr)
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{
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return (dpram_pbase + (uint)(addr - dpram_vbase));
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}
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EXPORT_SYMBOL(cpm_dpram_addr);
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