![Tony Lindgren](/assets/img/avatar_default.png)
Mostly clean up CONFIG_OMAP_RESET_CLOCKS. Also includes a patch from Imre Deak to make McSPI clocks use id. Signed-off-by: Tony Lindgren <tony@atomide.com>
797 lines
19 KiB
C
797 lines
19 KiB
C
//kernel/linux-omap-fsample/arch/arm/mach-omap1/clock.c#2 - edit change 3808 (text)
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/*
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* linux/arch/arm/mach-omap1/clock.c
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*
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* Copyright (C) 2004 - 2005 Nokia corporation
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* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
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*
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* Modified to use omap shared clock framework by
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* Tony Lindgren <tony@atomide.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <asm/io.h>
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#include <asm/mach-types.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/usb.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sram.h>
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#include "clock.h"
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__u32 arm_idlect1_mask;
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/*-------------------------------------------------------------------------
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* Omap1 specific clock functions
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*-------------------------------------------------------------------------*/
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static void omap1_watchdog_recalc(struct clk * clk)
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{
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clk->rate = clk->parent->rate / 14;
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}
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static void omap1_uart_recalc(struct clk * clk)
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{
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unsigned int val = omap_readl(clk->enable_reg);
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if (val & clk->enable_bit)
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clk->rate = 48000000;
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else
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clk->rate = 12000000;
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}
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static int omap1_clk_enable_dsp_domain(struct clk *clk)
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{
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int retval;
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retval = omap1_clk_enable(&api_ck.clk);
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if (!retval) {
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retval = omap1_clk_enable_generic(clk);
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omap1_clk_disable(&api_ck.clk);
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}
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return retval;
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}
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static void omap1_clk_disable_dsp_domain(struct clk *clk)
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{
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if (omap1_clk_enable(&api_ck.clk) == 0) {
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omap1_clk_disable_generic(clk);
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omap1_clk_disable(&api_ck.clk);
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}
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}
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static int omap1_clk_enable_uart_functional(struct clk *clk)
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{
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int ret;
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struct uart_clk *uclk;
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ret = omap1_clk_enable_generic(clk);
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if (ret == 0) {
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/* Set smart idle acknowledgement mode */
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uclk = (struct uart_clk *)clk;
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omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
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uclk->sysc_addr);
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}
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return ret;
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}
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static void omap1_clk_disable_uart_functional(struct clk *clk)
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{
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struct uart_clk *uclk;
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/* Set force idle acknowledgement mode */
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uclk = (struct uart_clk *)clk;
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omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
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omap1_clk_disable_generic(clk);
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}
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static void omap1_clk_allow_idle(struct clk *clk)
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{
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struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
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if (!(clk->flags & CLOCK_IDLE_CONTROL))
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return;
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if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count))
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arm_idlect1_mask |= 1 << iclk->idlect_shift;
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}
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static void omap1_clk_deny_idle(struct clk *clk)
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{
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struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
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if (!(clk->flags & CLOCK_IDLE_CONTROL))
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return;
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if (iclk->no_idle_count++ == 0)
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arm_idlect1_mask &= ~(1 << iclk->idlect_shift);
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}
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static __u16 verify_ckctl_value(__u16 newval)
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{
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/* This function checks for following limitations set
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* by the hardware (all conditions must be true):
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* DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
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* ARM_CK >= TC_CK
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* DSP_CK >= TC_CK
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* DSPMMU_CK >= TC_CK
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*
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* In addition following rules are enforced:
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* LCD_CK <= TC_CK
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* ARMPER_CK <= TC_CK
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*
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* However, maximum frequencies are not checked for!
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*/
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__u8 per_exp;
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__u8 lcd_exp;
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__u8 arm_exp;
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__u8 dsp_exp;
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__u8 tc_exp;
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__u8 dspmmu_exp;
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per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
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lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
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arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
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dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
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tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
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dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
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if (dspmmu_exp < dsp_exp)
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dspmmu_exp = dsp_exp;
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if (dspmmu_exp > dsp_exp+1)
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dspmmu_exp = dsp_exp+1;
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if (tc_exp < arm_exp)
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tc_exp = arm_exp;
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if (tc_exp < dspmmu_exp)
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tc_exp = dspmmu_exp;
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if (tc_exp > lcd_exp)
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lcd_exp = tc_exp;
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if (tc_exp > per_exp)
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per_exp = tc_exp;
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newval &= 0xf000;
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newval |= per_exp << CKCTL_PERDIV_OFFSET;
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newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
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newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
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newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
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newval |= tc_exp << CKCTL_TCDIV_OFFSET;
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newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
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return newval;
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}
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static int calc_dsor_exp(struct clk *clk, unsigned long rate)
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{
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/* Note: If target frequency is too low, this function will return 4,
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* which is invalid value. Caller must check for this value and act
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* accordingly.
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*
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* Note: This function does not check for following limitations set
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* by the hardware (all conditions must be true):
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* DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
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* ARM_CK >= TC_CK
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* DSP_CK >= TC_CK
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* DSPMMU_CK >= TC_CK
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*/
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unsigned long realrate;
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struct clk * parent;
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unsigned dsor_exp;
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if (unlikely(!(clk->flags & RATE_CKCTL)))
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return -EINVAL;
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parent = clk->parent;
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if (unlikely(parent == 0))
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return -EIO;
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realrate = parent->rate;
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for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
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if (realrate <= rate)
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break;
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realrate /= 2;
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}
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return dsor_exp;
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}
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static void omap1_ckctl_recalc(struct clk * clk)
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{
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int dsor;
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/* Calculate divisor encoded as 2-bit exponent */
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dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
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if (unlikely(clk->rate == clk->parent->rate / dsor))
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return; /* No change, quick exit */
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clk->rate = clk->parent->rate / dsor;
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if (unlikely(clk->flags & RATE_PROPAGATES))
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propagate_rate(clk);
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}
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static void omap1_ckctl_recalc_dsp_domain(struct clk * clk)
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{
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int dsor;
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/* Calculate divisor encoded as 2-bit exponent
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*
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* The clock control bits are in DSP domain,
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* so api_ck is needed for access.
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* Note that DSP_CKCTL virt addr = phys addr, so
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* we must use __raw_readw() instead of omap_readw().
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*/
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omap1_clk_enable(&api_ck.clk);
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dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
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omap1_clk_disable(&api_ck.clk);
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if (unlikely(clk->rate == clk->parent->rate / dsor))
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return; /* No change, quick exit */
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clk->rate = clk->parent->rate / dsor;
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if (unlikely(clk->flags & RATE_PROPAGATES))
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propagate_rate(clk);
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}
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/* MPU virtual clock functions */
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static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
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{
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/* Find the highest supported frequency <= rate and switch to it */
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struct mpu_rate * ptr;
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if (clk != &virtual_ck_mpu)
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return -EINVAL;
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for (ptr = rate_table; ptr->rate; ptr++) {
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if (ptr->xtal != ck_ref.rate)
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continue;
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/* DPLL1 cannot be reprogrammed without risking system crash */
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if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate)
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continue;
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/* Can check only after xtal frequency check */
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if (ptr->rate <= rate)
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break;
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}
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if (!ptr->rate)
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return -EINVAL;
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/*
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* In most cases we should not need to reprogram DPLL.
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* Reprogramming the DPLL is tricky, it must be done from SRAM.
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* (on 730, bit 13 must always be 1)
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*/
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if (cpu_is_omap730())
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omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
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else
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omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
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ck_dpll1.rate = ptr->pll_rate;
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propagate_rate(&ck_dpll1);
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return 0;
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}
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static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
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{
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int ret = -EINVAL;
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int dsor_exp;
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__u16 regval;
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if (clk->flags & RATE_CKCTL) {
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dsor_exp = calc_dsor_exp(clk, rate);
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if (dsor_exp > 3)
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dsor_exp = -EINVAL;
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if (dsor_exp < 0)
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return dsor_exp;
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regval = __raw_readw(DSP_CKCTL);
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regval &= ~(3 << clk->rate_offset);
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regval |= dsor_exp << clk->rate_offset;
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__raw_writew(regval, DSP_CKCTL);
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clk->rate = clk->parent->rate / (1 << dsor_exp);
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ret = 0;
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}
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if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
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propagate_rate(clk);
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return ret;
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}
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static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate)
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{
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/* Find the highest supported frequency <= rate */
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struct mpu_rate * ptr;
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long highest_rate;
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if (clk != &virtual_ck_mpu)
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return -EINVAL;
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highest_rate = -EINVAL;
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for (ptr = rate_table; ptr->rate; ptr++) {
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if (ptr->xtal != ck_ref.rate)
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continue;
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highest_rate = ptr->rate;
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/* Can check only after xtal frequency check */
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if (ptr->rate <= rate)
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break;
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}
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return highest_rate;
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}
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static unsigned calc_ext_dsor(unsigned long rate)
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{
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unsigned dsor;
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/* MCLK and BCLK divisor selection is not linear:
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* freq = 96MHz / dsor
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*
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* RATIO_SEL range: dsor <-> RATIO_SEL
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* 0..6: (RATIO_SEL+2) <-> (dsor-2)
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* 6..48: (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
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* Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
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* can not be used.
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*/
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for (dsor = 2; dsor < 96; ++dsor) {
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if ((dsor & 1) && dsor > 8)
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continue;
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if (rate >= 96000000 / dsor)
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break;
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}
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return dsor;
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}
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/* Only needed on 1510 */
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static int omap1_set_uart_rate(struct clk * clk, unsigned long rate)
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{
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unsigned int val;
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val = omap_readl(clk->enable_reg);
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if (rate == 12000000)
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val &= ~(1 << clk->enable_bit);
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else if (rate == 48000000)
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val |= (1 << clk->enable_bit);
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else
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return -EINVAL;
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omap_writel(val, clk->enable_reg);
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clk->rate = rate;
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return 0;
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}
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/* External clock (MCLK & BCLK) functions */
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static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
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{
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unsigned dsor;
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__u16 ratio_bits;
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dsor = calc_ext_dsor(rate);
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clk->rate = 96000000 / dsor;
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if (dsor > 8)
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ratio_bits = ((dsor - 8) / 2 + 6) << 2;
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else
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ratio_bits = (dsor - 2) << 2;
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ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd;
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omap_writew(ratio_bits, clk->enable_reg);
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return 0;
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}
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static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate)
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{
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return 96000000 / calc_ext_dsor(rate);
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}
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static void omap1_init_ext_clk(struct clk * clk)
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{
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unsigned dsor;
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__u16 ratio_bits;
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/* Determine current rate and ensure clock is based on 96MHz APLL */
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ratio_bits = omap_readw(clk->enable_reg) & ~1;
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omap_writew(ratio_bits, clk->enable_reg);
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ratio_bits = (ratio_bits & 0xfc) >> 2;
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if (ratio_bits > 6)
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dsor = (ratio_bits - 6) * 2 + 8;
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else
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dsor = ratio_bits + 2;
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clk-> rate = 96000000 / dsor;
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}
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static int omap1_clk_enable(struct clk *clk)
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{
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int ret = 0;
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if (clk->usecount++ == 0) {
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if (likely(clk->parent)) {
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ret = omap1_clk_enable(clk->parent);
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if (unlikely(ret != 0)) {
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clk->usecount--;
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return ret;
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}
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if (clk->flags & CLOCK_NO_IDLE_PARENT)
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if (!cpu_is_omap24xx())
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omap1_clk_deny_idle(clk->parent);
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}
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ret = clk->enable(clk);
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if (unlikely(ret != 0) && clk->parent) {
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omap1_clk_disable(clk->parent);
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clk->usecount--;
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}
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}
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return ret;
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}
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static void omap1_clk_disable(struct clk *clk)
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{
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if (clk->usecount > 0 && !(--clk->usecount)) {
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clk->disable(clk);
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if (likely(clk->parent)) {
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omap1_clk_disable(clk->parent);
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if (clk->flags & CLOCK_NO_IDLE_PARENT)
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if (!cpu_is_omap24xx())
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omap1_clk_allow_idle(clk->parent);
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}
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}
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}
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static int omap1_clk_enable_generic(struct clk *clk)
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{
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__u16 regval16;
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__u32 regval32;
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if (clk->flags & ALWAYS_ENABLED)
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return 0;
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if (unlikely(clk->enable_reg == 0)) {
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printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
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clk->name);
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return 0;
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}
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if (clk->flags & ENABLE_REG_32BIT) {
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if (clk->flags & VIRTUAL_IO_ADDRESS) {
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regval32 = __raw_readl(clk->enable_reg);
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regval32 |= (1 << clk->enable_bit);
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__raw_writel(regval32, clk->enable_reg);
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} else {
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regval32 = omap_readl(clk->enable_reg);
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regval32 |= (1 << clk->enable_bit);
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omap_writel(regval32, clk->enable_reg);
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}
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} else {
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if (clk->flags & VIRTUAL_IO_ADDRESS) {
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regval16 = __raw_readw(clk->enable_reg);
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regval16 |= (1 << clk->enable_bit);
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__raw_writew(regval16, clk->enable_reg);
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} else {
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regval16 = omap_readw(clk->enable_reg);
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regval16 |= (1 << clk->enable_bit);
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omap_writew(regval16, clk->enable_reg);
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}
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}
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return 0;
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}
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static void omap1_clk_disable_generic(struct clk *clk)
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{
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__u16 regval16;
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__u32 regval32;
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if (clk->enable_reg == 0)
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return;
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if (clk->flags & ENABLE_REG_32BIT) {
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if (clk->flags & VIRTUAL_IO_ADDRESS) {
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regval32 = __raw_readl(clk->enable_reg);
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regval32 &= ~(1 << clk->enable_bit);
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__raw_writel(regval32, clk->enable_reg);
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} else {
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regval32 = omap_readl(clk->enable_reg);
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regval32 &= ~(1 << clk->enable_bit);
|
|
omap_writel(regval32, clk->enable_reg);
|
|
}
|
|
} else {
|
|
if (clk->flags & VIRTUAL_IO_ADDRESS) {
|
|
regval16 = __raw_readw(clk->enable_reg);
|
|
regval16 &= ~(1 << clk->enable_bit);
|
|
__raw_writew(regval16, clk->enable_reg);
|
|
} else {
|
|
regval16 = omap_readw(clk->enable_reg);
|
|
regval16 &= ~(1 << clk->enable_bit);
|
|
omap_writew(regval16, clk->enable_reg);
|
|
}
|
|
}
|
|
}
|
|
|
|
static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
int dsor_exp;
|
|
|
|
if (clk->flags & RATE_FIXED)
|
|
return clk->rate;
|
|
|
|
if (clk->flags & RATE_CKCTL) {
|
|
dsor_exp = calc_dsor_exp(clk, rate);
|
|
if (dsor_exp < 0)
|
|
return dsor_exp;
|
|
if (dsor_exp > 3)
|
|
dsor_exp = 3;
|
|
return clk->parent->rate / (1 << dsor_exp);
|
|
}
|
|
|
|
if(clk->round_rate != 0)
|
|
return clk->round_rate(clk, rate);
|
|
|
|
return clk->rate;
|
|
}
|
|
|
|
static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
int ret = -EINVAL;
|
|
int dsor_exp;
|
|
__u16 regval;
|
|
|
|
if (clk->set_rate)
|
|
ret = clk->set_rate(clk, rate);
|
|
else if (clk->flags & RATE_CKCTL) {
|
|
dsor_exp = calc_dsor_exp(clk, rate);
|
|
if (dsor_exp > 3)
|
|
dsor_exp = -EINVAL;
|
|
if (dsor_exp < 0)
|
|
return dsor_exp;
|
|
|
|
regval = omap_readw(ARM_CKCTL);
|
|
regval &= ~(3 << clk->rate_offset);
|
|
regval |= dsor_exp << clk->rate_offset;
|
|
regval = verify_ckctl_value(regval);
|
|
omap_writew(regval, ARM_CKCTL);
|
|
clk->rate = clk->parent->rate / (1 << dsor_exp);
|
|
ret = 0;
|
|
}
|
|
|
|
if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
|
|
propagate_rate(clk);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*-------------------------------------------------------------------------
|
|
* Omap1 clock reset and init functions
|
|
*-------------------------------------------------------------------------*/
|
|
|
|
#ifdef CONFIG_OMAP_RESET_CLOCKS
|
|
|
|
static void __init omap1_clk_disable_unused(struct clk *clk)
|
|
{
|
|
__u32 regval32;
|
|
|
|
/* Clocks in the DSP domain need api_ck. Just assume bootloader
|
|
* has not enabled any DSP clocks */
|
|
if ((u32)clk->enable_reg == DSP_IDLECT2) {
|
|
printk(KERN_INFO "Skipping reset check for DSP domain "
|
|
"clock \"%s\"\n", clk->name);
|
|
return;
|
|
}
|
|
|
|
/* Is the clock already disabled? */
|
|
if (clk->flags & ENABLE_REG_32BIT) {
|
|
if (clk->flags & VIRTUAL_IO_ADDRESS)
|
|
regval32 = __raw_readl(clk->enable_reg);
|
|
else
|
|
regval32 = omap_readl(clk->enable_reg);
|
|
} else {
|
|
if (clk->flags & VIRTUAL_IO_ADDRESS)
|
|
regval32 = __raw_readw(clk->enable_reg);
|
|
else
|
|
regval32 = omap_readw(clk->enable_reg);
|
|
}
|
|
|
|
if ((regval32 & (1 << clk->enable_bit)) == 0)
|
|
return;
|
|
|
|
/* FIXME: This clock seems to be necessary but no-one
|
|
* has asked for its activation. */
|
|
if (clk == &tc2_ck // FIX: pm.c (SRAM), CCP, Camera
|
|
|| clk == &ck_dpll1out.clk // FIX: SoSSI, SSR
|
|
|| clk == &arm_gpio_ck // FIX: GPIO code for 1510
|
|
) {
|
|
printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
|
|
clk->name);
|
|
return;
|
|
}
|
|
|
|
printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
|
|
clk->disable(clk);
|
|
printk(" done\n");
|
|
}
|
|
|
|
#else
|
|
#define omap1_clk_disable_unused NULL
|
|
#endif
|
|
|
|
static struct clk_functions omap1_clk_functions = {
|
|
.clk_enable = omap1_clk_enable,
|
|
.clk_disable = omap1_clk_disable,
|
|
.clk_round_rate = omap1_clk_round_rate,
|
|
.clk_set_rate = omap1_clk_set_rate,
|
|
.clk_disable_unused = omap1_clk_disable_unused,
|
|
};
|
|
|
|
int __init omap1_clk_init(void)
|
|
{
|
|
struct clk ** clkp;
|
|
const struct omap_clock_config *info;
|
|
int crystal_type = 0; /* Default 12 MHz */
|
|
u32 reg;
|
|
|
|
/* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
|
|
reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
|
|
omap_writew(reg, SOFT_REQ_REG);
|
|
omap_writew(0, SOFT_REQ_REG2);
|
|
|
|
clk_init(&omap1_clk_functions);
|
|
|
|
/* By default all idlect1 clocks are allowed to idle */
|
|
arm_idlect1_mask = ~0;
|
|
|
|
for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) {
|
|
if (((*clkp)->flags &CLOCK_IN_OMAP1510) && cpu_is_omap1510()) {
|
|
clk_register(*clkp);
|
|
continue;
|
|
}
|
|
|
|
if (((*clkp)->flags &CLOCK_IN_OMAP16XX) && cpu_is_omap16xx()) {
|
|
clk_register(*clkp);
|
|
continue;
|
|
}
|
|
|
|
if (((*clkp)->flags &CLOCK_IN_OMAP730) && cpu_is_omap730()) {
|
|
clk_register(*clkp);
|
|
continue;
|
|
}
|
|
|
|
if (((*clkp)->flags &CLOCK_IN_OMAP310) && cpu_is_omap310()) {
|
|
clk_register(*clkp);
|
|
continue;
|
|
}
|
|
}
|
|
|
|
info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
|
|
if (info != NULL) {
|
|
if (!cpu_is_omap1510())
|
|
crystal_type = info->system_clock_type;
|
|
}
|
|
|
|
#if defined(CONFIG_ARCH_OMAP730)
|
|
ck_ref.rate = 13000000;
|
|
#elif defined(CONFIG_ARCH_OMAP16XX)
|
|
if (crystal_type == 2)
|
|
ck_ref.rate = 19200000;
|
|
#endif
|
|
|
|
printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
|
|
omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
|
|
omap_readw(ARM_CKCTL));
|
|
|
|
/* We want to be in syncronous scalable mode */
|
|
omap_writew(0x1000, ARM_SYSST);
|
|
|
|
#ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
|
|
/* Use values set by bootloader. Determine PLL rate and recalculate
|
|
* dependent clocks as if kernel had changed PLL or divisors.
|
|
*/
|
|
{
|
|
unsigned pll_ctl_val = omap_readw(DPLL_CTL);
|
|
|
|
ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
|
|
if (pll_ctl_val & 0x10) {
|
|
/* PLL enabled, apply multiplier and divisor */
|
|
if (pll_ctl_val & 0xf80)
|
|
ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
|
|
ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
|
|
} else {
|
|
/* PLL disabled, apply bypass divisor */
|
|
switch (pll_ctl_val & 0xc) {
|
|
case 0:
|
|
break;
|
|
case 0x4:
|
|
ck_dpll1.rate /= 2;
|
|
break;
|
|
default:
|
|
ck_dpll1.rate /= 4;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
propagate_rate(&ck_dpll1);
|
|
#else
|
|
/* Find the highest supported frequency and enable it */
|
|
if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
|
|
printk(KERN_ERR "System frequencies not set. Check your config.\n");
|
|
/* Guess sane values (60MHz) */
|
|
omap_writew(0x2290, DPLL_CTL);
|
|
omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL);
|
|
ck_dpll1.rate = 60000000;
|
|
propagate_rate(&ck_dpll1);
|
|
}
|
|
#endif
|
|
/* Cache rates for clocks connected to ck_ref (not dpll1) */
|
|
propagate_rate(&ck_ref);
|
|
printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
|
|
"%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
|
|
ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
|
|
ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
|
|
arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
|
|
|
|
#if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
|
|
/* Select slicer output as OMAP input clock */
|
|
omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
|
|
#endif
|
|
|
|
/* Amstrad Delta wants BCLK high when inactive */
|
|
if (machine_is_ams_delta())
|
|
omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
|
|
(1 << SDW_MCLK_INV_BIT),
|
|
ULPD_CLOCK_CTRL);
|
|
|
|
/* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
|
|
/* (on 730, bit 13 must not be cleared) */
|
|
if (cpu_is_omap730())
|
|
omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
|
|
else
|
|
omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
|
|
|
|
/* Put DSP/MPUI into reset until needed */
|
|
omap_writew(0, ARM_RSTCT1);
|
|
omap_writew(1, ARM_RSTCT2);
|
|
omap_writew(0x400, ARM_IDLECT1);
|
|
|
|
/*
|
|
* According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
|
|
* of the ARM_IDLECT2 register must be set to zero. The power-on
|
|
* default value of this bit is one.
|
|
*/
|
|
omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
|
|
|
|
/*
|
|
* Only enable those clocks we will need, let the drivers
|
|
* enable other clocks as necessary
|
|
*/
|
|
clk_enable(&armper_ck.clk);
|
|
clk_enable(&armxor_ck.clk);
|
|
clk_enable(&armtim_ck.clk); /* This should be done by timer code */
|
|
|
|
if (cpu_is_omap15xx())
|
|
clk_enable(&arm_gpio_ck);
|
|
|
|
return 0;
|
|
}
|
|
|