![Nate Case](/assets/img/avatar_default.png)
Configure the BCM5482S secondary SerDes for 1000Base-X mode when the appropriate dev_flags are passed in to phy_connect(). This is needed when the PHY is used for fiber and backplane connections. Signed-off-by: Nate Case <ncase@xes-inc.com> Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
468 lines
13 KiB
C
468 lines
13 KiB
C
/*
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* drivers/net/phy/broadcom.c
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*
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* Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet
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* transceivers.
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*
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* Copyright (c) 2006 Maciej W. Rozycki
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*
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* Inspired by code written by Amy Fong.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/phy.h>
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#define MII_BCM54XX_ECR 0x10 /* BCM54xx extended control register */
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#define MII_BCM54XX_ECR_IM 0x1000 /* Interrupt mask */
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#define MII_BCM54XX_ECR_IF 0x0800 /* Interrupt force */
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#define MII_BCM54XX_ESR 0x11 /* BCM54xx extended status register */
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#define MII_BCM54XX_ESR_IS 0x1000 /* Interrupt status */
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#define MII_BCM54XX_EXP_DATA 0x15 /* Expansion register data */
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#define MII_BCM54XX_EXP_SEL 0x17 /* Expansion register select */
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#define MII_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */
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#define MII_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */
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#define MII_BCM54XX_AUX_CTL 0x18 /* Auxiliary control register */
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#define MII_BCM54XX_ISR 0x1a /* BCM54xx interrupt status register */
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#define MII_BCM54XX_IMR 0x1b /* BCM54xx interrupt mask register */
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#define MII_BCM54XX_INT_CRCERR 0x0001 /* CRC error */
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#define MII_BCM54XX_INT_LINK 0x0002 /* Link status changed */
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#define MII_BCM54XX_INT_SPEED 0x0004 /* Link speed change */
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#define MII_BCM54XX_INT_DUPLEX 0x0008 /* Duplex mode changed */
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#define MII_BCM54XX_INT_LRS 0x0010 /* Local receiver status changed */
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#define MII_BCM54XX_INT_RRS 0x0020 /* Remote receiver status changed */
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#define MII_BCM54XX_INT_SSERR 0x0040 /* Scrambler synchronization error */
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#define MII_BCM54XX_INT_UHCD 0x0080 /* Unsupported HCD negotiated */
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#define MII_BCM54XX_INT_NHCD 0x0100 /* No HCD */
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#define MII_BCM54XX_INT_NHCDL 0x0200 /* No HCD link */
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#define MII_BCM54XX_INT_ANPR 0x0400 /* Auto-negotiation page received */
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#define MII_BCM54XX_INT_LC 0x0800 /* All counters below 128 */
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#define MII_BCM54XX_INT_HC 0x1000 /* Counter above 32768 */
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#define MII_BCM54XX_INT_MDIX 0x2000 /* MDIX status change */
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#define MII_BCM54XX_INT_PSERR 0x4000 /* Pair swap error */
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#define MII_BCM54XX_SHD 0x1c /* 0x1c shadow registers */
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#define MII_BCM54XX_SHD_WRITE 0x8000
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#define MII_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10)
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#define MII_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0)
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/*
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* Broadcom LED source encodings. These are used in BCM5461, BCM5481,
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* BCM5482, and possibly some others.
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*/
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#define BCM_LED_SRC_LINKSPD1 0x0
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#define BCM_LED_SRC_LINKSPD2 0x1
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#define BCM_LED_SRC_XMITLED 0x2
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#define BCM_LED_SRC_ACTIVITYLED 0x3
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#define BCM_LED_SRC_FDXLED 0x4
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#define BCM_LED_SRC_SLAVE 0x5
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#define BCM_LED_SRC_INTR 0x6
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#define BCM_LED_SRC_QUALITY 0x7
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#define BCM_LED_SRC_RCVLED 0x8
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#define BCM_LED_SRC_MULTICOLOR1 0xa
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#define BCM_LED_SRC_OPENSHORT 0xb
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#define BCM_LED_SRC_OFF 0xe /* Tied high */
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#define BCM_LED_SRC_ON 0xf /* Tied low */
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/*
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* BCM5482: Shadow registers
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* Shadow values go into bits [14:10] of register 0x1c to select a shadow
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* register to access.
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*/
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#define BCM5482_SHD_LEDS1 0x0d /* 01101: LED Selector 1 */
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/* LED3 / ~LINKSPD[2] selector */
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#define BCM5482_SHD_LEDS1_LED3(src) ((src & 0xf) << 4)
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/* LED1 / ~LINKSPD[1] selector */
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#define BCM5482_SHD_LEDS1_LED1(src) ((src & 0xf) << 0)
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#define BCM5482_SHD_SSD 0x14 /* 10100: Secondary SerDes control */
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#define BCM5482_SHD_SSD_LEDM 0x0008 /* SSD LED Mode enable */
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#define BCM5482_SHD_SSD_EN 0x0001 /* SSD enable */
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#define BCM5482_SHD_MODE 0x1f /* 11111: Mode Control Register */
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#define BCM5482_SHD_MODE_1000BX 0x0001 /* Enable 1000BASE-X registers */
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/*
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* BCM5482: Secondary SerDes registers
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*/
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#define BCM5482_SSD_1000BX_CTL 0x00 /* 1000BASE-X Control */
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#define BCM5482_SSD_1000BX_CTL_PWRDOWN 0x0800 /* Power-down SSD */
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#define BCM5482_SSD_SGMII_SLAVE 0x15 /* SGMII Slave Register */
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#define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */
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#define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */
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/*
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* Device flags for PHYs that can be configured for different operating
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* modes.
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*/
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#define PHY_BCM_FLAGS_VALID 0x80000000
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#define PHY_BCM_FLAGS_INTF_XAUI 0x00000020
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#define PHY_BCM_FLAGS_INTF_SGMII 0x00000010
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#define PHY_BCM_FLAGS_MODE_1000BX 0x00000002
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#define PHY_BCM_FLAGS_MODE_COPPER 0x00000001
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MODULE_DESCRIPTION("Broadcom PHY driver");
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MODULE_AUTHOR("Maciej W. Rozycki");
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MODULE_LICENSE("GPL");
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/*
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* Indirect register access functions for the 1000BASE-T/100BASE-TX/10BASE-T
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* 0x1c shadow registers.
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*/
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static int bcm54xx_shadow_read(struct phy_device *phydev, u16 shadow)
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{
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phy_write(phydev, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow));
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return MII_BCM54XX_SHD_DATA(phy_read(phydev, MII_BCM54XX_SHD));
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}
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static int bcm54xx_shadow_write(struct phy_device *phydev, u16 shadow, u16 val)
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{
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return phy_write(phydev, MII_BCM54XX_SHD,
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MII_BCM54XX_SHD_WRITE |
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MII_BCM54XX_SHD_VAL(shadow) |
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MII_BCM54XX_SHD_DATA(val));
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}
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/*
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* Indirect register access functions for the Expansion Registers
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* and Secondary SerDes registers (when sec_serdes=1).
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*/
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static int bcm54xx_exp_read(struct phy_device *phydev,
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int sec_serdes, u8 regnum)
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{
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int val;
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phy_write(phydev, MII_BCM54XX_EXP_SEL,
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(sec_serdes ? MII_BCM54XX_EXP_SEL_SSD :
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MII_BCM54XX_EXP_SEL_ER) |
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regnum);
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val = phy_read(phydev, MII_BCM54XX_EXP_DATA);
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phy_write(phydev, MII_BCM54XX_EXP_SEL, regnum);
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return val;
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}
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static int bcm54xx_exp_write(struct phy_device *phydev,
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int sec_serdes, u8 regnum, u16 val)
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{
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int ret;
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phy_write(phydev, MII_BCM54XX_EXP_SEL,
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(sec_serdes ? MII_BCM54XX_EXP_SEL_SSD :
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MII_BCM54XX_EXP_SEL_ER) |
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regnum);
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ret = phy_write(phydev, MII_BCM54XX_EXP_DATA, val);
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phy_write(phydev, MII_BCM54XX_EXP_SEL, regnum);
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return ret;
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}
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static int bcm54xx_config_init(struct phy_device *phydev)
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{
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int reg, err;
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reg = phy_read(phydev, MII_BCM54XX_ECR);
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if (reg < 0)
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return reg;
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/* Mask interrupts globally. */
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reg |= MII_BCM54XX_ECR_IM;
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err = phy_write(phydev, MII_BCM54XX_ECR, reg);
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if (err < 0)
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return err;
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/* Unmask events we are interested in. */
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reg = ~(MII_BCM54XX_INT_DUPLEX |
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MII_BCM54XX_INT_SPEED |
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MII_BCM54XX_INT_LINK);
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err = phy_write(phydev, MII_BCM54XX_IMR, reg);
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if (err < 0)
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return err;
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return 0;
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}
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static int bcm5482_config_init(struct phy_device *phydev)
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{
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int err, reg;
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err = bcm54xx_config_init(phydev);
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if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
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/*
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* Enable secondary SerDes and its use as an LED source
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*/
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reg = bcm54xx_shadow_read(phydev, BCM5482_SHD_SSD);
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bcm54xx_shadow_write(phydev, BCM5482_SHD_SSD,
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reg |
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BCM5482_SHD_SSD_LEDM |
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BCM5482_SHD_SSD_EN);
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/*
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* Enable SGMII slave mode and auto-detection
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*/
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reg = bcm54xx_exp_read(phydev, 1, BCM5482_SSD_SGMII_SLAVE);
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bcm54xx_exp_write(phydev, 1, BCM5482_SSD_SGMII_SLAVE,
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reg |
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BCM5482_SSD_SGMII_SLAVE_EN |
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BCM5482_SSD_SGMII_SLAVE_AD);
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/*
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* Disable secondary SerDes powerdown
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*/
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reg = bcm54xx_exp_read(phydev, 1, BCM5482_SSD_1000BX_CTL);
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bcm54xx_exp_write(phydev, 1, BCM5482_SSD_1000BX_CTL,
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reg & ~BCM5482_SSD_1000BX_CTL_PWRDOWN);
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/*
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* Select 1000BASE-X register set (primary SerDes)
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*/
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reg = bcm54xx_shadow_read(phydev, BCM5482_SHD_MODE);
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bcm54xx_shadow_write(phydev, BCM5482_SHD_MODE,
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reg | BCM5482_SHD_MODE_1000BX);
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/*
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* LED1=ACTIVITYLED, LED3=LINKSPD[2]
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* (Use LED1 as secondary SerDes ACTIVITY LED)
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*/
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bcm54xx_shadow_write(phydev, BCM5482_SHD_LEDS1,
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BCM5482_SHD_LEDS1_LED1(BCM_LED_SRC_ACTIVITYLED) |
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BCM5482_SHD_LEDS1_LED3(BCM_LED_SRC_LINKSPD2));
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/*
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* Auto-negotiation doesn't seem to work quite right
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* in this mode, so we disable it and force it to the
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* right speed/duplex setting. Only 'link status'
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* is important.
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*/
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phydev->autoneg = AUTONEG_DISABLE;
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phydev->speed = SPEED_1000;
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phydev->duplex = DUPLEX_FULL;
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}
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return err;
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}
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static int bcm5482_read_status(struct phy_device *phydev)
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{
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int err;
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err = genphy_read_status(phydev);
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if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
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/*
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* Only link status matters for 1000Base-X mode, so force
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* 1000 Mbit/s full-duplex status
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*/
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if (phydev->link) {
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phydev->speed = SPEED_1000;
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phydev->duplex = DUPLEX_FULL;
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}
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}
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return err;
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}
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static int bcm54xx_ack_interrupt(struct phy_device *phydev)
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{
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int reg;
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/* Clear pending interrupts. */
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reg = phy_read(phydev, MII_BCM54XX_ISR);
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if (reg < 0)
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return reg;
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return 0;
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}
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static int bcm54xx_config_intr(struct phy_device *phydev)
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{
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int reg, err;
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reg = phy_read(phydev, MII_BCM54XX_ECR);
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if (reg < 0)
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return reg;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
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reg &= ~MII_BCM54XX_ECR_IM;
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else
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reg |= MII_BCM54XX_ECR_IM;
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err = phy_write(phydev, MII_BCM54XX_ECR, reg);
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return err;
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}
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static int bcm5481_config_aneg(struct phy_device *phydev)
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{
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int ret;
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/* Aneg firsly. */
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ret = genphy_config_aneg(phydev);
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/* Then we can set up the delay. */
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
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u16 reg;
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/*
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* There is no BCM5481 specification available, so down
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* here is everything we know about "register 0x18". This
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* at least helps BCM5481 to successfuly receive packets
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* on MPC8360E-RDK board. Peter Barada <peterb@logicpd.com>
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* says: "This sets delay between the RXD and RXC signals
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* instead of using trace lengths to achieve timing".
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*/
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/* Set RDX clk delay. */
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reg = 0x7 | (0x7 << 12);
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phy_write(phydev, 0x18, reg);
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reg = phy_read(phydev, 0x18);
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/* Set RDX-RXC skew. */
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reg |= (1 << 8);
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/* Write bits 14:0. */
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reg |= (1 << 15);
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phy_write(phydev, 0x18, reg);
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}
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return ret;
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}
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static struct phy_driver bcm5411_driver = {
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.phy_id = 0x00206070,
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.phy_id_mask = 0xfffffff0,
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.name = "Broadcom BCM5411",
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.features = PHY_GBIT_FEATURES,
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.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
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.config_init = bcm54xx_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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.ack_interrupt = bcm54xx_ack_interrupt,
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.config_intr = bcm54xx_config_intr,
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.driver = { .owner = THIS_MODULE },
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};
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static struct phy_driver bcm5421_driver = {
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.phy_id = 0x002060e0,
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.phy_id_mask = 0xfffffff0,
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.name = "Broadcom BCM5421",
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.features = PHY_GBIT_FEATURES,
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.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
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.config_init = bcm54xx_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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.ack_interrupt = bcm54xx_ack_interrupt,
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.config_intr = bcm54xx_config_intr,
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.driver = { .owner = THIS_MODULE },
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};
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static struct phy_driver bcm5461_driver = {
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.phy_id = 0x002060c0,
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.phy_id_mask = 0xfffffff0,
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.name = "Broadcom BCM5461",
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.features = PHY_GBIT_FEATURES,
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.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
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.config_init = bcm54xx_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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.ack_interrupt = bcm54xx_ack_interrupt,
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.config_intr = bcm54xx_config_intr,
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.driver = { .owner = THIS_MODULE },
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};
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static struct phy_driver bcm5464_driver = {
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.phy_id = 0x002060b0,
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.phy_id_mask = 0xfffffff0,
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.name = "Broadcom BCM5464",
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.features = PHY_GBIT_FEATURES,
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.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
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.config_init = bcm54xx_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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.ack_interrupt = bcm54xx_ack_interrupt,
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.config_intr = bcm54xx_config_intr,
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.driver = { .owner = THIS_MODULE },
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};
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static struct phy_driver bcm5481_driver = {
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.phy_id = 0x0143bca0,
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.phy_id_mask = 0xfffffff0,
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.name = "Broadcom BCM5481",
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.features = PHY_GBIT_FEATURES,
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.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
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.config_init = bcm54xx_config_init,
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.config_aneg = bcm5481_config_aneg,
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.read_status = genphy_read_status,
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.ack_interrupt = bcm54xx_ack_interrupt,
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.config_intr = bcm54xx_config_intr,
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.driver = { .owner = THIS_MODULE },
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};
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static struct phy_driver bcm5482_driver = {
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.phy_id = 0x0143bcb0,
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.phy_id_mask = 0xfffffff0,
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.name = "Broadcom BCM5482",
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.features = PHY_GBIT_FEATURES,
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.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
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.config_init = bcm5482_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = bcm5482_read_status,
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.ack_interrupt = bcm54xx_ack_interrupt,
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.config_intr = bcm54xx_config_intr,
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.driver = { .owner = THIS_MODULE },
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};
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static int __init broadcom_init(void)
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{
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int ret;
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ret = phy_driver_register(&bcm5411_driver);
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if (ret)
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goto out_5411;
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ret = phy_driver_register(&bcm5421_driver);
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if (ret)
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goto out_5421;
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ret = phy_driver_register(&bcm5461_driver);
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if (ret)
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goto out_5461;
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ret = phy_driver_register(&bcm5464_driver);
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if (ret)
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goto out_5464;
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ret = phy_driver_register(&bcm5481_driver);
|
|
if (ret)
|
|
goto out_5481;
|
|
ret = phy_driver_register(&bcm5482_driver);
|
|
if (ret)
|
|
goto out_5482;
|
|
return ret;
|
|
|
|
out_5482:
|
|
phy_driver_unregister(&bcm5481_driver);
|
|
out_5481:
|
|
phy_driver_unregister(&bcm5464_driver);
|
|
out_5464:
|
|
phy_driver_unregister(&bcm5461_driver);
|
|
out_5461:
|
|
phy_driver_unregister(&bcm5421_driver);
|
|
out_5421:
|
|
phy_driver_unregister(&bcm5411_driver);
|
|
out_5411:
|
|
return ret;
|
|
}
|
|
|
|
static void __exit broadcom_exit(void)
|
|
{
|
|
phy_driver_unregister(&bcm5482_driver);
|
|
phy_driver_unregister(&bcm5481_driver);
|
|
phy_driver_unregister(&bcm5464_driver);
|
|
phy_driver_unregister(&bcm5461_driver);
|
|
phy_driver_unregister(&bcm5421_driver);
|
|
phy_driver_unregister(&bcm5411_driver);
|
|
}
|
|
|
|
module_init(broadcom_init);
|
|
module_exit(broadcom_exit);
|