![Stephen Neuendorffer](/assets/img/avatar_default.png)
Both the buffer-based and fifo-based icap cores have a status register. Previously, this was only used internally to check whether transactions have completed. However, the status can be useful to the main driver as well. This patch exposes these status functions to the main driver along with some masks for the differnet bits. Signed-off-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
397 lines
12 KiB
C
397 lines
12 KiB
C
/*****************************************************************************
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*
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* Author: Xilinx, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
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* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
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* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
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* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
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* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
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* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
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* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
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* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
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* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
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* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
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* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
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* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE.
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*
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* Xilinx products are not intended for use in life support appliances,
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* devices, or systems. Use in such applications is expressly prohibited.
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*
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* (c) Copyright 2007-2008 Xilinx Inc.
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* All rights reserved.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*****************************************************************************/
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#include "fifo_icap.h"
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/* Register offsets for the XHwIcap device. */
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#define XHI_GIER_OFFSET 0x1C /* Device Global Interrupt Enable Reg */
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#define XHI_IPISR_OFFSET 0x20 /* Interrupt Status Register */
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#define XHI_IPIER_OFFSET 0x28 /* Interrupt Enable Register */
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#define XHI_WF_OFFSET 0x100 /* Write FIFO */
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#define XHI_RF_OFFSET 0x104 /* Read FIFO */
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#define XHI_SZ_OFFSET 0x108 /* Size Register */
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#define XHI_CR_OFFSET 0x10C /* Control Register */
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#define XHI_SR_OFFSET 0x110 /* Status Register */
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#define XHI_WFV_OFFSET 0x114 /* Write FIFO Vacancy Register */
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#define XHI_RFO_OFFSET 0x118 /* Read FIFO Occupancy Register */
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/* Device Global Interrupt Enable Register (GIER) bit definitions */
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#define XHI_GIER_GIE_MASK 0x80000000 /* Global Interrupt enable Mask */
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/**
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* HwIcap Device Interrupt Status/Enable Registers
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*
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* Interrupt Status Register (IPISR) : This register holds the
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* interrupt status flags for the device. These bits are toggle on
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* write.
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*
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* Interrupt Enable Register (IPIER) : This register is used to enable
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* interrupt sources for the device.
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* Writing a '1' to a bit enables the corresponding interrupt.
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* Writing a '0' to a bit disables the corresponding interrupt.
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*
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* IPISR/IPIER registers have the same bit definitions and are only defined
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* once.
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*/
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#define XHI_IPIXR_RFULL_MASK 0x00000008 /* Read FIFO Full */
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#define XHI_IPIXR_WEMPTY_MASK 0x00000004 /* Write FIFO Empty */
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#define XHI_IPIXR_RDP_MASK 0x00000002 /* Read FIFO half full */
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#define XHI_IPIXR_WRP_MASK 0x00000001 /* Write FIFO half full */
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#define XHI_IPIXR_ALL_MASK 0x0000000F /* Mask of all interrupts */
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/* Control Register (CR) */
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#define XHI_CR_SW_RESET_MASK 0x00000008 /* SW Reset Mask */
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#define XHI_CR_FIFO_CLR_MASK 0x00000004 /* FIFO Clear Mask */
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#define XHI_CR_READ_MASK 0x00000002 /* Read from ICAP to FIFO */
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#define XHI_CR_WRITE_MASK 0x00000001 /* Write from FIFO to ICAP */
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#define XHI_WFO_MAX_VACANCY 1024 /* Max Write FIFO Vacancy, in words */
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#define XHI_RFO_MAX_OCCUPANCY 256 /* Max Read FIFO Occupancy, in words */
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/* The maximum amount we can request from fifo_icap_get_configuration
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at once, in bytes. */
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#define XHI_MAX_READ_TRANSACTION_WORDS 0xFFF
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/**
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* fifo_icap_fifo_write - Write data to the write FIFO.
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* @drvdata: a pointer to the drvdata.
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* @data: the 32-bit value to be written to the FIFO.
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*
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* This function will silently fail if the fifo is full.
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**/
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static inline void fifo_icap_fifo_write(struct hwicap_drvdata *drvdata,
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u32 data)
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{
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dev_dbg(drvdata->dev, "fifo_write: %x\n", data);
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out_be32(drvdata->base_address + XHI_WF_OFFSET, data);
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}
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/**
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* fifo_icap_fifo_read - Read data from the Read FIFO.
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* @drvdata: a pointer to the drvdata.
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*
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* This function will silently fail if the fifo is empty.
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**/
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static inline u32 fifo_icap_fifo_read(struct hwicap_drvdata *drvdata)
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{
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u32 data = in_be32(drvdata->base_address + XHI_RF_OFFSET);
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dev_dbg(drvdata->dev, "fifo_read: %x\n", data);
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return data;
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}
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/**
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* fifo_icap_set_read_size - Set the the size register.
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* @drvdata: a pointer to the drvdata.
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* @data: the size of the following read transaction, in words.
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**/
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static inline void fifo_icap_set_read_size(struct hwicap_drvdata *drvdata,
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u32 data)
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{
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out_be32(drvdata->base_address + XHI_SZ_OFFSET, data);
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}
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/**
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* fifo_icap_start_config - Initiate a configuration (write) to the device.
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* @drvdata: a pointer to the drvdata.
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**/
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static inline void fifo_icap_start_config(struct hwicap_drvdata *drvdata)
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{
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out_be32(drvdata->base_address + XHI_CR_OFFSET, XHI_CR_WRITE_MASK);
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dev_dbg(drvdata->dev, "configuration started\n");
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}
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/**
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* fifo_icap_start_readback - Initiate a readback from the device.
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* @drvdata: a pointer to the drvdata.
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**/
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static inline void fifo_icap_start_readback(struct hwicap_drvdata *drvdata)
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{
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out_be32(drvdata->base_address + XHI_CR_OFFSET, XHI_CR_READ_MASK);
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dev_dbg(drvdata->dev, "readback started\n");
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}
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/**
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* fifo_icap_get_status - Get the contents of the status register.
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* @drvdata: a pointer to the drvdata.
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*
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* The status register contains the ICAP status and the done bit.
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*
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* D8 - cfgerr
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* D7 - dalign
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* D6 - rip
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* D5 - in_abort_l
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* D4 - Always 1
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* D3 - Always 1
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* D2 - Always 1
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* D1 - Always 1
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* D0 - Done bit
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**/
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u32 fifo_icap_get_status(struct hwicap_drvdata *drvdata)
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{
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u32 status = in_be32(drvdata->base_address + XHI_SR_OFFSET);
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dev_dbg(drvdata->dev, "Getting status = %x\n", status);
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return status;
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}
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/**
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* fifo_icap_busy - Return true if the ICAP is still processing a transaction.
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* @drvdata: a pointer to the drvdata.
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**/
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static inline u32 fifo_icap_busy(struct hwicap_drvdata *drvdata)
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{
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u32 status = in_be32(drvdata->base_address + XHI_SR_OFFSET);
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return (status & XHI_SR_DONE_MASK) ? 0 : 1;
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}
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/**
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* fifo_icap_write_fifo_vacancy - Query the write fifo available space.
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* @drvdata: a pointer to the drvdata.
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*
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* Return the number of words that can be safely pushed into the write fifo.
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**/
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static inline u32 fifo_icap_write_fifo_vacancy(
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struct hwicap_drvdata *drvdata)
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{
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return in_be32(drvdata->base_address + XHI_WFV_OFFSET);
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}
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/**
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* fifo_icap_read_fifo_occupancy - Query the read fifo available data.
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* @drvdata: a pointer to the drvdata.
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*
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* Return the number of words that can be safely read from the read fifo.
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**/
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static inline u32 fifo_icap_read_fifo_occupancy(
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struct hwicap_drvdata *drvdata)
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{
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return in_be32(drvdata->base_address + XHI_RFO_OFFSET);
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}
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/**
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* fifo_icap_set_configuration - Send configuration data to the ICAP.
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* @drvdata: a pointer to the drvdata.
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* @frame_buffer: a pointer to the data to be written to the
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* ICAP device.
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* @num_words: the number of words (32 bit) to write to the ICAP
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* device.
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* This function writes the given user data to the Write FIFO in
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* polled mode and starts the transfer of the data to
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* the ICAP device.
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**/
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int fifo_icap_set_configuration(struct hwicap_drvdata *drvdata,
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u32 *frame_buffer, u32 num_words)
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{
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u32 write_fifo_vacancy = 0;
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u32 retries = 0;
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u32 remaining_words;
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dev_dbg(drvdata->dev, "fifo_set_configuration\n");
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/*
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* Check if the ICAP device is Busy with the last Read/Write
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*/
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if (fifo_icap_busy(drvdata))
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return -EBUSY;
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/*
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* Set up the buffer pointer and the words to be transferred.
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*/
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remaining_words = num_words;
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while (remaining_words > 0) {
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/*
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* Wait until we have some data in the fifo.
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*/
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while (write_fifo_vacancy == 0) {
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write_fifo_vacancy =
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fifo_icap_write_fifo_vacancy(drvdata);
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retries++;
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if (retries > XHI_MAX_RETRIES)
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return -EIO;
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}
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/*
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* Write data into the Write FIFO.
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*/
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while ((write_fifo_vacancy != 0) &&
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(remaining_words > 0)) {
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fifo_icap_fifo_write(drvdata, *frame_buffer);
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remaining_words--;
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write_fifo_vacancy--;
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frame_buffer++;
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}
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/* Start pushing whatever is in the FIFO into the ICAP. */
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fifo_icap_start_config(drvdata);
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}
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/* Wait until the write has finished. */
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while (fifo_icap_busy(drvdata)) {
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retries++;
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if (retries > XHI_MAX_RETRIES)
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break;
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}
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dev_dbg(drvdata->dev, "done fifo_set_configuration\n");
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/*
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* If the requested number of words have not been read from
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* the device then indicate failure.
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*/
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if (remaining_words != 0)
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return -EIO;
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return 0;
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}
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/**
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* fifo_icap_get_configuration - Read configuration data from the device.
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* @drvdata: a pointer to the drvdata.
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* @data: Address of the data representing the partial bitstream
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* @size: the size of the partial bitstream in 32 bit words.
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*
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* This function reads the specified number of words from the ICAP device in
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* the polled mode.
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*/
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int fifo_icap_get_configuration(struct hwicap_drvdata *drvdata,
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u32 *frame_buffer, u32 num_words)
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{
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u32 read_fifo_occupancy = 0;
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u32 retries = 0;
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u32 *data = frame_buffer;
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u32 remaining_words;
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u32 words_to_read;
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dev_dbg(drvdata->dev, "fifo_get_configuration\n");
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/*
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* Check if the ICAP device is Busy with the last Write/Read
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*/
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if (fifo_icap_busy(drvdata))
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return -EBUSY;
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remaining_words = num_words;
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while (remaining_words > 0) {
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words_to_read = remaining_words;
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/* The hardware has a limit on the number of words
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that can be read at one time. */
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if (words_to_read > XHI_MAX_READ_TRANSACTION_WORDS)
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words_to_read = XHI_MAX_READ_TRANSACTION_WORDS;
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remaining_words -= words_to_read;
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fifo_icap_set_read_size(drvdata, words_to_read);
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fifo_icap_start_readback(drvdata);
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while (words_to_read > 0) {
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/* Wait until we have some data in the fifo. */
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while (read_fifo_occupancy == 0) {
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read_fifo_occupancy =
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fifo_icap_read_fifo_occupancy(drvdata);
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retries++;
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if (retries > XHI_MAX_RETRIES)
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return -EIO;
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}
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if (read_fifo_occupancy > words_to_read)
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read_fifo_occupancy = words_to_read;
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words_to_read -= read_fifo_occupancy;
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/* Read the data from the Read FIFO. */
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while (read_fifo_occupancy != 0) {
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*data++ = fifo_icap_fifo_read(drvdata);
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read_fifo_occupancy--;
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}
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}
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}
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dev_dbg(drvdata->dev, "done fifo_get_configuration\n");
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return 0;
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}
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/**
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* buffer_icap_reset - Reset the logic of the icap device.
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* @drvdata: a pointer to the drvdata.
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*
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* This function forces the software reset of the complete HWICAP device.
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* All the registers will return to the default value and the FIFO is also
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* flushed as a part of this software reset.
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*/
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void fifo_icap_reset(struct hwicap_drvdata *drvdata)
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{
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u32 reg_data;
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/*
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* Reset the device by setting/clearing the RESET bit in the
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* Control Register.
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*/
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reg_data = in_be32(drvdata->base_address + XHI_CR_OFFSET);
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out_be32(drvdata->base_address + XHI_CR_OFFSET,
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reg_data | XHI_CR_SW_RESET_MASK);
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out_be32(drvdata->base_address + XHI_CR_OFFSET,
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reg_data & (~XHI_CR_SW_RESET_MASK));
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}
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/**
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* fifo_icap_flush_fifo - This function flushes the FIFOs in the device.
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* @drvdata: a pointer to the drvdata.
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*/
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void fifo_icap_flush_fifo(struct hwicap_drvdata *drvdata)
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{
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u32 reg_data;
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/*
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* Flush the FIFO by setting/clearing the FIFO Clear bit in the
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* Control Register.
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*/
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reg_data = in_be32(drvdata->base_address + XHI_CR_OFFSET);
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out_be32(drvdata->base_address + XHI_CR_OFFSET,
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reg_data | XHI_CR_FIFO_CLR_MASK);
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out_be32(drvdata->base_address + XHI_CR_OFFSET,
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reg_data & (~XHI_CR_FIFO_CLR_MASK));
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}
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